CN201349219Y

CN201349219Y - Asynchronous communication controller

Info

Publication number: CN201349219Y
Application number: CNU2008202384909U
Authority: CN
Inventors: 刘渝新
Original assignee: Chongqing Chuanyi Automation Co Ltd
Current assignee: Chongqing Chuanyi Automation Co Ltd
Priority date: 2008-12-21
Filing date: 2008-12-21
Publication date: 2009-11-18
Anticipated expiration: 2018-12-21

Abstract

The utility model relates to the UART asynchronous communication field, in particular to an asynchronous communication controller which comprises an interface module and a receiving module and a sending module which are respectively connected with the interface module, and further comprises a receiving-sending control module which is used for automatically recognizing frame addresses and automatically controlling the receiving and the sending directions, wherein the receiving-sending control module is respectively connected with the interface module, the receiving module and the sending module. The utility model can control direction control signals of half-duplex communication according to setting and resetting of the receiving-sending control module to receiving and sending state signs, makes the asynchronous communication controller utilize the receiving-sending control module to automatically recognize addresses of devices, and ensures whether to receive and response the information frame, and a CPU can not be frequently interrupted, and can realize high-speed asynchronous communication, which effectively improves transmission efficiency.

Description

Asynchronous communication controller

Technical field

The utility model relates to UART asynchronous communication field, particularly a kind of asynchronous communication controller.

Background technology

The common control chip of universal asynchronous communication has 16C450,16C550,16C750 etc.Interfaces such as 3 bit address buses, 8 bit address buses, read-write control bus can realize that baud rate setting, position of rest number are provided with, the setting of data bit number, have the various functions that report an error simultaneously.The high several megabits of universal asynchronous communication control chip traffic rate per second can realize high-speed communication.

When universal asynchronous communication controler is used for the RS485 multi-computer communication, particularly (as greater than 400KBPS) under the speed condition with higher, the asynchronous communication control chip has following shortcoming:

In order to judge whether to respond this Frame, CPU is interrupted continually so that whether judge message frame address is this machine address, and whether decision provides response.

RS485 receives, sending direction control needs CPU control.The control line of control communications reception, sending direction may make the RS485 driving interface be in transmit status all the time when cpu fault, causes bus by clamper, causes bus to lose efficacy.

The utility model content

The utility model has overcome above-mentioned shortcoming, and a kind of simple in structure, efficient, safe asynchronous communication controller of transmission is provided.

The technical scheme in the invention for solving the technical problem is: a kind of asynchronous communication controller, comprise interface module and the receiver module and the sending module that link to each other with described interface module respectively, comprise that also being used for frame address discerns automatically, and automatic control receives, the reception of sending direction sends control module, and described reception sends control module and links to each other with interface module, receiver module, sending module respectively.

Also can comprise the Baud rate generator that is used for producing according to the setting of interface module the asynchronous communication baud rate, described Baud rate generator links to each other with described interface module, receiver module and sending module respectively.

Described interface module also can be provided with the 9th bit data bus as parity check.

The utility model carries out set according to reception transmission control module to transmission, accepting state sign or resets, just can control the direction control signal of half-duplex operation, and make asynchronous communication controller can utilize described reception to send control module automatic identification equipment address, and determine whether reception and respond this information frame, CPU can frequently not interrupted, can realize high-speed asynchronous communication, effectively raise efficiency of transmission.

Description of drawings

Fig. 1 is a theory diagram of the present utility model.

Embodiment

A kind of preferred embodiment of the present utility model, as shown in fig. 1, the utility model comprises interface module and the receiver module and the sending module that link to each other with described interface module respectively, comprise that also described reception sends control module and Baud rate generator, described Baud rate generator is used for the setting according to interface module, produce the Baud rate generator of asynchronous communication baud rate, offer receiver module and sending module, link to each other with interface module, receiver module, sending module respectively.Described reception sends control module and has the frame address comparing function, automatic identification that can the achieve frame address, and when half-duplex operation reception, the sending direction of automatic control data, drive the Data Receiving and the transmission of port.

Described interface module is the interface that receives, sends data, comprises various control registers, status register interface.The address of this machine equipment can be set simultaneously, be used for the multi-computer communication address and relatively discern.

Main signal instruction is as follows:

MCLK: master clock;

RESET: reset;

A: 3 of register address buses;

D: 8 of data/address buss;

WR: write line;

RD: read control line;

INT: interrupt signal;

PT: send parity check bit (constituting 9 write data buss) with the D signal port;

PR: receive parity check bit (constituting 9 place readings according to bus) with the D signal port;

SIN: serial input signals end

SOUT: serial output signal end;

TRCTRL: send, receive control signal during half-duplex work;

According to said structure, control procedure of the present utility model is as follows:

When the reception information frame began, set information frame accepting state sign began to receive first byte by interface module.After first byte receives, described reception sends control module the content of this machine address register of storing in the byte content that receives and the described interface module is compared, if it is identical then open this information frame receiving key, receive the other guide of this information frame, if difference then close this information frame receiving key stops the other guide that receives this information frame.When first byte that transmits frame is the address, but the achieve frame address is discerned automatically.When the address of information frame is identical with this machine address, just receive this information frame.Realize the automatic recognition function of 8 bit address hardware, versatility is good, improves the operational efficiency of CPU simultaneously greatly.

During half-duplex operation, interface module can only be in and receive and send one of these two states, send control module by described reception and realize the direction controlled function, can finish direction control automatically when half-duplex is worked, the reception of information, sending direction need not be intervened by CPU.Detailed process is, after the initialization, whether receive and send the control module inspection is that frame receives beginning or is frame transmission beginning, if frame receives beginning, receive and send control module set frame accepting state sign, check then whether frame receives, do not receive the data representation received frame when 3 characters and finish, at this moment receive and send control module reset frame accepting state sign, receive loop ends.If frame sends beginning, receive and send control module set frame transmit status sign, check then whether frame sends to finish, send the data representation transmit frame and finish when 3 characters monitor, at this moment receive and send control module reset frame transmit status sign.Detect, carry out this two processes by above-mentioned circulation.According to receive to send control module to send, the accepting state sign carries out set or resets, and just can control the direction control signal of half-duplex operation.Can control reception, sending direction automatically, need not CPU and intervene, make the simplification of communication drivers Interface design, safety, efficient.

In addition, described interface module also is provided with the 9th bit data bus as parity check, and the 9th is to send, receive the data parity check position, improves the reliability of data and CPU parallel transmission.

More than asynchronous communication controller provided by the utility model is described in detail, used specific case herein principle of the present utility model and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model.

Claims

1. asynchronous communication controller, comprise interface module and the receiver module and the sending module that link to each other with described interface module respectively, it is characterized in that: comprise that also being used for frame address discerns automatically, and automatic control receives, the reception of sending direction sends control module, and described reception sends control module and links to each other with interface module, receiver module, sending module respectively.

2. asynchronous communication controller according to claim 1, it is characterized in that: also comprise the Baud rate generator that is used for producing according to the setting of interface module the asynchronous communication baud rate, described Baud rate generator links to each other with described interface module, receiver module and sending module respectively.

3. asynchronous communication controller according to claim 1 and 2 is characterized in that: described interface module also is provided with the 9th bit data bus as parity check.