CN201251437Y - CCD video real-time display - Google Patents
CCD video real-time display Download PDFInfo
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- CN201251437Y CN201251437Y CNU2008201869052U CN200820186905U CN201251437Y CN 201251437 Y CN201251437 Y CN 201251437Y CN U2008201869052 U CNU2008201869052 U CN U2008201869052U CN 200820186905 U CN200820186905 U CN 200820186905U CN 201251437 Y CN201251437 Y CN 201251437Y
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Abstract
The utility model relates to a CCD video real-time display device which belongs to the field of video real-time display, and comprises a single chip, an FPGA, a CCD camera, an SRAM buffer memory chip and a video encoder, wherein, the FPGA comprises a camera control unit, an FIFO memorizer, a data pick-up unit, an SRAM controller and a data packing unit; the single chip is respectively connected with the camera controller, the data pick-up unit and the video encoder. The camera control unit is connected with the CCD camera; after being output to the FIFO memorizer and is buffered, the data of the CCD camera is input into the data pick-up unit and is output to the SRAM buffer memory chip through the data pick-up unit; the SRAM buffer memory chip realizes reading-writing operation through the SRAM controller and outputs the data to the data packing unit; and the data packing unit is connected with the video encoder. The utility model realizes the high-definition video display under the condition that the frame rate of the CCD camera is changeable, has the advantage of good real-time effect and is suitable for all CCD cameras with different resolutions.
Description
Technical field
The utility model relates to a kind of CCD real-time video display device, belongs to real-time video and shows the field.
Background technology
In the photogrammetric measurement system, often adopt high-speed CCD camera object to be taken continuously in the high-altitude.Usual way is under the situation that CCD camera frame frequency is fixed at present, realizes the real-time shooting of fixed area is shown.Yet, in certain applications,, adjust the camera frame frequency in real time how according to external request, dynamically adjust the real-time monitored of window position realization simultaneously to area-of-interest, be the difficult point that realizes in the aerial survey system.How under the condition of frame frequency conversion, realize that high-resolution analog video real-time stabilization to the continuous high-speed CCD image data stream of magnanimity is presented at engineering and has vital role in using.
Summary of the invention
In order to solve usual method, the utility model proposes a kind of variable ratio frequency changer CCD real-time video display device only at the fixing problem of the real-time shooting demonstration of frame frequency fixed area.This device can be under the condition that CCD camera frame frequency constantly changes, and the variable high sharpness video in window position shows in real time.
Variable ratio frequency changer CCD real-time video display device of the present utility model, this device comprises single-chip microcomputer, programmable logic device (PLD) (FPGA), CCD camera, static memory (SRAM) cache chip and video encoder, and described programmable logic device (PLD) (FPGA) comprises camera control module, first-in first-out (FIFO) storer, data pick-up unit, static memory (SRAM) controller and packing data unit; Single-chip microcomputer receives external data information and window position information by serial ports, wherein external data information comprises flying height H, flying speed v, longitude information, latitude information, single-chip microcomputer connects camera control module, data pick-up unit and video encoder respectively, single-chip microcomputer obtains camera frame frequency value after the external data information that receives is calculated, give the camera control module camera frame frequency value then, and give the data pick-up unit with the window position information that receives, single-chip microcomputer is connected with video encoder, by the control of chip microcontroller to video encoder; The camera control module is connected with the CCD camera, and the camera control module produces the outer synchronization pulse of camera according to camera frame frequency value, controls the camera frame frequency by the outer synchronization pulse of this camera; The CCD camera data directly outputs to the FIFO storer, by the FIFO storer camera data is write the data pick-up unit; The data pick-up unit extracts data according to window position information, the data that extraction is obtained output to buffer memory in the sram cache chip, wherein the sram cache chip carries out read-write operation by the SRAM controller, by the SRAM controller, the data of data pick-up unit are sent into buffer memory in the sram cache chip, by the SRAM controller, sense data outputs to the packing data unit from the sram cache chip then; The packing data of packing data unit after with buffer memory is the hdtv video data form, the input end of the output termination video encoder of packing data unit, thereby realize the video data encoding after the packing is shown that the output terminal output video of video encoder shows output signal.
Single-chip microprocessor MCU receives external data information, calculates the camera frame frequency in real time according to data message; To calculate camera frame frequency value and input to FPGA, structure camera control module in FPGA, this control module produces the outer synchronization pulse of camera and inputs to the CCD camera, and the CCD camera is exported continuous data stream under the control of FPGA; The continuous data stream of CCD output enters the data pick-up unit of FPGA by the FIFO storer of FPGA, adopts local selection technology to realize that the variable data in real time in window position extracts so that to the real-time monitored of area-of-interest; Data after the extraction input to the sram cache chip, structure SRAM controller in FPGA, and the structure that adopts ping-pong buffer is to set up the coupling passage between the video code model of the ccd image data of frequency conversion and constant speed, realizes the buffer memory to data; Pure view data behind the buffer memory realizes being packaged as the 1080i hdtv video data packet format that meets the SMPTE274 standard through the packing data unit module in FPGA; Packed video data stream is encoded to it by video encoder (dedicated video coding chip) ADV7300A.I by single-chip microcomputer and ADV7300A chip
2The C interface communication realizes that finally the high-resolution analog video image shows.
The utility model has realized that the high sharpness video under CCD camera frame frequency contingent condition shows, has the good advantage of real-time and all suitable to different resolution CCD camera.
Description of drawings
Fig. 1 is a principle schematic of the present utility model.
Fig. 2 is that outer synchronization pulse of the present utility model produces synoptic diagram.
Fig. 3 is the process flow diagram of the utility model data extraction module.
Label title in the accompanying drawing: the outer synchronization pulse of EXSYNC---camera, twSYNC---smallest synchronization pulse.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail:
Fig. 1 is a principle schematic of the present utility model, this device comprises single-chip microcomputer, FPGA, CCD camera, sram cache chip and video encoder, and described FPGA comprises camera control module, FIFO storer, data pick-up unit, SRAM controller and packing data unit; Single-chip microcomputer receives external data information and window position information by serial ports, wherein external data information comprises flying height H, flying speed v, longitude information, latitude information, single-chip microcomputer connects camera control module, data pick-up unit and video encoder respectively, single-chip microcomputer obtains camera frame frequency value after the external data information that receives is calculated, give the camera control module camera frame frequency value then, and give the data pick-up unit with the window position information that receives, single-chip microcomputer is connected with video encoder, by the control of chip microcontroller to video encoder; The camera control module is connected with the CCD camera, and the camera control module produces the outer synchronization pulse of camera according to camera frame frequency value, controls the camera frame frequency by the outer synchronization pulse of this camera; The CCD camera data directly outputs to the FIFO storer, by the FIFO storer camera data is write the data pick-up unit; The data pick-up unit extracts data according to window position information, the data that extraction is obtained output to buffer memory in the sram cache chip, wherein the sram cache chip carries out read-write operation by the SRAM controller, by the SRAM controller, the data of data pick-up unit are sent into buffer memory in the sram cache chip, by the SRAM controller, sense data outputs to the packing data unit from the sram cache chip then; The packing data of packing data unit after with buffer memory is the hdtv video data form, the input end of the output termination video encoder of packing data unit, thereby realize the video data encoding after the packing is shown that the output terminal output video of video encoder shows output signal.
Single-chip microprocessor MCU receives external data information, calculates the camera frame frequency in real time according to data message; To calculate camera frame frequency value and input to FPGA, structure camera control module in FPGA, this control module produces the outer synchronization pulse of camera and inputs to the CCD camera, and the CCD camera is exported continuous data stream under the control of FPGA; The continuous data stream of CCD output enters the data pick-up unit of FPGA by the FIFO storer of FPGA, adopts local selection technology to realize that the variable data in real time in window position extracts so that to the real-time monitored of area-of-interest; Data after the extraction input to the sram cache chip, structure SRAM controller in FPGA, and the structure that adopts ping-pong buffer is to set up the coupling passage between the video code model of the ccd image data of frequency conversion and constant speed, realizes the buffer memory to data; Pure view data behind the buffer memory realizes being packaged as the 1080i hdtv video data packet format that meets the SMPTE274 standard through the packing data unit module in FPGA; Packed video data stream is encoded to it by video encoder (dedicated video coding chip) ADV7300A.I by single-chip microcomputer and ADV7300A chip
2The C interface communication realizes that finally the high-resolution analog video image shows.
Function and designing requirement according to device have proposed the hardware platform that combines with programmable logic device (PLD)+single-chip microcomputer (FPGA+MCU).Because it is very high that this device real-time requires, and simultaneously, need carry out handle up (up to the 80MHz) of mass data, for existing processor, it is very difficult carrying out the data of big handling capacity like this and handling in real time.Therefore, select the special processing unit of FPGA structure in the device for use, can utilize the abundant I/O pin of device to finish data throughput on the one hand, can utilize it to improve real-time on the other hand; Owing to need constantly to receive the data message that outside serial ports sends in the device and carry out some basic calculation process, wherein also relate to some floating-point operations, FPGA has very big deficiency in this respect, realizes that floating-point operation needs ample resources on the one hand, and very difficult; Also inconvenient for serial ports reception aspect in addition.Consider from these factors and business efficiency angle thereof, also selected for use a single-chip microcomputer (MCU) to finish the auxiliary control of serial ports reception, data operation and some others in the device.Based on this, this device adopt with FPGA is handle core, be the hardware platform of assisting with MCU.
The MCU single-chip microcomputer is mainly realized following three big functions: the data message computing camera frame frequency that receives outside serial ports; Receive outside window position information and input to FPGA; Control to video encoder.
Function one, and MCU reception external data information (longitude information, latitude information, flying height H, flying speed v) obtains current camera frame frequency value according to information calculations.Because the Refresh Data rate is higher, the accuracy that MCU receives data is to guarantee the precise and stable precondition of follow-up work.MCU mainly contains inquiry and interrupts dual mode the reception of data.Receiving data is under probabilistic condition, if adopt inquiry mode to take mcu resource too much, efficient is low, and causes losing of data easily when single-chip microcomputer is handled other tasks.Therefore, adopt interrupt mode to receive external data, not only can improve CPU efficient, can also finish reception in real time data.By the external data information of real-time reception, MCU calculates camera frame frequency with flying height and speed real time altering according to formula (1).Then, the frame frequency numerical value that obtains is inputed to FPGA.
The computing formula of CCD camera frame frequency is as follows:
Wherein f is a CCD camera frame frequency value, and H is a flying height, and v is a flying speed, and α is a field angle, q
xFor the adjacent picture in course (course) Duplication, get q here
x=60%, α=60 ° calculating.
Function two receives the outside window position information of sending and inputs to FPGA.For ease of real-time monitored, need Real-time and Dynamic to adjust window position information to area-of-interest.Therefore, window position information (line width, col width, start of line address and row start address) can be write single-chip microcomputer successively, and input to FPGA by the parallel port.
Function three realizes the control to video encoder.I by single-chip microcomputer
2The C bus interface, the communication of realization and video encoder chip by the correct configuration to the chip internal register, realizes the reality output of video coding.
FPGA comprises five unit: camera control module, FIFO storer, data pick-up unit, SRAM controller and packing data unit.
Wherein the camera control module is used to produce the outer synchronization pulse of camera.
This unit at first receives the camera frame frequency value that single-chip microcomputer calculates;
Utilize FPGA in the superiority of carrying out aspect the complex time sequence logic control then, obtain the pulsewidth of the outer synchronization pulse of camera, promptly produce the outer synchronization pulse EXSYNC of camera according to the frame frequency value.For example single-chip microcomputer is 0.25fps (frame per second) according to current information calculating frame frequency, illustrates that then shooting interval is 4s, and the pulsewidth that promptly will produce the outer synchronization pulse EXSYNC of this frame is 4s.Suppose the trigger pip of the negative edge of synchronization pulse EXSYNC beyond the camera as camera, then according to above-mentioned result of calculation, the outer synchronization pulse of the EXSYNC of generation as shown in Figure 2.
It should be noted that the negative edge that uses EXSYNC at camera as when triggering, must guarantee that the pulsewidth of smallest synchronization pulse twSYNC is at least 100ns.
At last, outer synchronization pulse EXSYNC is transferred to the CCD camera with the camera that produces, and then under the triggering of synchronizing pulse outside of CCD camera, finally exports camera data.
Therefore, whole camera Control work flow process is as follows:
At first, MCU receives external data information (flying height H, flying speed v, longitude information, latitude information), calculates current camera frame frequency value according to formula (1);
Then, the frame frequency numerical value that obtains is inputed to FPGA;
Utilize FPGA in the superiority of carrying out aspect the complex time sequence logic control again, produce the outer synchronization pulse EXSYNC of camera, and the outer synchronization pulse of this camera is transferred to the CCD camera according to the camera frame frequency value that receives;
At last, under the triggering of CCD camera synchronizing pulse outside camera, camera begins integration (exposure), after integration finishes, under the control of pixel clock, produces required field, and row etc. are signal synchronously, and camera data can be exported line by line.
The FIFO storer is used for the output data of buffer memory CCD camera, gives the data pick-up unit with this data transmission then.
The data pick-up unit is used to realize the real-time extraction to original CCD camera data.Fig. 3 is the process flow diagram of data pick-up unit:
Step 1, single-chip microcomputer receive outside window position information;
Step 2, the current window position information that MCU is received inputs to data pick-up unit among the FPGA by the parallel port;
Step 3 is in the window position information of data pick-up unit internal structure special register sum counter with the preservation reception; Special register is used to deposit start of line address, row start address, line width and col width; Counter then is used for realizing the row, column counting to image respectively; Structure ripple door discriminant function judges promptly to realize the detection to original ccd image data whether the current data position belongs in the window position in the data pick-up unit;
Wherein the implementation of discriminant function is as follows:
Suppose that start of line address is 16, the row start address is 128, and line width is 1920, and col width is 1080, and then row address is 16 to the scope of 16+1920, and column address is in the scope of 128+1080 the time, and discriminant function be true, otherwise is vacation;
Step 4, according to ripple door discriminant function with realize to the reservation of original ccd image data with give up; Concrete rule is as follows: as discriminant function is true, when promptly current count value is in the range of information of window position, is extracted for view data, otherwise is given up; Image data resolution size after extracting in real time is identical with high sharpness video valid data resolution.
The SRAM controller is used to realize the read/write control of FPGA to the sram cache chip.Here cache chip adopts the sram chip that Cypress company produces, and model is CY7C1010DV33.Though the data resolution size that retains after extracting in real time is identical with high sharpness video valid data resolution, but both are unequal on speed and frame frequency, camera data speed is 80MHz, frame frequency is a variable, it is 74.25MHz that the hdtv video data form is selected speed, frame frequency was 30 frame/seconds, and every frame is divided into the form of strange and idol, therefore need adapt to passage for one of structure between the video coding of the ccd image raw data of frequency conversion and constant speed.Here, adopt biplate sram cache structure, to the read-write operation of SRAM and the control of address, finish seamless buffering and processing data stream by FPGA.
It is the hdtv video data form that the packing data unit is realized the packing data behind the buffer memory.Because what read from data cache module is pure view data, therefore need in FPGA sense data is packaged as the hdtv video data form.Consider in system taking detailed information accuracy requirement height, select for use the 1080i high-resolution analog video format output that meets the SMPTE274 standard here.It has following principal feature:
1) valid data resolution is 1920 * 1080, and three quadrature components (luminance component Y, the first chromatic component C are arranged
bWith the second chromatic component C
r), and the compound form transmission of pressing 4:2:2, sampling clock speed is 74.25MHz.
2) two timing reference signals are respectively video data signal SAV (Start of Active Video), video data end-of-block signal EAV (End of Active Video).
3) frame frequency was 30 frame/seconds, every frame scan 1125 row.One frame data branch is made two of odd evens, is strange from 1124 row of previous frame to 560 row of this frame, and wherein going up frame 1124 row is strange vertical blanking periods to this frame 20 row, and being that very the field is effective from 21 row to 560 row goes; Is even from this frame 561 row to 1123 row, and wherein 561 to 583 row are even vertical blanking periods, 584 to 1123 behaviors idol effective row.
4) three synchronous input signal field sync signal F, line synchronizing signal H and blanking synchronizing signal V.Data are packed actual produce the padding data of header packet information, blanking interval and the data and the first chromatic component C of luminance component Y with FPGA exactly
b, the second chromatic component C
rData compound, further video data and header packet information, padding data are merged the final packet that meets above-mentioned definition format standard that produces again.
In the specific implementation process, FPGA will design two counters, and one is used for to the every trade counting of advancing, and one is used for the pixel of every row is counted.According to the value of two counters, write header packet information in corresponding place, fill out padding data at blanking interval, and in the valid pixel phase of effectively going, the output of FPGA is from the original camera data of sram cache chip output.Like this, the video data in FPGA is combined into module, and the clock of using 74.25MHz is with the luminance component Y and the first chromatic component C
b, the second chromatic component C
rComponent is combined into hdtv video data stream by the 4:2:2 form of call format.
Video encoder is realized the coding of packaged unit output video data is shown.Here the video data stream of selecting for use video coding chip ADV7300A to realize fighting each other after wrapping is encoded.Data after the packing are through the two-way scale-of-two synchronous serial bus (I of ADV7300A inside
2The C bus) transmission by the correct configuration of MCU to the inner read-write register of video encoder ADV7300A, realizes that finally the high-resolution analog video shows in real time.
Claims (2)
1, a kind of CCD real-time video display device, it is characterized in that: this device comprises single-chip microcomputer, FPGA, CCD camera, sram cache chip and video encoder, and described FPGA comprises camera control module, FIFO storer, data pick-up unit, SRAM controller and packing data unit; Single-chip microcomputer receives external data information and window position information by serial ports, single-chip microcomputer connects camera control module, data pick-up unit and video encoder respectively, single-chip microcomputer obtains camera frame frequency value after the external data information that receives is calculated, give the camera control module camera frame frequency value then, and give the data pick-up unit with the window position information that receives, single-chip microcomputer is connected with video encoder, by the control of chip microcontroller to video encoder; The camera control module is connected with the CCD camera, and the camera control module produces the outer synchronization pulse of camera according to camera frame frequency value, controls the camera frame frequency by the outer synchronization pulse of this camera; The CCD camera data directly outputs to the FIFO storer, by the FIFO storer camera data is write the data pick-up unit; The data pick-up unit extracts data according to window position information, the data that extraction is obtained output to buffer memory in the sram cache chip, wherein the sram cache chip carries out read-write operation by the SRAM controller, by the SRAM controller, the data of data pick-up unit are sent into buffer memory in the sram cache chip, by the SRAM controller, sense data outputs to the packing data unit from the sram cache chip then; The packing data of packing data unit after with buffer memory is the hdtv video data form, the input end of the output termination video encoder of packing data unit, thereby realize the video data encoding after the packing is shown that the output terminal output video of video encoder shows output signal.
2, a kind of CCD real-time video display device as claimed in claim 1, it is characterized in that: the sram cache chip is a biplate sram cache structure.
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| CNU2008201869052U CN201251437Y (en) | 2008-09-12 | 2008-09-12 | CCD video real-time display |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107079135A (en) * | 2016-01-29 | 2017-08-18 | 深圳市大疆创新科技有限公司 | Method of transmitting video data, system, equipment and filming apparatus |
| CN108897511A (en) * | 2018-07-05 | 2018-11-27 | 四川长九光电科技有限责任公司 | A method of it receiving different frame frequency images and is shown |
-
2008
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107079135A (en) * | 2016-01-29 | 2017-08-18 | 深圳市大疆创新科技有限公司 | Method of transmitting video data, system, equipment and filming apparatus |
| CN107079135B (en) * | 2016-01-29 | 2020-02-07 | 深圳市大疆创新科技有限公司 | Video data transmission method, system, equipment and shooting device |
| US10616480B2 (en) | 2016-01-29 | 2020-04-07 | SZ DJI Technology Co., Ltd. | Method, system, device for video data transmission and photographing apparatus |
| CN111182268A (en) * | 2016-01-29 | 2020-05-19 | 深圳市大疆创新科技有限公司 | Video data transmission method, system, equipment and shooting device |
| CN111182268B (en) * | 2016-01-29 | 2021-08-17 | 深圳市大疆创新科技有限公司 | Video data transmission method, system, equipment and shooting device |
| CN108897511A (en) * | 2018-07-05 | 2018-11-27 | 四川长九光电科技有限责任公司 | A method of it receiving different frame frequency images and is shown |
| CN108897511B (en) * | 2018-07-05 | 2021-03-05 | 四川长九光电科技有限责任公司 | Method for receiving and displaying images with different frame frequencies |
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Granted publication date: 20090603 Termination date: 20110912 |