CN1991788A - Method for treating broken block when using flash memory in tax-controlled cashing machine - Google Patents
Method for treating broken block when using flash memory in tax-controlled cashing machine Download PDFInfo
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- CN1991788A CN1991788A CN 200510121160 CN200510121160A CN1991788A CN 1991788 A CN1991788 A CN 1991788A CN 200510121160 CN200510121160 CN 200510121160 CN 200510121160 A CN200510121160 A CN 200510121160A CN 1991788 A CN1991788 A CN 1991788A
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Abstract
The invention relates to a bad block processing method using flash memory which is used in tax controlling cashier's machine, it resolves problems that the NANDFLASH can not be used in 8 bit singlechip system for its bad block, it adopts technique that during the processing cause, a mapping table between logic block and physical block is built, once there is bad block, new mapping will be formed in the head sector, when the p page of the programming logic X fails or unsuccessful to erasure some logic block Y, the bad block is identified first, then the max standby block BLK and its table address ADR are found out, programs or erasures BLK+1, the new physical address is filled into the mapping table. The method possesses advantages of simple practicality, easy to understand and realize few quantities of codes, fast running speed and stable, it is reliable to be used intax controlling cashier's machine.
Description
Technical field
The present invention relates to a kind of method of operating of in Single Chip Microcomputer (SCM) system, using flash memory, relate in particular to a kind of method of handling bad piece when in tax-control cash register, using flash memory.
Background technology
NANDFLASH is because its storage volume is big, wipe, writing rate is fast, in data storage system, used in a large number, because its interface class is similar to hard disk, to replacing the hard disk direction to develop, present electric board is as USB flash disk, DOC (disk on chip), smart card etc. all are to use NANDFLASH's.
At present, based on the system of 8 single-chip microcomputers, seldom have and to use NANDFLASH and do data storing.And based on 32 ARM kernels, the system of LINUX platform, the internal memory of use has several million even tens at least, also operation therein of program, dominant frequency is more than 70,000,000, and it is all masterly to run any algorithm.
That the chances are is such for its algorithm: at the 0th table of building a 2000*2, reserve 35 pieces from first BOB(beginning of block) and make stand-by block, list index points to the actual physical piece, but when having bad piece to take place, need read back the 0th 16K byte among the RAM, after in RAM, bad pointer being rewritten, wipe the 0th, the 16K byte is write back the 0th again.
And 8 bit single-chip systems, because the program quantitative limitation, the restriction of memory size, the restriction of frequency and can not being widely used.And NANDFLASH since the handling problem of bad piece can not well be applied on 8 bit single-chip systems.
Summary of the invention
The invention provides a kind of method of handling bad piece when in tax-control cash register, using flash memory for addressing the above problem, to realize that NANDFLASH is carried out bad block management.
Technical scheme provided by the invention is:, a kind of method of handling bad piece when in tax-control cash register, using flash memory, in the flash memory process process, set up the mapping table of a logical block and physical block in first sector, in case when having bad piece to take place, new mapping relations can directly be appended formation in first sector, when the failure of the P page or leaf of programmed logic piece X or wipe certain logical block Y when unsuccessful, make bad block identification earlier, find out maximum stand-by block BLK and table address ADR thereof again, the programming or wipe BLK+1 up to success, again the new physical block address is inserted in the mapping table.
Further improvement in the technical proposal is: when the P page or leaf failure of programmed logic piece X, also comprise copy preceding P-1 page data to this piece after, this piece number is write the step at ADR+2 place, also comprise and find out X*8 place page or leaf, from left to right begin to calculate, note the step of BLK value in the position that occurs FF at first.
Further improvement in the technical proposal is: also comprise the step that this piece BLK+N is write the ADR+2 place when unsuccessful wiping certain logical block Y, also comprise and find out Y*8 place page or leaf, from left to right begin to calculate, note the step of the value of BLK+N in the position that occurs FF at first.
Further improvement in the technical proposal is: also be included in a data field step that the flexible ECC of mistake carries out verification and corrects.
The invention has the beneficial effects as follows: based on the bad block management program of this method processing, procedure quantity is no more than 2K, the RAM use is no more than 30 bytes and is overlayable (not comprising the buffer zone that read data is used), do not need to do the relocating work of big data quantity, simple and practical, easy to understand and realization, it is few to take size of code, travelling speed is fast and stable, and this method is used on tax-control cash register, and system is solid.
Description of drawings
Fig. 1 is the process flow diagram of a programming embodiment of the present invention;
Fig. 2 is a process flow diagram of wiping embodiment of the present invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments
Be example with a capacity 32M flash memory now, this flash memory is divided into 2048 pieces, and every is divided into 32 pages again, the 512+16B byte is arranged on every page, and wherein preceding 512 bytes generally are used for store data, and back 16B is used for depositing check code and bad block mark.So Capacity design is become to have 2000 logical blocks, every 32 pages, every page 512 byte, special reason piece 0 is deposited mapping table, and last 47 are the mapping stand-by block.The mapping table design of above-mentioned flash memory is as follows
A. rule: the physical block address of chip obtains by the mapping table in the 0th, if a slice chip has 47 bad pieces of surpassing, or certain corresponding blocks has been gone bad 4 times continuously and be not simultaneously bad, thinks that chip is bad;
B. the 0th has: 16384B, and each logical block takies 8 bytes, represents its first, the second, the three, the four stand-by block respectively, can only go bad at most four times for every thus;
C. in the following table, blueness is mapping block address (piece 0), and red is the physical block that this logical block shone upon;
D. the physical block of logical block 3 be 2001 (0 * 7d1), because of physical block 3 bad.
E. the physical block of logical block 2000 be 2005 (0 * 7d5), because of physical block 2000 and physics bad 2002 successively all bad.
| 00H | 01H | 02H | 03H | 04H | 05H | 06H | 07H | Piece 1 |
| FF | FF | FF | FF | FF | FF | FF | FF | |
| 08H | 09H | 0AH | 0BH | 0CH | 0DH | 0EH | 0FH | Piece 2 |
| FF | FF | FF | FF | FF | FF | FF | FF | |
| 10H | 11H | 12H | 13H | 14H | 15H | 16H | 17H | Piece 3 |
| 07 | D1 | FF | FF | FF | FF | FF | FF | |
| …………………………………………………………… | ||||||||
| 3E78H (15992) | 3E79H (15993) | 3E7AH (15994) | 3E7BH (15995) | 3E7CH (15996) | 3E7DH (15997) | 3E7EH (15998) | 3E7FH (15999) | Piece 2000 |
| 07 | D2 | 07 | D5 | FF | FF | FF | FF | |
F. used the largest block number of stand-by block with the 0th the 31st page back 256B record, as when formaing three bad pieces being arranged, then at 3F00, the value of 3F01 is 07H, D1H (2001); 3F02, the value of 3F03 is 07H, D2H (2002); 3F04, the value of 3F05 is 07H, D3H (2003) does not format the physical block after 2000, handles in the application (can not operate then after the mapping and abandon).
As shown in Figure 1, when the P page or leaf failure of programmed logic piece X, carry out bad block identification earlier, and find out maximum stand-by block BLK and table address ADR thereof, the P page or leaf of this piece of programming, the failure again with BLK+1 up to success, after copying preceding P-1 page data to this piece, this piece number is write the ADR+2 place.Find out X*8 place page or leaf simultaneously, from left to right begin to calculate, note BLK value,, point out FLASH bad if 8 bytes are non-FF entirely in the position that occurs FF at first.(because be to roll to have stored in using, the possibility that occurs in this situation practical application is extremely low), a flexible ECC of mistake carries out verification and corrects in the data field then.
In the another embodiment of the present invention, as shown in Figure 2, wiping certain logical block Y when unsuccessful, equally, make bad block identification earlier, find out maximum stand-by block BLK and table address ADR thereof again, wipe BLK+1 again up to success, BLK+N writes the ADR+2 place with this piece, finds out Y*8 place page or leaf simultaneously, from left to right begins to calculate, note the value of BLK+N in the position that occurs FF at first, if 8 bytes are non-FF entirely, FLASH is bad in prompting, and a flexible ECC of mistake carries out verification and corrects in the data field then.
Claims (6)
1, a kind of method of handling bad piece when in tax-control cash register, using flash memory, in the flash memory process process, set up the mapping table of a logical block and physical block in first sector, in case when having bad piece to take place, new mapping relations can directly be appended formation in first sector, when the failure of the P page or leaf of programmed logic piece X or wipe certain logical block Y when unsuccessful, make bad block identification earlier, find out maximum stand-by block BLK and table address ADR thereof again, the programming or wipe BLK+1 up to success, again the new physical block address is inserted in the mapping table.
2. the method for handling bad piece when using flash memory in tax-control cash register as claimed in claim 1 is characterized in that: when the P page or leaf failure of programmed logic piece X, also comprise copy preceding P-1 page data to this piece after, this piece number is write the step at ADR+2 place.
3, the method for handling bad piece when using flash memory in tax-control cash register as claimed in claim 2 is characterized in that: also comprise and find out X*8 place page or leaf, from left to right begin to calculate, note the step of BLK value in the position that occurs FF at first.
4, the method for handling bad piece when using flash memory in tax-control cash register as claimed in claim 1 is characterized in that: also comprise the step that this piece BLK+N is write the ADR+2 place when unsuccessful wiping certain logical block Y.
5, the method for handling bad piece when using flash memory in tax-control cash register as claimed in claim 4 is characterized in that: also comprise and find out Y*8 place page or leaf, from left to right begin to calculate, note the step of the value of BLK+N in the position that occurs FF at first.
6, as any one described method of handling bad piece when in tax-control cash register, using flash memory of claim 1-5, it is characterized in that: also be included in a data field step that the flexible ECC of mistake carries out verification and corrects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101211602A CN100456263C (en) | 2005-12-30 | 2005-12-30 | Method for treating broken block when using flash memory in tax-controlled cashing machine |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101211602A CN100456263C (en) | 2005-12-30 | 2005-12-30 | Method for treating broken block when using flash memory in tax-controlled cashing machine |
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| CN1991788A true CN1991788A (en) | 2007-07-04 |
| CN100456263C CN100456263C (en) | 2009-01-28 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944065A (en) * | 2010-08-24 | 2011-01-12 | 苏州国芯科技有限公司 | Flash memory bad block shielding method based on section |
| CN101593157B (en) * | 2008-05-27 | 2011-03-16 | 中兴通讯股份有限公司 | Bad block management (BBM) method and device for Nand Flash |
| CN101441552B (en) * | 2007-11-19 | 2012-05-23 | 深圳市朗科科技股份有限公司 | Flash memory medium bad block processing method |
| CN102541676A (en) * | 2011-12-22 | 2012-07-04 | 福建新大陆通信科技股份有限公司 | Method for detecting and mapping states of NAND FLASH |
| CN104166627A (en) * | 2014-09-02 | 2014-11-26 | 科大智能电气技术有限公司 | NAND-FLASH writing operation method based on single-chip microcomputer |
| CN108573735A (en) * | 2017-03-08 | 2018-09-25 | 北京兆易创新科技股份有限公司 | A kind of the block restorative procedure and device of NAND-FLASH |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6260156B1 (en) * | 1998-12-04 | 2001-07-10 | Datalight, Inc. | Method and system for managing bad areas in flash memory |
| US6895464B2 (en) * | 2002-06-03 | 2005-05-17 | Honeywell International Inc. | Flash memory management system and method utilizing multiple block list windows |
| KR20040072875A (en) * | 2003-02-11 | 2004-08-19 | 유비시스테크놀러지 주식회사 | Storage using nand flash memory |
| KR100526186B1 (en) * | 2003-04-04 | 2005-11-03 | 삼성전자주식회사 | Method and apparatus for managing bad block in flash memory |
| KR100526188B1 (en) * | 2003-12-30 | 2005-11-04 | 삼성전자주식회사 | Method for address mapping and managing mapping information, and flash memory thereof |
| KR100678047B1 (en) * | 2004-05-06 | 2007-02-02 | 삼성전자주식회사 | Mobile communication terminal having nand flash memory and booting method thereof |
-
2005
- 2005-12-30 CN CNB2005101211602A patent/CN100456263C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441552B (en) * | 2007-11-19 | 2012-05-23 | 深圳市朗科科技股份有限公司 | Flash memory medium bad block processing method |
| CN101593157B (en) * | 2008-05-27 | 2011-03-16 | 中兴通讯股份有限公司 | Bad block management (BBM) method and device for Nand Flash |
| CN101944065A (en) * | 2010-08-24 | 2011-01-12 | 苏州国芯科技有限公司 | Flash memory bad block shielding method based on section |
| CN101944065B (en) * | 2010-08-24 | 2012-07-04 | 苏州国芯科技有限公司 | Flash memory bad block shielding method based on section |
| CN102541676A (en) * | 2011-12-22 | 2012-07-04 | 福建新大陆通信科技股份有限公司 | Method for detecting and mapping states of NAND FLASH |
| CN102541676B (en) * | 2011-12-22 | 2014-03-05 | 福建新大陆通信科技股份有限公司 | Method for detecting and mapping states of NAND FLASH |
| CN104166627A (en) * | 2014-09-02 | 2014-11-26 | 科大智能电气技术有限公司 | NAND-FLASH writing operation method based on single-chip microcomputer |
| CN104166627B (en) * | 2014-09-02 | 2017-12-08 | 科大智能电气技术有限公司 | A kind of SCM Based NAND FLASH write operation methods |
| CN108573735A (en) * | 2017-03-08 | 2018-09-25 | 北京兆易创新科技股份有限公司 | A kind of the block restorative procedure and device of NAND-FLASH |
| CN108573735B (en) * | 2017-03-08 | 2020-12-11 | 北京兆易创新科技股份有限公司 | NAND-FLASH block repair method and device |
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|---|---|
| CN100456263C (en) | 2009-01-28 |
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