CN1987835A - System for realizing multiple FPGA image file serial unload and its relative computer - Google Patents
System for realizing multiple FPGA image file serial unload and its relative computer Download PDFInfo
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- CN1987835A CN1987835A CN 200510111850 CN200510111850A CN1987835A CN 1987835 A CN1987835 A CN 1987835A CN 200510111850 CN200510111850 CN 200510111850 CN 200510111850 A CN200510111850 A CN 200510111850A CN 1987835 A CN1987835 A CN 1987835A
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Abstract
A system which can realize multi FPGA image file download and the related computer, the system includes a CPU and some FPGA, every FPGA can connect with the CPU by n signal lines, the CPU can locate n registers by the information pattern, and the same pattern signal of FPGA arranges on the corresponding digitally of the register. The CPU contains a sending and accepting process element which is used to compile the relate pattern signal data on the same digitally of the FPGA image profile into a data and write into the corresponding signal pattern of the register's digitally. At the same time it can use to read all the data in the relate signal pattern of the register when the reading of the information data comes about, after separation it can obtain the real download FPGA data. This invention optimizes the location serial download inducing foot by the reasonable hardware design, and it realizes multi image profile serial download at the same time, the download time is same with one FPGA image, so it saves the system start time.
Description
Technical field
The present invention relates to method and implement device thereof that a kind of a plurality of FPGA image file serial is downloaded.
Background technology
FPGA (Field Programmable Gate Array, field programmable gate array) is a kind of Logic Circuit Design technology, is characterized in having the characteristic of user-programmable.Utilize FPGA, electronic system design slip-stick artist can design application-specific integrated circuit (integrated circuit) in the laboratory, realizes the integrated of system, thereby has shortened time of product development greatly, reduces cost of development.But FPGA also has static state overprogram or online dynamic restructuring characteristic in addition, the function of hardware can be revised by programming as software, be not only Change In Design and product up-gradation and become very convenient, and the dirigibility and the general ability of electronic system greatly are provided.
Because the dirigibility of FPGA field-programmable is being widely used in the communication system at present, on the circuit board that has even dozens of FPGA is set.Generally after circuit board powered on, the system start-up program was responsible for for example reading the FPGA image file on the CF card (Nonvolatile memory card) from non-volatile medium, downloaded among the FPGA, and then, FPGA could operate as normal.
Usually the download of FPGA image file all is to utilize GPIO (general I/O) pin.Though parallel download speed is fast, be to solve long effective ways of download time, but parallel the download realized complexity, and in some cases, be subjected to the influence of circuit board wiring layout, for example be difficult to tens of lead-in wires are connected in the downloading control chip, perhaps fpga chip itself is not supported parallel the download, becomes first-selection so serial is downloaded.
The FPGA image file is downloaded in serial, only need a plurality of FPGA image files in turn in turn serial download and get final product, realize simply, application is more extensive in current design.
But the defective that serial is downloaded is that speed is slower, main bottleneck is on universal serial bus, suppose to have on the circuit board n FPGA, downloading a FPGA image file need be according to downloading flow process to universal serial bus operation one time, t consuming time second, download n FPGA reflection and just need operate n time universal serial bus, nt consuming time second according to downloading flow process.Like this, had a strong impact on the toggle speed of system.
Summary of the invention
The present invention aims to provide method and the implement device thereof that a kind of a plurality of FPGA image file serial is downloaded, in simple and direct mode, avoid a plurality of FPGA image file serials to download defective consuming time, thereby save the system start-up time, satisfy high reliability request such as telecommunication apparatus.
A kind of system that realizes that a plurality of FPGA image file serials are downloaded provided by the present invention, comprise a CPU and several FPGA, it is characterized in that: each FPGA links to each other with described CPU by n root signal wire, and described n root signal wire is to be used for serial to download that a FPGA image file is required to take all types of signal wires; Described CPU presses signal type and distributes n register, and the signal of the same type of all FPGA is sequentially arranged on each numerical digit of corresponding registers; Again, described CPU comprises a transmission/reception processing unit, when being used to send the FPGA image file, the correlation type signal data on the identical numerical digit of each FPGA image file is formed data, write then in each data bit of register of corresponding signal type; Simultaneously, when being used to read signal data, all data bit in the coherent signal type register are read together each the FPGA True Data after can obtaining after the separation to download.
In above-mentioned system, it comprises that also one connects the CPLD that is used for extension CPU GPIO pin between described CPU and several FPGA.
In above-mentioned system, n root signal wire comprises clock cable, data signal line, configuration signal line and status signal lines; Described register correspondence comprise clock register, status register, configuration register and data register.
In above-mentioned system, clock cable is shared for all FPGA.
The present invention also provides a kind of computing machine, comprise n register, it is characterized in that: it also comprises a transmission/reception processing unit that links to each other with a described n register, and wherein: a described n register is to download the required signal type that takies all types of signal wires of a FPGA image file by its serial to distribute; Transmission/reception processing unit, when being used to send the FPGA image file, the correlation type signal data on the identical numerical digit of each FPGA image file formed data after, write in each data bit of register of corresponding signal type; When reading signal data, all data bit in the coherent signal type register are read together each the FPGA True Data after can obtaining after the separation to download.
In above-mentioned computing machine, register comprises clock register, status register, configuration register and data register.
In above-mentioned computing machine, the data that transmission/reception processing unit writes in the clock register are shared for all FPGA.
The present invention provides a kind of computer processing method of realizing that a plurality of FPGA image file serials are downloaded again, comprise: allocation step: CPU is downloaded the required signal type that takies all types of signal wires of a FPGA image file by serial distribute n register, and the signal of the same type of all FPGA is sequentially arranged on each numerical digit of corresponding registers; Forwarding step: when sending the FPGA image file, the correlation type signal data on the identical numerical digit of each FPGA image file is formed data, write then in each data bit of register of corresponding signal type; And, read step: when being used to read signal data, all data bit in the coherent signal type register are read together, separate, each the FPGA True Data after can obtaining to download.
In above-mentioned computer processing method, register comprises clock register, status register, configuration register and data register.
In above-mentioned computer processing method, the data that write in the clock register are shared for all FPGA.
Owing to adopted above-mentioned technical solution, by rational hardware design, pin is downloaded in the optimized distribution serial, and serial is downloaded when realizing a plurality of FPGA reflection, and its time is with to download a FPGA reflection almost equal.The invention solves when having a plurality of FPGA on the circuit board, the problem consuming time that its image file serial is downloaded has been saved the start-up time of system (the particularly contour security device of telecommunication apparatus).
Description of drawings
Fig. 1 is the synoptic diagram that the present invention realizes the system that a plurality of FPGA image file serials are downloaded;
Fig. 2 is its registers and a line synoptic diagram among the present invention.
Embodiment
The basic thought that the present invention comes from is: it is on universal serial bus that slow bottleneck is downloaded in serial, rather than on cpu frequency, so should reduce operation as far as possible to universal serial bus, and by rational its registers and line, can download n FPGA reflection fully simultaneously, and only to universal serial bus operation one time.
If the number of FPGA is less in the system of the present invention, FPGA can directly be connected on the GPIO pin of CPU; If the number of FPGA is more, participate in Fig. 1, CPU is by CPLD (CPLD) expansion GPIO pin, and FPGA can be connected on the CPLD.
Shown in Fig. 1～2, the present invention promptly realizes the system that a plurality of FPGA image file serials are downloaded, and comprises a CPU and several FPGA.
Each FPGA links to each other with CPLD by n root signal wire, and n root signal wire is to be used for serial to download that a FPGA image file is required to take all types of signal wires.The serial of a common FPGA image file is downloaded need take 4,5 lines, and it is all similar to download flow process.
CPLD presses signal type and distributes n register, and the signal of the same type of all FPGA is sequentially arranged on each numerical digit of corresponding registers.
Cyclone Series FPGA with altera corp is that example is illustrated the present invention, contains expansion CPLD in the system.
A FPGA image file is downloaded in serial needs 4 signal wires, is respectively:
I) CLK: clock signal;
Ii) Data: data-signal;
Iii) Config: configuration signal;
Iv) Status: status signal.
Each FPGA links to each other with CPLD by these 4 signal wires, and CPU downloads to the FPGA image file among the FPGA by these 4 signal wires exactly.In CPLD, in the corresponding register of every signal wire one.
Principle one: register is pressed signal type and is distributed, and distributes not according to FPGA.Specifically, the CLK signal of all FPGA is arranged in (other 3 signal same treatment) in the same register, rather than 4 signal wires of same FPGA are arranged in the same register.This is convenient to register of CPU read-write, just can realize the operation to all FPGA.
As shown in Figure 2, distributed 4 registers according to signal type:
I) CLK Reg.: clock register;
Ii) Status Reg.: status register;
Iii) Config Reg.: configuration register;
Iv) Data Reg.: data register.
Signal wire of each management of each register.Clock cable is shared, and all FPGA reflections are to download synchronously.
Principle two: operate universal serial bus less as far as possible, utilize cpu resource as much as possible.
CPU comprises a transmission/reception processing unit, and when sending data, CPU at first is organized into data with the data bit of each FPGA image file, writes in the data register then.For example, send m data, suppose to have 5 FPGA (n=5), m data of FPGA 1 image file are 1, and m data of FPGA 2 image files are 0, and m data of FPGA 3 image files are 1, m data of FPGA 4 image files are 1, m data of FPGA 5 image files are 0, and CPU just writes binary number 10110 in the data register so, can occur each self-corresponding data bit simultaneously on each FPGA corresponding data line.Because the frequency of CPU is higher than the frequency of universal serial bus far away, so by contrast, CPU organizes the time of data almost can ignore.
During the tranmitting data register signal, because clock signal is shared, each FPGA is synchronous, promptly sends " 1 ", and CPU sends the clock register set simultaneously so, sends " 0 " in like manner.
During read state signal, CPU reads back all positions of status register to come together, is analyzed then.
Because all FPGA download simultaneously, so each reflection of status register all is True Data, and do not resemble when downloading the FPGA reflection one by one, have only download that FPGA pairing position reflection be True Data.
Config operation registers method is identical with status register.
In sum, the present invention is by reasonable hardware design, and pin is downloaded in the optimized distribution serial, and serial is downloaded when realizing a plurality of FPGA image file, and its time is with to download a FPGA reflection almost equal.
Above embodiment is only for the usefulness that the present invention is described, but not limiting the scope of the invention.Relevant those skilled in the art under the situation that does not break away from the spirit and scope of the present invention, can also make various conversion or modification, and the technical scheme that all are equal to also should belong within the category of the present invention's protection, is limited by each claim.
Claims (10)
1. a system that realizes that a plurality of FPGA image file serials are downloaded comprises a CPU and several FPGA, it is characterized in that:
Each FPGA links to each other with described CPU by n root signal wire, and described n root signal wire is to be used for serial to download that a FPGA image file is required to take all types of signal wires;
Described CPU presses signal type and distributes n register, and the signal of the same type of all FPGA is sequentially arranged on each numerical digit of corresponding registers; Again,
Described CPU comprises a transmission/reception processing unit, when being used to send the FPGA image file, the correlation type signal data on the identical numerical digit of each FPGA image file is formed data, writes then in each data bit of register of corresponding signal type; Simultaneously, when being used to read signal data, all data bit in the coherent signal type register are read together each the FPGA True Data after can obtaining after the separation to download.
2. system according to claim 1 is characterized in that: it comprises that also one connects the CPLD that is used for extension CPU GPIO pin between described CPU and several FPGA.
3. system according to claim 1 and 2 is characterized in that: described n root signal wire comprises clock cable, data signal line, configuration signal line and status signal lines; Described register correspondence comprise clock register, status register, configuration register and data register.
4. system according to claim 3 is characterized in that: described clock cable is shared for all FPGA.
5. a computing machine comprises n register, it is characterized in that: it also comprises a transmission/reception processing unit that links to each other with a described n register, wherein:
A described n register is to download the required signal type that takies all types of signal wires of a FPGA image file by its serial to distribute;
Transmission/reception processing unit, when being used to send the FPGA image file, the correlation type signal data on the identical numerical digit of each FPGA image file formed data after, write in each data bit of register of corresponding signal type; When reading signal data, all data bit in the coherent signal type register are read together each the FPGA True Data after can obtaining after the separation to download.
6. computing machine according to claim 5 is characterized in that: described register comprises clock register, status register, configuration register and data register.
7. computing machine according to claim 6 is characterized in that: the data that described transmission/reception processing unit writes in the clock register are shared for all FPGA.
8. computer processing method of realizing that a plurality of FPGA image file serials are downloaded comprises:
Allocation step: CPU is downloaded the required signal type that takies all types of signal wires of a FPGA image file by serial distribute n register, and the signal of the same type of all FPGA is sequentially arranged on each numerical digit of corresponding registers;
Forwarding step: when sending the FPGA image file, the correlation type signal data on the identical numerical digit of each FPGA image file is formed data, write then in each data bit of register of corresponding signal type; And,
Read step: when being used to read signal data, all data bit in the coherent signal type register are read together, separate, each the FPGA True Data after can obtaining to download.
9. computer processing method according to claim 8 is characterized in that: described register comprises clock register, status register, configuration register and data register.
10. computing machine according to claim 9 is characterized in that: the data in the said write clock register are shared for all FPGA.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043747A (en) * | 2010-12-17 | 2011-05-04 | 浙江大学 | Method for downloading field programmable gate array (FPGA) logic codes under joint test action group (JTAG) download mode |
| CN102289381A (en) * | 2011-08-24 | 2011-12-21 | 中兴通讯股份有限公司 | Method and system for upgrading programmable logic devices |
| CN101604244B (en) * | 2008-06-13 | 2012-11-28 | 中兴通讯股份有限公司 | Device and method for realizing that FPGA can be used when being electrified and remote upgrade of FPGA |
| CN103092652A (en) * | 2013-01-16 | 2013-05-08 | 深圳市怡化电脑有限公司 | Multiprocessor program loading device and loading method |
| CN109347954A (en) * | 2018-10-18 | 2019-02-15 | 中国人民解放军战略支援部队航天工程大学 | A kind of bullet arrow polymorphic type signal acquisition and processing apparatus based on a variety of buses |
| CN113127302A (en) * | 2021-04-16 | 2021-07-16 | 山东英信计算机技术有限公司 | Method and device for monitoring GPIO (general purpose input/output) of board card |
| CN114238207A (en) * | 2021-12-09 | 2022-03-25 | 讯牧信息科技(上海)有限公司 | Configuration method of multiple FPGA (field programmable Gate array) and multiple FPGA system |
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| CN106682296A (en) * | 2016-12-19 | 2017-05-17 | 西安微电子技术研究所 | FPGA oriented multi-way universal configuration loading control system and method |
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- 2005-12-22 CN CNB200510111850XA patent/CN100468369C/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604244B (en) * | 2008-06-13 | 2012-11-28 | 中兴通讯股份有限公司 | Device and method for realizing that FPGA can be used when being electrified and remote upgrade of FPGA |
| CN102043747A (en) * | 2010-12-17 | 2011-05-04 | 浙江大学 | Method for downloading field programmable gate array (FPGA) logic codes under joint test action group (JTAG) download mode |
| CN102043747B (en) * | 2010-12-17 | 2012-07-18 | 浙江大学 | Method for downloading field programmable gate array (FPGA) logic codes under joint test action group (JTAG) download mode |
| CN102289381A (en) * | 2011-08-24 | 2011-12-21 | 中兴通讯股份有限公司 | Method and system for upgrading programmable logic devices |
| CN103092652A (en) * | 2013-01-16 | 2013-05-08 | 深圳市怡化电脑有限公司 | Multiprocessor program loading device and loading method |
| CN109347954A (en) * | 2018-10-18 | 2019-02-15 | 中国人民解放军战略支援部队航天工程大学 | A kind of bullet arrow polymorphic type signal acquisition and processing apparatus based on a variety of buses |
| CN109347954B (en) * | 2018-10-18 | 2021-08-06 | 中国人民解放军战略支援部队航天工程大学 | Rocket multi-type signal acquisition and processing device based on multiple buses |
| CN113127302A (en) * | 2021-04-16 | 2021-07-16 | 山东英信计算机技术有限公司 | Method and device for monitoring GPIO (general purpose input/output) of board card |
| CN113127302B (en) * | 2021-04-16 | 2023-05-26 | 山东英信计算机技术有限公司 | Board GPIO monitoring method and device |
| CN114238207A (en) * | 2021-12-09 | 2022-03-25 | 讯牧信息科技(上海)有限公司 | Configuration method of multiple FPGA (field programmable Gate array) and multiple FPGA system |
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| CN100468369C (en) | 2009-03-11 |
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