CN115858426A - Hard disk interface, hard disk and electronic equipment - Google Patents
Hard disk interface, hard disk and electronic equipment Download PDFInfo
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- CN115858426A CN115858426A CN202211665424.0A CN202211665424A CN115858426A CN 115858426 A CN115858426 A CN 115858426A CN 202211665424 A CN202211665424 A CN 202211665424A CN 115858426 A CN115858426 A CN 115858426A
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Abstract
The invention relates to a hard disk interface, a hard disk and an electronic device. In the present application: the first high-speed analog switch is connected with the M.2 slot through a PCIE signal link and an SATA signal link, and the nA pin of the first high-speed analog switch is directly connected with the CPU; the nB1 pin or nB2 pin used for supporting the UFS hard disk in the second high-speed analog switch is connected with the M.2 slot, the nA pin of the second high-speed analog switch is connected with an MIPI M-PHY signal to PCIE signal conversion chip, and the MIPI M-PHY signal to PCIE signal conversion chip is connected with the CPU; and a self-adaptive driving circuit is connected between the enabling and selecting pins of the M.2 slot and the first high-speed analog switch and the second high-speed analog switch, and the working states of the first high-speed analog switch and the second high-speed analog switch are controlled according to the type of the hard disk connected with the M.2 slot so as to adapt to the connected hard disk. And the compatibility of the M.2 slot to PCIE, SATA and UFS hard disks is realized.
Description
Technical Field
The invention relates to the field of hard disk interface design, in particular to a hard disk interface, a hard disk and electronic equipment.
Background
In order to pursue higher server read-write speed, intel developed a solid state disk with an m.2 interface. The M.2 interface is a new host interface scheme, and can be compatible with various communication protocols, such as SATA, PCIE, USB, HSIC, UART, SMBus and the like.
Universal Flash Storage (UFS) is a Flash Storage specification, and UFS uses an M-PHY physical layer developed by the MIPI alliance and has a speed of 2.9Gbps per thread to 5.8Gbps per thread. The UFS realizes a full-duplex LVDS serial port, and has a wider bandwidth compared with the eMMC with 8 parallel threads. Has the characteristics of small volume, high speed and low power consumption. UFS is designed for consumer electronics products such as digital cameras, smart phones, and the like. The UFS interface is not adapted to the m.2 interface used by the hard disk in the existing server, and cannot be applied to a server using the m.2 interface as the hard disk interface. In the existing m.2 interface design, a selection switch capable of gating a PCIE data transmission bus or an SATA data transmission bus is usually designed to be connected to the m.2 slot, so that the same m.2 slot simultaneously supports the design of the SATA hard disk and the PCIE hard disk. When the UFS is adapted to the m.2 interface, the type of the m.2 interface adapted hard disk is increased, and the adaptive compatible design of the corresponding hard disk with multiple communication protocols is yet to be further improved, and we expect to improve the existing m.2 interface to be compatible with the hard disk including the UFS, so as to improve the adaptive capability of the hard disk with multiple communication protocols.
Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the invention provides a hard disk interface, a hard disk and an electronic device.
In a first aspect, the present invention provides a hard disk interface, including: m.2 slot;
the M.2 slot is connected to the central processing unit through a first high-speed analog switch for gating the PCIE signal link or the SATA signal link;
the M.2 slot is connected with a second high-speed analog switch supporting a universal flash memory link, and the second high-speed analog switch is connected to the central processing unit through a signal conversion chip.
Furthermore, the first high-speed analog switch is connected with a PCIE controller in the central processing unit; and/or the presence of a gas in the gas,
the first high-speed analog switch is connected with the SATA controller in the central processing unit.
Furthermore, the signal conversion chip is used for converting the MIPI M-PHY signal into a PCIE signal;
the signal conversion chip is connected with the PCIE controller.
Furthermore, the device also comprises an adaptive driving circuit which is arranged between the M.2 slot and the first high-speed analog switch and/or the second high-speed analog switch and is used for adapting to the type of the hard disk, and the adaptive driving circuit controls the working states of the first high-speed analog switch and the second high-speed analog switch according to the type of the hard disk connected with the M.2 slot so as to adapt to the connected hard disk.
Still further, the adaptive driving circuit includes:
a pull-up wire arranged between the first high-speed analog switch enabling pin and the M.2 slot hard disk on-position detection pin,
a pull-up trace disposed between the first high-speed analog switch selection pin and the communication protocol detection pin on the M.2 slot,
and the upper pull wire is connected with an upper pull resistor.
Still further, the adaptive driving circuit further includes:
a pull-up wire of a NOT gate is arranged between the second high-speed analog switch enabling pin and the M.2 slot hard disk on-position detection pin,
and the state configuration circuit is arranged on the selection pin of the second high-speed analog switch and is used for configuring the second high-speed analog switch to gate the universal flash memory link.
Furthermore, the second high-speed analog switch comprises a reference clock pin supporting the general flash memory storage, a downlink data input pin and an uplink data output pin.
Further, the m.2 slot is one of a B _ KEY _ m.2 slot or an M _ KEY _ m.2 slot.
In a second aspect, the present invention provides a hard disk, which is suitable for the hard disk interface, and includes a storage module and a gold finger, where the gold finger is adapted to the m.2 slot; the golden finger is connected with an indicating circuit corresponding to the self-adaptive driving circuit in the hard disk interface, the indicating circuits of different hard disks are different, and the storage module comprises a universal flash memory for storage.
In a third aspect, the present invention provides an electronic device, which includes at least one of the hard disk interfaces, and/or includes at least one of the hard disks.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
the invention non-standard defines and supports pins in the M.2 slot of the PCIE hard disk and the SATA hard disk, so that the M.2 slot supports the data transmission of the UFS hard disk, and the gold finger adapting to the M.2 slot is configured for the UFS hard disk, so that the M.2 slot supports the connection of the UFS hard disk. In order to realize data transmission of the UFS hard disk, a second high-speed analog switch and an MIPI M-PHY signal-to-PCIE signal chip are configured between a CPU and an M.2 slot, wherein the second high-speed analog switch is controlled to realize the on-off of a UFS data channel based on a self-adaptive driving circuit.
The self-adaptive drive circuit controls and coordinates the working states of a first high-speed analog switch compatible with a PCIE hard disk and a SATA hard disk and a second high-speed analog switch compatible with a UFS hard disk according to the type of the hard disk connected with the M.2 slot. The compatibility of one M.2 slot to PCIE, SATA, especially UFS hard disk is realized, and the product competitiveness can be effectively improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic diagram of a hard disk interface according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an adaptive driving circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another hard disk interface according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another adaptive driving circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a PCIE hard disk, an SATA hard disk, and a UFS hard disk provided in the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Example 1
An embodiment of the present invention provides a hard disk interface, including: and the M.2 slot supports a PCIE hard disk, an SATA hard disk and a UFS hard disk, and the M.2 slot is any one of a B _ KEY _ M.2 slot or an M _ KEY _ M.2 slot. The M.2 slot is connected to the central processing unit through a first high-speed analog switch for gating a PCIE signal link or a SATA signal link; the M.2 slot is connected with a second high-speed analog switch supporting a universal flash memory link, and the second high-speed analog switch is connected to the central processing unit through a signal conversion chip.
Specifically, the first high-speed analog switch is connected to a PCIE controller in the central processing unit; and/or the first high-speed analog switch is connected with the SATA controller in the central processing unit. The signal conversion chip is used for converting the MIPI M-PHY signal into a PCIE signal; the signal conversion chip is connected with the PCIE controller.
And the self-adaptive driving circuit is used for adapting to the type of the hard disk and is arranged between the M.2 slot and the first high-speed analog switch and/or the second high-speed analog switch, and the self-adaptive driving circuit controls the working states of the first high-speed analog switch and the second high-speed analog switch according to the type of the hard disk connected with the M.2 slot so as to adapt to the connected hard disk.
In the prior art, an m.2 interface supporting the UFS hard disk is lacking, and in the present application, pins in the m.2 slot supporting the PCIE hard disk and the SATA hard disk are defined in a non-standard manner, so that the m.2 slot supports the UFS hard disk, the PCIE hard disk, and the SATA hard disk. And for the golden finger and the M.2 slot of the UFS hard disk, combining the UFS hard disk pin definition to define the nonstandard pins of the M.2 slot, so that the M.2 slot can support the UFS hard disk. The pins in the M.2 slot for the non-standard definition of the UFS hard disk comprise: the power supply pin, the grounding pin, the reset control pin, the downlink data input pin, the uplink data output pin of the UFS hard disk and the reference clock pin of the UFS hard disk correspond to the VCC pin of the UFS hard disk, the VSS pin of the UFS hard disk, the RST pin of the UFS hard disk, the downlink data input pin of the UFS hard disk, the power supply pin, the grounding pin, the reset control pin, the downlink data input pin, the uplink data output pin and the reference clock pin of the UFS hard disk.
In order to identify different types of hard disks, the golden finger connected with the hard disk of the M.2 slot needs to be connected with an indicating circuit: the indication circuit of the PCIE hard disk comprises: the grounding circuit corresponds to the on-position detection pin of the hard disk in the M.2 slot, and the communication protocol detection pin corresponding to the M.2 slot is suspended. The indication circuit of the SATA hard disk comprises: the grounding circuit corresponds to the on-position detection pin of the hard disk in the M.2 slot and corresponds to the grounding circuit of the communication protocol detection pin in the M.2 slot. The indicating circuit of the UFS hard disk comprises: and the communication protocol detection pins corresponding to the hard disk in-place detection pins and the M.2 slots are suspended.
In the application, the first high-speed analog switch is used for being compatible with a PCIE hard disk and an SATA hard disk, and the second high-speed analog switch is used for supporting a UFS hard disk. And a self-adaptive driving circuit is connected between the enabling pins and the selecting pins of the M.2 slot and the first high-speed analog switch and the second high-speed analog switch, and controls the working states of the first high-speed analog switch and the second high-speed analog switch according to the type of the hard disk connected with the M.2 slot so as to adapt to the connected hard disk.
In a specific implementation process, the adaptive driving circuit includes: the pull-up wiring is arranged between the first high-speed analog switch enabling pin and the M.2 slot hard disk on-site detection pin, the pull-up wiring is arranged between the first high-speed analog switch selecting pin and the M.2 slot communication protocol detection pin, and the pull-up wiring is connected with a pull-up resistor.
The adaptive driving circuit further includes: the upper pull-away line of the NOT gate is configured between the enabling pin of the second high-speed analog switch and the on-position detection pin of the M.2 slot hard disk, and the state configuration circuit is connected with the selecting pin of the second high-speed analog switch, and the state configuration circuit enables the second high-speed analog switch to be selectively matched with the nB1 pin or the nB2 pin supporting the UFS hard disk to be connected with the nA pin when the second high-speed analog switch works. The state configuration circuit is one of a ground or a pull-up circuit.
Referring to fig. 1 and fig. 2 in combination, in a possible implementation, the first high-speed analog switch and the second high-speed analog switch each include one set of uplink pins nA and two sets of downlink pins nB1 and nB2, and the first high-speed analog switch and the second high-speed analog switch configure the uplink pins nA to gate the downlink pins nB1 or gate the downlink pins nB2.
The nB1 pin of the first high-speed analog switch is connected with the M.2 slot through PCIE signal wiring (PCIE _ TX and PCIE _ RX); the nB2 pin of the first high-speed analog switch is connected with the M.2 slot through SATA signal routing (SATA _ TX and SATA _ RX), undefined pins are suspended, and the nA pin of the first high-speed analog switch is directly and electrically connected with a PCIE controller and an SATA controller which are integrated in the CPU.
The nB1 pin or nB2 pin part of the second high-speed analog switch is defined as a reference clock pin, a downlink data input pin and an uplink data output pin for supporting the UFS hard disk.
In one embodiment, the nB1 pins of the second high speed analog switch are defined as reference clock pins (REF _ CLK _ N ), down data input pins (DIN _ P, DIN _ N), up data output pins (DOUT _ P, DOUT _ N); the nB1 pin of the second high-speed analog switch is connected with the corresponding pin of the M.2 slot, the nB2 pin of the second high-speed analog switch is suspended, the nA pin of the second high-speed analog switch is electrically connected with an MIPI M-PHY signal to PCIE signal chip, and then the MIPI M-PHY signal to PCIE signal chip is electrically connected with a PCIE controller integrated in the CPU.
An enabling pin (/ OE pin, active low) of the first high-speed analog switch is connected to a hard disk on-site detection pin (DAS/DSS # pin) on the M.2 slot through an upper pull-out wire, and a selection pin (S pin) of the first high-speed analog switch is connected to a communication protocol detection Pin (PEDET) on the M.2 slot through an upper pull-out wire. If when the SATA hard disk or the PCIE hard disk is inserted into the M.2 slot, the hard disk provides a low level at the on-site detection pin, the enable pin of the first high-speed analog switch inputs a low level, the first high-speed analog switch works, if the UFS hard disk is inserted into the M.2 slot, the hard disk provides a high level at the on-site detection pin, the enable pin of the first high-speed analog switch inputs a high level, and the first high-speed analog switch disconnects the connection between the nA pin and the nBx (x =1, 2) pin. If the M.2 slot is connected with a SATA hard disk, the communication protocol detection pin provides a low level, and the selection pin of the first high-speed analog switch inputs the low level, the nA pin and the nB2 pin are switched on by the first high-speed analog switch; if the M.2 slot is connected with a PCIE hard disk, the on-site detection pin of the hard disk is suspended, and the selection pin of the first high-speed analog switch inputs a high level, the nA pin and the nB1 pin are connected through by the first high-speed analog switch.
The enabling pin (/ OE pin, active low) of the second high-speed analog switch is connected to a hard disk on-site detection pin (DAS/DSS # pin) on the M.2 slot through an up-pulling wire of a set NOT gate, and a selection pin (S pin) of the second high-speed analog switch is powered up. If a SATA hard disk or a PCIE hard disk is plugged in the M.2 slot, the hard disk provides a low level at an in-place detection pin, an enable pin of the second high-speed analog switch inputs a high level, and the second high-speed analog switch disconnects the connection between the nA pin and the nBx (x =1, 2) pin; if the UFS hard disk is plugged into the M.2 slot (the UFS hard disk is suspended for the hard disk in-place detection pin), the hard disk in-place detection pin provides a high level, the enable pin of the second high-speed analog switch inputs a low level, and the second high-speed analog switch is connected with the nA pin and the nB1 pin.
With reference to fig. 3 and fig. 4, in another possible implementation, the nB1 pin of the first high-speed analog switch is connected to the m.2 slot via PCIE signal traces (PCIE _ TX and PCIE _ RX); the nB2 pin of the first high-speed analog switch is connected with the M.2 slot through SATA signal routing (SATA _ TX and SATA _ RX), undefined pins are suspended, and the nA pin of the first high-speed analog switch is directly and electrically connected with a PCIE controller and an SATA controller which are integrated in the CPU. The nB2 pins of the second high-speed analog switch are defined as reference clock pins (REF _ CLK _ N ), downlink data input pins (DIN _ P, DIN _ N), and uplink data output pins (DOUT _ P, DOUT _ N); the nB2 pin of the second high-speed analog switch is connected with the corresponding pin of the M.2 slot, the nB1 pin of the second high-speed analog switch is suspended, the nA pin of the second high-speed analog switch is electrically connected with an MIPI M-PHY signal to PCIE signal chip, and then the MIPI M-PHY signal to PCIE signal chip is electrically connected with a PCIE controller integrated in the CPU.
An enabling pin (/ OE pin, active low) of the first high-speed analog switch is connected to a hard disk on-site detection pin (DAS/DSS # pin) on the M.2 slot through an upper pull-out wire, and a selection pin (S pin) of the first high-speed analog switch is connected to a communication protocol detection Pin (PEDET) on the M.2 slot through an upper pull-out wire. If when the SATA hard disk or the PCIE hard disk is inserted into the M.2 slot, the hard disk provides a low level at the on-site detection pin, the enable pin of the first high-speed analog switch inputs a low level, the first high-speed analog switch works, if the UFS hard disk is inserted into the M.2 slot, the hard disk provides a high level at the on-site detection pin, the enable pin of the first high-speed analog switch inputs a high level, and the first high-speed analog switch disconnects the connection between the nA pin and the nBx (x =1, 2) pin. If the M.2 slot is connected with a SATA hard disk, the communication protocol detection pin provides a low level, and the selection pin of the first high-speed analog switch inputs the low level, the nA pin and the nB2 pin are switched on by the first high-speed analog switch; if the M.2 slot is connected with a PCIE hard disk, the on-site detection pin of the hard disk is suspended, and the selection pin of the first high-speed analog switch inputs a high level, the nA pin and the nB1 pin are connected through by the first high-speed analog switch.
The enabling pin (/ OE pin, active low) of the second high-speed analog switch is connected to a hard disk on-site detection pin (DAS/DSS # pin) on the M.2 slot through an upper pull-out wire of a set NOT gate, and a selection pin (S pin) of the second high-speed analog switch is grounded. If a SATA hard disk or a PCIE hard disk is plugged in the M.2 slot, the hard disk provides a low level at an in-place detection pin, an enable pin of the second high-speed analog switch inputs a high level, and the second high-speed analog switch disconnects the connection between the nA pin and the nBx (x =1, 2) pin; if the UFS hard disk is plugged in the M.2 slot, the hard disk on-site detection pin provides a high level, the enable pin of the second high-speed analog switch inputs a low level, and the second high-speed analog switch is connected with the nA pin and the nB2 pin.
Example 2
Referring to fig. 5, an embodiment of the present invention provides a hard disk, which is suitable for the hard disk interface described in embodiment 1, where the hard disk configuration includes a gold finger adapted to the hard disk interface; the storage module is matched with a golden finger, and the golden finger is matched with the M.2 slot; the golden finger is connected with an indicating circuit corresponding to the self-adaptive driving circuit in the hard disk interface, the indicating circuits of different hard disks are different, and the storage module comprises a universal flash memory for storage.
In a specific implementation process, the hard disk types include: PCIE hard disk, SATA hard disk and UFS hard disk. In a specific implementation process, when the B _ KEY _ m.2 slot is applied to the hard disk interface in embodiment 1, in order to adapt to the m.2 slot, a gold finger of the PCIE hard disk, the SATA hard disk, and the UFS hard disk connected to the hard disk interface needs to be set to any one of a B & M _ KEY type and a B _ KEY type; when the M _ KEY _ m.2 slot is applied, in order to adapt to the m.2 slot, the gold finger of the PCIE hard disk, the SATA hard disk, and the UFS hard disk connected to the hard disk interface needs to be any one of the B & M _ KEY type and the M _ KEY type. In order to identify different types of hard disks, the golden finger of the hard disk needs to be connected with an indicating circuit:
the indication circuit of the PCIE hard disk comprises: the grounding circuit corresponds to the on-position detection pin of the hard disk in the M.2 slot, and the communication protocol detection pin corresponding to the M.2 slot is suspended.
The indication circuit of the SATA hard disk comprises: the grounding circuit corresponds to the on-position detection pin of the hard disk in the M.2 slot and corresponds to the grounding circuit of the communication protocol detection pin in the M.2 slot.
The indicating circuit of the UFS hard disk comprises: and the communication protocol detection pins corresponding to the hard disk in-place detection pins and the M.2 slots are suspended.
Example 3
The embodiment of the invention provides electronic equipment, wherein the electronic equipment is provided with at least one central processing unit, and the central processing unit is connected with at least one hard disk interface in embodiment 1; a hard disk interface may be connected to the hard disk described in at least one embodiment 2, where the hard disk types include: PCIE hard disk, SATA hard disk and UFS hard disk.
The indication circuit of the PCIE hard disk comprises: and the grounding circuit corresponds to the on-position detection pin of the hard disk in the M.2 slot, and the suspension of the communication protocol detection pin corresponds to the M.2 slot.
The indication circuit of the SATA hard disk comprises: the grounding circuit corresponds to the on-position detection pin of the hard disk in the M.2 slot and corresponds to the grounding circuit of the communication protocol detection pin in the M.2 slot.
The indicating circuit of the UFS hard disk comprises: and the communication protocol detection pins corresponding to the hard disk in-place detection pins and the M.2 slots are suspended.
In the embodiments provided in the present invention, it should be understood that the disclosed structures may be implemented in other ways. For example, the above-described structural embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and there may be other divisions when the actual implementation is performed, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, structures or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A hard disk interface, comprising: m.2 slot;
the M.2 slot is connected to the central processing unit through a first high-speed analog switch for gating a PCIE signal link or a SATA signal link;
the M.2 slot is connected with a second high-speed analog switch supporting a universal flash memory link, and the second high-speed analog switch is connected to the central processing unit through a signal conversion chip.
2. The hard disk interface of claim 1,
the first high-speed analog switch is connected with a PCIE controller in the central processing unit; and/or the presence of a gas in the gas,
the first high-speed analog switch is connected with the SATA controller in the central processing unit.
3. The hard disk interface of claim 2,
the signal conversion chip is used for converting the MIPI M-PHY signal into a PCIE signal;
the signal conversion chip is connected with the PCIE controller.
4. The hard disk interface according to claim 1, further comprising an adaptive driving circuit disposed between the m.2 slot and the first high-speed analog switch and/or the second high-speed analog switch for adapting to a type of a hard disk, wherein the adaptive driving circuit controls an operating state of the first high-speed analog switch and the second high-speed analog switch according to a type of a hard disk connected to the m.2 slot to adapt to the connected hard disk.
5. The hard disk interface of claim 4, wherein the adaptive drive circuit comprises:
a pull-up wire arranged between the first high-speed analog switch enabling pin and the M.2 slot hard disk on-position detection pin,
a pull-up trace disposed between the first high-speed analog switch selection pin and the communication protocol detection pin on the M.2 slot,
and the upper pull wire is connected with an upper pull resistor.
6. The hard disk interface of claim 4 or 5, wherein the adaptive drive circuit further comprises:
a pull-up wire of a NOT gate is arranged between the second high-speed analog switch enabling pin and the M.2 slot hard disk on-position detection pin,
and the state configuration circuit is arranged on the selection pin of the second high-speed analog switch and is used for configuring the second high-speed analog switch to gate the universal flash memory link.
7. The hard disk interface of claim 6, wherein the second high speed analog switch comprises a reference clock pin, a downstream data input pin, and an upstream data output pin to support flash memory.
8. The hard disk interface of claim 7, wherein the M.2 slot is one of a B _ KEY _ M.2 slot or an M _ KEY _ M.2 slot.
9. A hard disk adapted for use in the hard disk interface of any one of claims 1-8, comprising: the storage module is matched with a golden finger, and the golden finger is matched with the M.2 slot; the golden finger is connected with an indicating circuit corresponding to the self-adaptive driving circuit in the hard disk interface, the indicating circuits of different hard disks are different, and the storage module comprises a universal flash memory for storage.
10. An electronic device, characterized in that it comprises at least one hard disk interface according to any of claims 1-8 and/or at least one hard disk according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211665424.0A CN115858426A (en) | 2022-12-23 | 2022-12-23 | Hard disk interface, hard disk and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211665424.0A CN115858426A (en) | 2022-12-23 | 2022-12-23 | Hard disk interface, hard disk and electronic equipment |
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| CN115858426A true CN115858426A (en) | 2023-03-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117093515A (en) * | 2023-10-09 | 2023-11-21 | 荣耀终端有限公司 | Memory, terminal equipment and memory system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117093515A (en) * | 2023-10-09 | 2023-11-21 | 荣耀终端有限公司 | Memory, terminal equipment and memory system |
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