CN1979802A - Lead mfg. method and method for shortening distance between lead an pattern - Google Patents
Lead mfg. method and method for shortening distance between lead an pattern Download PDFInfo
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- CN1979802A CN1979802A CN 200510129767 CN200510129767A CN1979802A CN 1979802 A CN1979802 A CN 1979802A CN 200510129767 CN200510129767 CN 200510129767 CN 200510129767 A CN200510129767 A CN 200510129767A CN 1979802 A CN1979802 A CN 1979802A
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- 238000000034 method Methods 0.000 title claims abstract description 114
- 238000004904 shortening Methods 0.000 title 1
- 239000004020 conductor Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims description 283
- 239000000463 material Substances 0.000 claims description 169
- 238000002955 isolation Methods 0.000 claims description 31
- 238000000059 patterning Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 11
- 238000001259 photo etching Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The method for reducing space between wires includes steps: providing substrate; forming first conductor layer on substrate; patternizing first conductor layer to form openings on the first conductor layer; forming gap walls on sidewall of the first conductor layer, and widths of these gap walls are smaller than widths of openings; on substrate, forming second conductor layer to be filled to the openings, and to expose top of each gap wall. Gap wall separates first conductor layer from second conductor layer. Width of gap wall is equal to space between first conductor layer and second conductor layer.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly relate to the manufacture method of the lead on a kind of semiconductor technology, and the method for dwindling lead and pattern-pitch.
Background technology
In integrated circuit flourish today, miniaturization of components and the productive setization trend that is inevitable, also be the important topic of industry develop actively, and influence the technology that the most very important key of component size just is photoetching (Photolithography) technology in the whole semiconductor technology.
With present semiconductor process techniques, want further to improve the resolution of photoetching process, employed machine, photomask or even light source all may incur a considerable or great expense.And, under the situation that the integration of each component placement increases day by day, layer with layer between stacked accuracy (Overlay Accuracy) also can be more and more harsh, the alignment issues between each rete (alignment issue) becomes very important.
For instance, please refer to Figure 1A to Figure 1B, it goes up the manufacturing process profile that forms word line for illustrating at shallow trench isolation from (STI).Please refer to Figure 1A, a plurality of shallow trench isolations are arranged in the substrate 100 from 101.Shallow trench isolation has been formed with one deck polysilicon layer 110 on 101.Has one deck patterning photoresist layer 120 on the polysilicon layer 110.Patterning photoresist layer 120 must cover the adjacent substrate 100 of two shallow trench isolations between 101 accurately.Afterwards, be mask with this patterning photoresist layer 120 again, etch the polysilicon layer 110 among Figure 1B.Yet, for fear of the restriction on the photoetching technique, the stacked error that the pattern of polysilicon layer 110 is produced in may the process because of the photoresist layer patternization, and depart to some extent, become shown in the dotted line among Figure 1B, can't be formed at two shallow trench isolations exactly between 101.This error will cause between the word line, or undesired electrical connection the between word line and the element, and cause the overall efficiency of semiconductor element and reliability to decline to a great extent, even may make element that situation about can't operate takes place.
Summary of the invention
In view of this, purpose of the present invention is exactly in the manufacture method that a kind of lead is provided and dwindles lead and the method for pattern-pitch, can break through the restriction of the minimum feature that original photoetching process can form, and can produce the less lead of live width.
Another object of the present invention provides a kind of manufacture method of lead and dwindles lead and the method for pattern-pitch, can avoid the alignment issues between each rete, helps to improve the overall efficiency and the reliability of element.
The present invention proposes a kind of method of dwindling wire pitch, and substrate at first is provided, and forms one deck first conductor layer then in substrate.Then, patterning first conductor layer forms a plurality of openings in first conductor layer.Sidewall in first conductor layer forms a plurality of clearance walls afterwards, and the width of these clearance walls is less than the width of opening.Then form second conductor layer and insert those openings in substrate, and expose the top of each clearance wall, wherein clearance wall is kept apart first conductor layer and second conductor layer, and the width of clearance wall is the spacing between first conductor layer and second conductor layer.
According to the described method of dwindling wire pitch of embodiments of the invention, above-mentioned first conductor layer is identical with the material of second conductor layer, and it for example is a doped polycrystalline silicon.
According to the described method of dwindling wire pitch of embodiments of the invention, above-mentioned formation second conductor layer, and the method that exposes the top of each clearance wall for example is prior to forming one deck second conductor layer in the substrate, and then etch-back first conductor layer and second conductor layer, up to the top that exposes each clearance wall, and till clearance wall keeps apart first conductor layer and second conductor layer.
According to the described method of dwindling wire pitch of embodiments of the invention, on be set forth in after the step that forms second conductor layer, also comprise removing clearance wall.
According to the described method of dwindling wire pitch of embodiments of the invention, above-mentioned isolation structure protrudes in substrate.Above-mentioned isolation structure comprises fleet plough groove isolation structure.
The present invention proposes a kind of manufacture method of lead, and substrate at first is provided, and has been formed with a plurality of isolation structures in the substrate at least.Then in substrate, form one deck conductor layer and one deck first mask layer in regular turn.Then, patterning first mask layer makes first mask layer cover substrate between per two adjacent isolation structures at least.Then, form a plurality of clearance walls in the sidewall of first mask layer, clearance wall is positioned on the isolation structure, and the width of clearance wall is less than the width between adjacent two isolation structures.Afterwards, form second mask layer in the substrate that comes out between first mask layer of patterning, and expose the top of each clearance wall, wherein clearance wall is kept apart first mask layer and second mask layer.Then, remove clearance wall, and be mask, patterning conductor layer with first mask layer and second mask layer.
According to the manufacture method of the described lead of embodiments of the invention, above-mentioned first mask layer is identical with the material of second mask layer, and it for example is a silicon nitride.
According to the manufacture method of the described lead of embodiments of the invention, the material of above-mentioned conductor layer comprises doped polycrystalline silicon.
Said method can be produced the less lead of live width by the thickness of control gap wall, increases process margin.This kind method can break through the restriction of the minimum feature that present machine can form, and reaches the effect of dwindling live width.Thus, also can avoid the alignment issues between each rete, help technology controlling and process, and further improve the overall efficiency and the reliability of element.
The present invention proposes a kind of method of dwindling pattern-pitch, and a substrate at first is provided, and has been formed with a plurality of elements in the substrate at least.Then, form first material layer in substrate, first material layer has a plurality of openings, exposes the part substrate.Then the sidewall in first material layer forms clearance wall.Then insert second material layer in opening, and expose the top of clearance wall, wherein clearance wall is kept apart first material layer and second material layer.
According to the described method of dwindling pattern-pitch of embodiments of the invention, on be set forth in opening and insert second material layer, and the step that exposes the top of clearance wall comprises: form second material layer in substrate, etch-back first material layer and second material layer again are up to the top that exposes clearance wall.
According to the described method of dwindling pattern-pitch of embodiments of the invention, on be set forth in after the step of inserting second material layer, also comprise removing clearance wall.
According to the described method of dwindling pattern-pitch of embodiments of the invention, on be set forth in before the step that forms first material layer, also be included in and form one in the substrate and treat etch layer.When formation remains the situation of etch layer, after removing the step of clearance wall, comprise that also with first material layer and second material layer be mask, remove part and treat etch layer.Treat that wherein etch layer for example is one deck conductor layer, its material for example is a doped polycrystalline silicon.And first material layer and second material layer for example are its materials of barrier layer for example is titanium, titanium nitride or silicon nitride.In treating under the etch layer it for example is to be formed with an interlayer dielectric layer (Inter-Layer Dielectric).
According to the described method of dwindling pattern-pitch of embodiments of the invention, above-mentioned second material layer is identical with the material of first material layer, for example is all conductor material.
Above-mentioned method of dwindling pattern-pitch can break through the restriction of machine, the formation by clearance wall and remove the gap that can make between the lead (treating the etch layer or first material layer/second material layer) and dwindle.Under the prerequisite of not changing machine, break through the restriction of the minimum feature that original photoetching process can form, and then improve element integration and process margin.
The present invention utilizes the formation of clearance wall, by the width of control gap wall, makes that the live width of technology is dwindled, even the resolution of photoetching process is relatively poor, still can reduce component size, and under set photoetching resolution, increase the integration of semiconductor process line allowance and raising element.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A to Figure 1B is for illustrating existing word line manufacturing process profile.
Fig. 2 A to Fig. 2 E is the manufacture method that illustrates a kind of lead of one embodiment of the invention.
Fig. 3 A to Fig. 3 F is the manufacturing process profile that illustrates a kind of pattern of one embodiment of the invention.
Fig. 3 G to Fig. 3 H is the manufacturing process profile that illustrates a kind of pattern of another embodiment of the present invention.
The simple symbol explanation
100,200,300: substrate
101: shallow trench isolation from
110: polysilicon layer
120: patterning photoresist layer
232: patterning photoresist layer
210: isolation structure
215a, 235a, 240a, 315a, 320a, 340a: width
220,308: treat etch layer
230,250,310,330: material layer
235,315,340: opening
240,320: clearance wall
305: inner layer dielectric layer
Embodiment
Fig. 2 A to Fig. 2 E is the manufacturing process profile that illustrates a kind of lead of one embodiment of the invention.
Please refer to Fig. 2 A, present embodiment is that example explains with the word line that forms memory.At least the substrate 200 that has a plurality of isolation structures 210 at first is provided, and the surface of substrate 200 also may comprise one dielectric layer (not illustrating).Isolation structure 210 for example be shallow trench isolation from.According to the resolution of the photoetching machine of present use, the width 215a between the isolation structure 210 for example is 90nm.Then, in this substrate 200, form one deck and treat etch layer 220.Treat that etch layer 220 for example is one deck conductor layer, with as the follow-up control grid or the usefulness of lead.The material for the treatment of etch layer 220 for example is the conductor material of doped polycrystalline silicon, metal or metal silicide etc., and its formation method for example is chemical vapour deposition technique or physical vaporous deposition.Then, cambium layer material layer 230 in substrate 200.Material layer 230 for example is the usefulness as mask layer in follow-up technology, and the material of material layer 230 has different etching selectivities with treating etch layer 220, and it for example is a silicon nitride.The formation method of material layer 230 for example is a chemical vapour deposition technique.
Then, please refer to Fig. 2 B, this material layer 230 of patterning makes material layer 230 cover substrate 200 between per two adjacent isolation structures 210 at least, and form a plurality of openings 235 in material layer 230.That is to say that material layer 230 is not to be the substrate 200 that covers between all adjacent isolation structures 210, but the compartment of terrain covers the substrate between the adjacent isolation structures 210.The method of this material layer 230 of patterning for example is prior to forming one deck patterning photoresist layer 232 on the material layer 230, is mask with patterning photoresist layer 232 then, removes part material layer 230 to form it.Wherein, the formation method of patterning photoresist layer 232 for example is prior to coating one deck photoresist layer (not illustrating) on the material layer 230, exposes, step of developing again.The method that removes part material layer 230 for example is the dry-etching method.The width 235a of opening 235 can that is to say that the formed live width of photoetching process is greater than 90nm greater than 90nm.
Afterwards, please refer to Fig. 2 C, remove patterning photoresist layer 232, and form a plurality of clearance walls 240 in the sidewall of material layer 230.These clearance walls 240 are preferably placed at isolation structure 210 tops, therefore, when carrying out the step of patterned material layer 230 of Fig. 2, promptly need consider the formation position of clearance wall 240.The method that removes patterning photoresist layer 232 for example is that dry type is delustered and caused resist or wet type and deluster and cause resist.The formation method of clearance wall 240 for example is that etch-back spacer material layer is to form it again prior to cambium layer spacer material layer (not illustrating) on the material layer 230.The method of etch-back spacer material layer for example is an anisotropic etch process, and the width 240a of clearance wall 240 can be controlled according to the thickness and the etched condition of spacer material layer that is deposited and material layer 230.The width 240a of clearance wall 240 is preferably less than the width 235a of opening 235, and less than the width 215a between the isolation structure 210.
Then, please refer to Fig. 2 D, in substrate 200, form material layer 250, and expose the top of clearance wall 240.The formation method of material layer 250 for example is that the material of material layer 250 for example is and material layer 230 identical materials, and then etch-back material layer 250 and material layer 230, and exposes clearance wall 240 prior to formation material layer 250 in the substrate 200.Wherein, the material of material layer 250 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.Etch-back material layer 250 for example is dry-etching method, wet etching or chemical mechanical milling method with the method for material layer 230, if use is chemical mechanical milling method, then the material layer 230,250 of clearance wall 240 meetings and two sides is contour.
Continuing it, please refer to Fig. 2 E, remove clearance wall 240, be that mask removes and partly treats etch layer 220 with material layer 230 and material layer 250 again.The method that removes clearance wall 240 for example is the dry-etching method.Remove part and treat that the method for etch layer 220 for example is an anisotropic etching process.
The etch layer 220 for the treatment of after the patterning can be used as lead.The pattern for the treatment of etch layer 220 (lead) can not produce because of the stacked error in the photoetching and depart from, and exposes substrate 200.This that is to say, by the formation of clearance wall 240 and the thickness of control gap wall 240, not only can form lead in more accurate location, and can not produce alignment issues between rete, and then raising process margin (processwindow), increase the overall efficiency and the reliability of semiconductor element, can also dwindle the spacing between lead, further improve the integration of element.
Fig. 3 A to Fig. 3 E is the manufacturing process profile that illustrates a kind of pattern-pitch of one embodiment of the invention.
Please refer to Fig. 3 A, the manufacture method of the pattern that the present invention proposes at first provides substrate 300, for example has been formed with a plurality of elements in the substrate 300, as semiconductor elements (not illustrating) such as metal oxide semiconductor transistor (MOS), memory, logic elements.One deck inner layer dielectric layer 305 has for example been formed on the top of substrate 300, and the material of inner layer dielectric layer 305 for example is silica, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), non-impurity-doped silex glass suitable dielectric materials such as (USG).Afterwards, form layer of material layer 310 in substrate 300, material layer 310 for example is a conductor layer in the present embodiment, and in subsequent technique as the usefulness of lead.The material of material layer 310 for example is conductor materials such as metal, metal silicide or doped polycrystalline silicon, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique etc., decides according to the difference of material.
Then, please refer to Fig. 3 B, patterned material layer 310 is to form a plurality of openings 315 in material layer 310.Opening 315 exposes substrate 300, in the present embodiment, promptly exposes inner layer dielectric layer 305.Patterned material layer 310 to form the method for a plurality of openings 315, for example is prior to forming one deck patterning photoresist layer (not illustrating) on the material layer 310, is mask with this patterning photoresist layer again, removes part material layer 310.The method that removes for example is the dry-etching method.Technologies such as the follow-up exposure of above-mentioned painting photoresist, development, the optimum resolution of its employed machine for example is 90nm, that is to say, the width 315a of opening 315 for example is 90nm.
Then, please refer to Fig. 3 C, in the sidewall formation clearance wall 320 of material layer 310.The formation method of clearance wall 320 for example is prior to forming one deck spacer material layer (not illustrating) in the substrate 300, carrying out anisotropic etching process again to form it.The material of spacer material layer for example is silica or silicon nitride, and its formation method for example is a chemical vapour deposition technique.The thickness 320a of clearance wall 320 can be controlled according to the thickness and the etched condition of spacer material layer 320 that is deposited and material layer 310.The thickness 320a of clearance wall 320 for example is the width 315a less than opening 315.
Then, please refer to Fig. 3 D, form layer of material layer 330 in substrate 300, material layer 330 fills up opening 315.The material of the material layer 330 of this step for example is identical with the material of material layer 310, for example is conductor material equally.The formation method of material layer 330 for example is technologies such as chemical vapour deposition technique or physical vaporous deposition.
Then, please refer to Fig. 3 E, etch-back material layer 330 and material layer 310 expose the top of clearance wall 320.The method of etch-back material layer 330 and material layer 310 for example is to remove material layer 330 on the clearance wall 320 with chemical mechanical milling method earlier, the mode that perhaps preferably is aided with over etching again, remove part material layer 330 and material layer 310, and expose clearance wall 320.Because clearance wall 320 has different etch-rates with material layer 310,330, therefore, clearance wall 320 can not be removed, and can retain between material layer 310 and the material layer 330.In the present embodiment, material layer 310 is the lead that desire forms with material layer 330.
Afterwards, please refer to Fig. 3 F, remove clearance wall 320, form material layer 310,330 with opening 340.The method that removes clearance wall 320 for example is an anisotropic etch process.The width 340a of opening 340 is the thickness 320a of clearance wall 320, thickness 320a by control gap wall 320, just can control the width 330a of opening 330, and then dwindle live width between the material layer 310,330 (lead), make live width be reduced to width 330a among Fig. 3 F by the width 315a among Fig. 3 B.That is to say, even have the resolution of machine now, only can form the width 315a of opening 315, utilize the formation method of above-mentioned pattern, the width of control gap wall 320 still can reach the effect of dwindling live width.
It is noted that, remove the step of clearance wall 320 among Fig. 3 F, can look actual needs and optionally carry out.For instance, if the circuit elements design layout need form one dielectric layer and cover material layer 310,330, then stay the clearance wall 320 between the material layer 310,330, just can stay some as the dielectric layer of follow-up layer of cover material 310,330, be used for spacer material layer 330 and material layer 310 (lead), and do not need to be removed.
What deserves to be mentioned is, present embodiment does not form one deck mask layer in addition on material layer 310 (treating etch layer), but directly in material layer 310 (treating etch layer), form a plurality of openings 315 earlier, and then form clearance wall 320 in material layer 310 sidewalls, insert material layer 330 afterwards again.This kind mode also can be applied to an embodiment.That is to say that the material layer 230 among Fig. 2 A (as the usefulness of mask layer) can optionally optionally be provided with, treat on the etch layer 220, in treating etch layer 220, form opening and the patterning photoresist layer 232 among Fig. 2 B is arranged at.As for the follow-up material layer of inserting in the opening, preferably has the material of same material (with reference to Fig. 3 E～Fig. 3 F) with treating etch layer 220.Those skilled in the art's its application as can be known repeats no more in this.
Fig. 3 G and Fig. 3 H, it is the manufacturing flow profile that illustrates a kind of pattern of another embodiment of the present invention.
Please refer to Fig. 3 G, the different of present embodiment and a last embodiment are to form before the material layer 310, treat etch layer 308 prior to having formed one deck on the inner layer dielectric layer 305.As for other and the corresponding rete of a last embodiment, just with the components identical symbol description it.Treat that etch layer 308 for example is one deck conductor layer, can be used to make lead.The material for the treatment of etch layer 308 for example is to comprise doped polycrystalline silicon, metal as copper, aluminium, tungsten, as the metal silicide of titanium silicide, nickle silicide, tungsten silicide or the conductor materials such as compound of metal/metal silicide, the formation method for the treatment of etch layer 308 for example is to be chemical vapour deposition technique or physical vaporous deposition according to its material.Cooperate material and the effect for the treatment of etch layer 308, material layer 310 for example is the usefulness as barrier layer in present embodiment.Material layer 310 should select etch-rate to be lower than the material for the treatment of etch layer 308, is beneficial to the etching mask that etch layer 308 is treated in follow-up conduct.The material of material layer 310 for example is a suitably material such as titanium/titanium nitride or silicon nitride.The formation method of the clearance wall 320 among Fig. 3 G is identical with clearance wall 320 among material and Fig. 3 E, repeats no more in this.It is noted that, by in the explanation of Fig. 3 D of the foregoing description and Fig. 3 E as can be known, clearance wall 320 should be selected the material different with material layer 310,330.
Then, please refer to Fig. 3 H, remove clearance wall 320.Then, be etching mask with material layer 310,330, remove come out treat etch layer 308, and in treating etch layer 308, form opening 350.The method that removes clearance wall 320 for example is the dry-etching method.Removing the method for the treatment of etch layer 308 that comes out for example is anisotropic etch process.The width 340a of formed opening 340 is identical with the width 320a of clearance wall 320, and wherein the etch layer 308 for the treatment of after the patterning is the lead of finishing.
In the foregoing description, except reaching the effect of dwindling live width equally, can also be by the setting of material layer 310,330, the quality on etch layer 308 surfaces is treated in protection, further the reliability and the stability of lift elements.
In sum, the present invention utilizes the formation of clearance wall and removes, and can overcome the restriction of present photoetching process resolution, need use the live width that the machine of (generation) of future generation can be finished and reach script.The feasible very high key stratum (critical layer) of accuracy requirement originally, its difficulty in process degree can reduce.Not only save manufacturing cost, reach the effect of dwindling live width, can also avoid the alignment issues between each rete, and then improve the overall efficiency and the reliability of element.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should the claim person of defining be as the criterion.
Claims (23)
1. method of dwindling wire pitch comprises:
Substrate is provided;
In this substrate, form first conductor layer;
This first conductor layer of patterning forms a plurality of openings in this first conductor layer;
Sidewall in this first conductor layer forms a plurality of clearance walls, and respectively the width of this clearance wall is less than the width of this opening; And
In this substrate, form second conductor layer and insert those openings;
Expose the respectively top of this clearance wall, wherein this clearance wall is kept apart this first conductor layer and this second conductor layer, and the width of this clearance wall is the spacing between this first conductor layer and this second conductor layer.
2. method of dwindling wire pitch as claimed in claim 1, wherein this first conductor layer is identical with the material of this second conductor layer.
3. method of dwindling wire pitch as claimed in claim 1, wherein the material of this first conductor layer and this second conductor layer comprises doped polycrystalline silicon.
4. method of dwindling wire pitch as claimed in claim 1, wherein exposing respectively, the method at the top of this clearance wall comprises etch-back or cmp step.
5. method of dwindling wire pitch as claimed in claim 1 wherein after the step that forms this second conductor layer, also comprises removing this clearance wall.
6. method of dwindling wire pitch as claimed in claim 1 also is included in before this first conductive layer forms, and have a plurality of isolation structures that protrude in this substrate and be arranged in this substrate, and those clearance walls is follow-up is formed on those isolation structures.
7. method of dwindling wire pitch as claimed in claim 6, wherein those isolation structures comprise fleet plough groove isolation structure.
8. the manufacture method of a lead comprises:
Substrate is provided, has been formed with a plurality of isolation structures in this substrate;
In this substrate, form the conductor layer and first mask layer in regular turn;
This first mask layer of patterning makes this first mask layer cover this substrate between per two adjacent isolation structures at least;
Sidewall in this first mask layer forms a plurality of clearance walls, and those clearance walls are positioned at those isolation structure tops, and the width of those clearance walls is less than the width between adjacent two isolation structures;
In this substrate that comes out between this first mask layer of patterning, form second mask layer;
Expose the respectively top of this clearance wall, this clearance wall is kept apart this first mask layer and this second mask layer;
Remove this clearance wall; And
With this first mask layer and this second mask layer is mask, this conductor layer of patterning.
9. the manufacture method of lead as claimed in claim 8, wherein this first mask layer is identical with the material of this second mask layer.
10. the manufacture method of lead as claimed in claim 9, wherein the material of this first mask layer and this second mask layer comprises silicon nitride.
11. the manufacture method of lead as claimed in claim 8, wherein the material of this conductor layer comprises doped polycrystalline silicon.
12. a method of dwindling pattern-pitch comprises:
Substrate is provided, has been formed with a plurality of elements in this substrate at least;
Form first material layer in this substrate, this first material layer has a plurality of openings, exposes this substrate of part;
Sidewall in this first material layer forms clearance wall; And
Insert second material layer in those openings, and expose the top of this clearance wall, wherein this clearance wall is kept apart this first material layer and this second material layer, and the width of this clearance wall is the spacing between this first material layer and this second material layer.
13. method of dwindling pattern-pitch as claimed in claim 12 wherein after the step of inserting this second material layer, also comprises removing this clearance wall.
14. method of dwindling pattern-pitch as claimed in claim 13 wherein before the step that forms this first material layer, also is included in to form in this substrate and treats etch layer.
15. method of dwindling pattern-pitch as claimed in claim 14 wherein after the step that removes this clearance wall, comprises that also with this first material layer and this second material layer be mask, this treats etch layer to remove part.
16. method of dwindling pattern-pitch as claimed in claim 15, wherein this treats that etch layer is a conductor layer.
17. method of dwindling pattern-pitch as claimed in claim 16, wherein this material for the treatment of etch layer comprises doped polycrystalline silicon.
18. method of dwindling pattern-pitch as claimed in claim 16, wherein this first material layer and this second material layer are barrier layer.
19. method of dwindling pattern-pitch as claimed in claim 18, wherein the material of this barrier layer comprises titanium, titanium nitride or silicon nitride.
20. method of dwindling pattern-pitch as claimed in claim 15, wherein this treats to be formed with interlayer dielectric layer under the etch layer.
21. method of dwindling pattern-pitch as claimed in claim 12 is wherein inserted this second material layer in those openings, and the step that exposes the top of this clearance wall comprises:
In this substrate, form this second material layer; And
This first material layer of etch-back and this second material layer are up to the top that exposes this clearance wall.
22. method of dwindling pattern-pitch as claimed in claim 12, wherein this second material layer is identical with the material of this first material layer.
23. method of dwindling pattern-pitch as claimed in claim 22, wherein the material of this first material layer and this second material layer comprises conductor material.
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| CNB2005101297675A CN100437974C (en) | 2005-12-05 | 2005-12-05 | Lead mfg. method and method for shortening distance between lead an pattern |
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| CN100437974C CN100437974C (en) | 2008-11-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102693898A (en) * | 2011-03-21 | 2012-09-26 | 华邦电子股份有限公司 | Method for narrowing pitch |
| WO2022226875A1 (en) * | 2021-04-29 | 2022-11-03 | 京东方科技集团股份有限公司 | Display substrate, fabrication method therefor, and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895740A (en) * | 1996-11-13 | 1999-04-20 | Vanguard International Semiconductor Corp. | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
| TW379432B (en) * | 1998-09-14 | 2000-01-11 | Worldwide Semiconductor Mfg | Method of manufacturing self-aligned shield wires |
| CN1391277A (en) * | 2001-06-07 | 2003-01-15 | 矽统科技股份有限公司 | Internal connecting line structure with dual-layer electric partition and its preparing process |
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2005
- 2005-12-05 CN CNB2005101297675A patent/CN100437974C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102693898A (en) * | 2011-03-21 | 2012-09-26 | 华邦电子股份有限公司 | Method for narrowing pitch |
| CN102693898B (en) * | 2011-03-21 | 2016-02-24 | 华邦电子股份有限公司 | Contract closely spaced method |
| WO2022226875A1 (en) * | 2021-04-29 | 2022-11-03 | 京东方科技集团股份有限公司 | Display substrate, fabrication method therefor, and display device |
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| CN100437974C (en) | 2008-11-26 |
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