CN1979197A - Method for increasing synchronous detecting number of chips - Google Patents
Method for increasing synchronous detecting number of chips Download PDFInfo
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- CN1979197A CN1979197A CN 200510111284 CN200510111284A CN1979197A CN 1979197 A CN1979197 A CN 1979197A CN 200510111284 CN200510111284 CN 200510111284 CN 200510111284 A CN200510111284 A CN 200510111284A CN 1979197 A CN1979197 A CN 1979197A
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Abstract
The invention discloses a method to increase testing chip quantity. One probe desk is shared by plural testing machines. And probe card or hardware interface would be shared by tested object. It integrates testing functions of plural independent testing machine. It has the advantages of increasing the quantity of testing chips, lowering cost, decreasing testing time and improving testing efficiency.
Description
Technical field
The present invention relates to a kind of method of testing of semiconductor devices, the method that particularly a kind of chip is tested simultaneously.
Background technology
In the semiconductor product test, be to use tester that product is carried out single survey at first, along with the development in market, the raising of measuring technology had proposed promptly a plurality of products to be tested simultaneously with the method for surveying afterwards.Method of testing has improved testing efficiency simultaneously, has reduced testing expense, but this method is when improving with quantitation, the manufacturing cost of tester is also along with increasing, and along with the increase with quantitation, the reliability of tester test, stability also is faced with great challenge.
At present, realize that the method for testing with brake is at a single tester, realize synchronous detecting number by increasing test channel.Realize by this method becoming complicated in its hardware design and the control with surveying.Its manufacturing cost is along with increasing.In the configuration of test macro, a tester must connect a probe station (probe station), a probe.
Also has a kind of situation, many companies that test service is provided, originally bought the less tester of a lot of realization synchronous detecting number functions, improve testing efficiency, the tester that more synchronous detecting number abilities are provided can only be bought, so, the cost of buying new tester certainly will be additionally increased, old tester originally can not use, and causes waste.
Tester of every like this increase will increase a probe station and a probe, also at double growth of testing apparatus investment.And the investment that had both reduced test resource to improve testing efficiency then be the target that test manufacturer and testing apparatus provider are concerned about always and pursue.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that increases synchronous detecting number of chips, can merge the test function of many platform independent tester, obviously improves testing efficiency.
For solving the problems of the technologies described above, it is main frame that the present invention increases the tester that the method for synchronous detecting number of chips sets in many testers, other tester is a slave, all testers use same probe and same probe station, main frame is responsible for test command is sent to slave, detect the state of slave, and the test result of each slave is fetched main frame.
Many shared same probe of tester and probe station have reduced setting cost in the method provided by the invention, have made full use of test resource, have reduced the test duration, have improved testing efficiency.
Description of drawings
Fig. 1 is a test macro connection layout of the present invention;
Fig. 2 is an operational flowchart of the present invention.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing.
The present invention includes the framework with software built of test macro.The building method of test macro as shown in Figure 1, a tester of at first setting in many testers is a main frame, other tester is that slave 1 is to slave N.This N+1 platform tester uses same probe and same probe station.Connect with netting twine between main frame and the slave, cable is used in being connected of tester and probe.
The software architecture method is, uses general purpose interface bus (GPIB) agreement to carry out communication between main frame and the probe station, and main frame is responsible for the control of test mode, the transmission of test result.Use TCP (TCP/IP) to carry out communication between main frame and the slave, main frame will be controlled test procedure and download in the slave, the state of detecting slave is responsible for test command is sent to slave, and the test result of each slave is fetched main frame.Be separate between the slave, after slave is received the order that begins to test that main frame sends, promptly begin test, after the slave end of test (EOT) test result is passed back main frame, wait for the beginning of test next time then.
Referring to Fig. 2, communication and operation in the following manner between probe station, main frame, the slave:
After step 1, main frame are assigned the order that begins to test to each slave,
Step 2, each slave are promptly tested measured body (DUT) after receiving the beginning test command;
Step 3, main frame adopt poll (polling) mode to detect each slave and whether finish test, if slave is finished test, promptly return test result;
Step 4, after all slaves were all passed test result back, main frame was to its processing and be transferred to probe station;
Step 5 after probe station is handled test result well, transmits a response signal and gives main frame;
Step 6, main frame are assigned the order that begins to test to each slave after receiving the response signal that probe station transmits again.Execution in step 1 is to step 5 then, so circulation, until main frame till each slave sends unloading test procedure.
Claims (3)
1, a kind of method that increases synchronous detecting number of chips, adopt probe, probe station and tester test measured object, it is characterized in that, a tester of setting in many testers is a main frame, and other tester is a slave, and all testers use same probe and same probe station, main frame will be controlled test procedure and download in the slave, test command is sent to slave, detect the state of slave, and the test result of each slave is fetched main frame.
2, the method for increase synchronous detecting number of chips according to claim 1 is characterized in that, connects with netting twine between main frame and the slave, and tester is connected with cable with probe; Use the general purpose interface bus agreement to carry out communication between main frame and the probe station, main frame is responsible for the control of test mode, the transmission of test result; Use TCP to carry out communication between main frame and the slave.
3, the method for increase synchronous detecting number of chips according to claim 2 is characterized in that, is separate between the slave.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510111284 CN1979197A (en) | 2005-12-08 | 2005-12-08 | Method for increasing synchronous detecting number of chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510111284 CN1979197A (en) | 2005-12-08 | 2005-12-08 | Method for increasing synchronous detecting number of chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1979197A true CN1979197A (en) | 2007-06-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510111284 Pending CN1979197A (en) | 2005-12-08 | 2005-12-08 | Method for increasing synchronous detecting number of chips |
Country Status (1)
| Country | Link |
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| CN (1) | CN1979197A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441625B (en) * | 2007-11-23 | 2010-11-03 | 上海华虹Nec电子有限公司 | Method for counting use amount of probe card by using probe card tester |
| CN103533020A (en) * | 2012-06-29 | 2014-01-22 | 格罗方德半导体公司 | Method and system for customer specific test system allocation in a production environment |
| CN104133172A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Novel test development method for improving simultaneous test number |
| CN109633417A (en) * | 2019-01-31 | 2019-04-16 | 上海华虹宏力半导体制造有限公司 | Multi-chip is the same as geodesic structure and method |
| CN110161977A (en) * | 2018-02-13 | 2019-08-23 | 京元电子股份有限公司 | Measuring system and its measurement method |
| CN111487519A (en) * | 2020-04-07 | 2020-08-04 | 长江存储科技有限责任公司 | Test system and method |
| CN111564383A (en) * | 2020-05-16 | 2020-08-21 | 南京宏泰半导体科技有限公司 | Method for improving productivity of semiconductor test system and semiconductor test system |
-
2005
- 2005-12-08 CN CN 200510111284 patent/CN1979197A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441625B (en) * | 2007-11-23 | 2010-11-03 | 上海华虹Nec电子有限公司 | Method for counting use amount of probe card by using probe card tester |
| CN103533020A (en) * | 2012-06-29 | 2014-01-22 | 格罗方德半导体公司 | Method and system for customer specific test system allocation in a production environment |
| CN104133172A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Novel test development method for improving simultaneous test number |
| CN104133172B (en) * | 2014-08-08 | 2017-09-29 | 上海华力微电子有限公司 | It is a kind of to improve with the novel test development approach for surveying number |
| CN110161977A (en) * | 2018-02-13 | 2019-08-23 | 京元电子股份有限公司 | Measuring system and its measurement method |
| CN110161977B (en) * | 2018-02-13 | 2022-04-12 | 京元电子股份有限公司 | Measuring system and measuring method thereof |
| CN109633417A (en) * | 2019-01-31 | 2019-04-16 | 上海华虹宏力半导体制造有限公司 | Multi-chip is the same as geodesic structure and method |
| CN111487519A (en) * | 2020-04-07 | 2020-08-04 | 长江存储科技有限责任公司 | Test system and method |
| CN111487519B (en) * | 2020-04-07 | 2024-05-07 | 长江存储科技有限责任公司 | Test system and method |
| CN111564383A (en) * | 2020-05-16 | 2020-08-21 | 南京宏泰半导体科技有限公司 | Method for improving productivity of semiconductor test system and semiconductor test system |
| CN111564383B (en) * | 2020-05-16 | 2021-01-05 | 南京宏泰半导体科技有限公司 | Method for improving productivity of semiconductor test system and semiconductor test system |
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Open date: 20070613 |