CN1947259A - 具有雪崩保护的高电流mos器件及操作方法 - Google Patents
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Abstract
尤其在高电流应用中,在MOS晶体管(51)的漏区(74)中产生的碰撞离子化引起的电子-空穴对会导致寄生双极晶体管(38)破坏性地导通。空穴流经MOS晶体管(51)的具有本征电阻的体区(76)到达典型保持在较低电压例如地的源区(80)。空穴电流导致作为基区(42)的体区(76)电压上升。该上升的基区电压就是导致寄生双极晶体管(38)导通的原因。沟道电流经过源区(80)和体区(76)之间的阻抗(62),作为发射区(44)的源区(80)和体区(76)之间的电压升高,可以大大减小上述可能性。当基区电压增高时,其导致发射区电压增高,从而阻止寄生双极晶体管(38)导通。
Description
技术领域
本发明一般涉及半导体,并且更具体地,涉及具有雪崩保护的高电流MOS器件及操作方法。
背景技术
随着功率器件尺寸的连续缩短,能量性能引起很大的关注。实际上,功率MOS器的尺寸不再受到工作电阻的限制,取而代之受到能量性能的限制。就自动化应用来说,对于功率MOS器件的能量需求能够导致器件温度显著升高,某些时候会导致相应的器件由于迅速跳回而电失效。此外,功率MOS器件中固有的寄生双极晶体管导致个别器件电-热失效,阻碍其达到器件的纯发热极限。
图1是根据现有技术的LDMOSFET器件10的截面图。LDMOSFET器件1O包括P-型衬底12,N-阱区14,P体区16,N+扩散区18和20,以及P+扩散区22。注意N+扩散区20与P+扩散区22交叠一定长度。N+扩散区18和N-阱14构成漏区。N+扩散区20和P+扩散区22构成器件1O的源区。P+扩散区22提供与P体区16的接触。
LDMOSFET器件10还包括氧化隔离区24,电介质26(包括栅电极28下方的栅电介质)和栅电极28。LDMOSFET器件10还包括分别用于漏和源区的电接触30和32(例如,某些类型的硅化物)。注意源接触32横跨并连接N+扩散区20和P+体接触区22。引用标记34和36表示的导电材料分别连接漏和源区至器件10的顶部。
LDMOSFET器件10的一个缺点是它还包括固有的寄生双极晶体管38。寄生双极晶体管38包括集电区40(对应于N-阱40和N+扩散区18),基区42(对应于P体区16),和发射区22(对应于N+扩散区20),以及配置在基区42和发射区44之间表示为RB1的电阻元件46(对应于位于P体区16内沿着N+扩散区20的横向尺寸延伸的部分P体区16)。发射区44有效地连接至P+体接触22和N+扩散区20。在高电流导通和高漏-源电压的操作条件下,寄生双极晶体管38会导致器件10电-热失效,阻碍器件10达到其纯发热极限。
需要一种克服上述问题的改善的高电流MOS器件和方法。
发明内容
根据一个实施例,半导体器件包括衬底、衬底中具有P型本底掺杂并具有顶表面的有源区、具有第一P级的P体区,形成于P体区的顶表面处并形成晶体管沟道的第一边界的N-型区、与P体区隔开并形成沟道的第二边界的N-漂移区以及连接在P体区和形成在P体区中的N-型区之间的阻抗。
附图说明
通过例子示例本发明的实施例,但不限于附图,其中相似的标记表示相似的元件,其中;
图1是根据现有技术的LDMOSFET的截面图;
图2是根据本发明的一个实施例的包括阻抗的混合LDMOSFET的示意图;
图3是根据本发明的一个实施例的包括齐纳二极管的混合LDMOSFET的示意图;
图4是图3的根据本发明的一个实施例的包括齐纳二极管的混合LDMOSFET的截面图;
图5是根据本发明的一个实施例的包括电阻元件的混合LDMOSFET的示意图;
图6是图5的根据本发明的一个实施例的包括混合LDMOSFET内部的电阻元件的混合LDMOSFET的截面图;
图7是图5的根据本发明的一个实施例的包括混合LDMOSFET外部的电阻元件的混合LDMOSFET的截面图;
图8是在大约25摄氏度的第一温度下和150摄氏度的第二温度下比较公知LDMOSFET和本发明的混合LDMOSFET的功率处理性能,以瓦特表示的功率与对以伏特表示的漏-源电压的曲线表示图;
图9是比较公知的体/源区短路的LDMOSFET和本发明的体/源区分离的混合LDMOSFET的功率处理性能,以瓦特表示的功耗对以摄氏度表示的温度的曲线表示图。
熟练技术人员明白附图中的元件是为了简化和清楚示例的目的,并未按尺寸绘制。例如,为了有助于进一步理解本发明的实施例,在附图中可以相对于其它元件而言夸大某些元件的尺寸。
具体实施方式
在高电流应用中,MOS晶体管的漏区中产生电子-空穴对,导致固有的寄生双极晶体管破坏性地导通。空穴穿过MOS晶体管具有本征电阻的体区到达通常保持在低电压例如地的源区。空穴电流导致作为基区的体区电压上升。该上升的基区电压就是导致寄生双极晶体管导通的原因。沟道电流经过源区和体区之间的阻抗,作为发射区的源区和体区之间的电压升高,可以大大减小上述可能性。当基区电压增高时,其导致发射区电压增高,从而阻止寄生双极晶体管导通。
因此,为了实现功率LDMOSFET器件实际的热性能,必须使LDMOSFET器件的固有寄生双极晶体管不起作用。使固有寄生双极晶体管不起作用,除掉了对于LDMOSFET器件功耗性能的电学影响。在一个实施例中,源接触浮置,电阻或低压齐纳二极管设置于源和体接触之间。此外,体接触视作最终器件的有效源区端子。
本发明的实施例中,当电流流经LDMOSFET时,电流在源-体区结上产生反向偏压,从而阻止固有寄生双极晶体管在能量性能测试情形中开启。而且,能量性能能够比现有公知器件提高40%。
再看附图,图2是根据本发明的一个实施例的包括阻抗62的混合LDMOSFET 50的示意图。混合LDMOSFET 50包括栅极52、漏区54、和源区56。LDMOSFET 50还包括与源区56分开的体接触58,其中体接触58连接到器件50的有效源区60。阻抗62连接实际的源区56和体接触58,以激活有效源区60。阻抗62可以包括有源阻抗或无源阻抗,如特殊LDMOSFET实施所需要的。
图3是根据本发明的一个实施例的包括齐纳二极管64的混合LDMOSFET 51的示意图。混合LDMOSFET 51包括栅极52、漏区54和源区56。LDMOSFET 51还包括与源区56分开的体接触58,其中体接触58连接到器件51的有效源区60。齐纳二极管64连接实际的源区56和体接触58,以激活有效源区60,进一步如这里所述。
图4是图3的根据本发明的一个实施例的包括齐纳二极管64的混合LDMOSFET 51的截面图。LDMOSFET器件51包括P-型衬底72、N-阱74、P体区76、N+扩散区78和80以及P+扩散区82。注意N+扩散区80与P+扩散区82交叠一定长度。而且,N+扩散区78和N-阱74构成LDMOSFET 51的漏区。N+扩散区80构成LDMOSFET器件51实际的源区。
再注意N+扩散区80与P+扩散区82交叠一定长度。并注意当不存在接触两个区域的交叠电接触时,N+扩散区80与P+扩散区82交叠一定长度的组合体形成齐纳二极管(如图3的引用标记64所示)。齐纳二极管64连接实际的源区80和体接触82,以激活有效源区(如图3的引用标记60所示)。此外,P+扩散区82提供与P体区76的接触(如图3的引用标记58所示)。
仍参照图4,LDMOSFET器件51还包括氧化隔离区84、电介质86(包括栅电极88下方的栅电介质)和栅电极88。LDMOSFET器件51还包括分别用于漏和有效源区的电接触90和92(例如,任意适合的硅化物)。注意电接触92完全包含在与P+扩散区82重叠的区域内。换句话说,电接触92不横跨、也不连接N+扩散区80(对应于器件51的实际源区)。因此,电接触92不会干扰齐纳二极管64。而且,提供引用标记94和96表示的导电材料以分别连接漏和有效源区至器件51的顶部。
图4的LDMOSFET器件51的一个优点是,虽然它也包括固有寄生双极晶体管38,但是功率处理性能显著好于图1的实施例。寄生双极晶体管38包括集电区40(对应于N-阱74和N+扩散区78),基区42(对应于P体区76)和发射区44(对应于N+扩散区80)以及配置在基区42和发射区44之间表示为RB1的电阻元件46(对应于位于P体区76内沿着N+扩散区80的横向尺寸延伸的部分P体区76)。发射区44经由齐纳二极管64有效地连接至P+体接触82。
在LDMOSFET器件51的高电流导通和高漏-源电压的操作条件下,齐纳二极管64在寄生双极晶体管38的基区42和发射区44之间产生反向偏压。反向偏压防止寄生双极晶体管38过早导通。换句话说,反向偏压抑制了寄生双极晶体管38的开启。反向偏压延缓了寄生双极晶体管38过早导通,因此抑制其开启,与导通响应将导致器件51电-热失效。因此,齐纳二极管64提供的反向偏压能够使器件51达到基本上接近其纯发热极限的功率处理性能。
图5是根据本发明的一个实施例的包括电阻元件66的混合LDMOSFET器件53的示意图。混合LDMOSFET53包括栅极52、漏区54和源区56。LDMOSFET53还包括与源区56分开的体接触58,其中体接触58连接到器件53的有效源区60。电阻元件66连接实际的源区56和体接触58,以激活有效源区60,进一步如这里所述。
图6是图5的根据本发明的一个实施例的包括混合LDMOSFET器件内部的电阻元件66的混合LDMOSFET 53的截面图。LDMOSFET器件53包括P-型衬底72、N-阱区74、P体区100、N+扩散区78和102、以及P+扩散区104。注意N+扩散区102不与P+扩散区104交叠,而是间隔开预定间距。N+扩散区78和N-阱74构成LDMOSFET 53的漏区。N+扩散区102构成LDMOSFET器件53实际的源区。
再注意N+扩散区102不与P+扩散区104交叠,而是间隔开预定间距。然而,提供电阻元件110,其中电阻元件连接实际的源区102和体接触104,以激活有效源区(如图5的引用标记60所示)。注意在图6的实施例中,电阻元件110在LDMOSFET器件53的内部。此外,P+扩散区104提供与P体区100的接触(如图5的引用标记58所示)。
仍参照图6,LDMOSFET器件53还包括氧化隔离区84、电介质86(包括栅电极88下方的栅电介质)和栅电极88。LDMOSFET器件53还包括分别用于漏和有效源区的电接触90和106(例如,任意适合的硅化物)。注意电接触106可完全包含在与P+扩散区104重叠的区域内。换句话说,电接触106不横跨、也不连接N+扩散区102(对应于器件53的实际源区)。此外,提供引用标记94和116表示的导电材料以分别连接漏和有效源区至器件53的顶部。
仍然参照图6,提供附加的电接触108、112和114。导电材料116经由电接触112连接电阻元件110的一端至器件53的顶部。导电材料118经由电接触114连接电阻元件110的另一端至器件53的顶部,并还经由电接触108连接实际的源区102至器件53的顶部。
图7是图5的根据本发明的一个实施例的包括混合LDMOSFET器件外部的电阻元件113的混合LDMOSFET 55的截面图。图7的实施例与图6类似,但具有以下不同。导电材料116连接至LDMOSFET器件55的顶部和外部电阻元件113的一端。因此,导电材料116连接至器件55的有效源区。导电材料118经由电接触108连接实际源区102至器件55的顶部。导电材料还连接至外部电阻元件114的另一端。
图8是在大约25摄氏度的第一温度下和150摄氏度的第二温度下比较公知LDMOSFET和根据本发明的一个实施例的混合LDMOSFET的功率处理性能,以瓦特表示的功率对以伏特表示的漏-源电压的曲线表示图120。关于曲线122和124,在25摄氏度的低温操作下,曲线122表示根据本发明的一个实施例的混合LDMOSFET的功率处理性能,曲线124表示公知LDMOSFET器件的功率处理性能。对于25℃下大约为36伏特的VDS,德耳塔功率(或能量差)大约为百分之十(10%)。对于25℃下大约为54伏特的VDS,德耳塔功率(或能量差)大约为百分之二十四(24%)。
仍参见图8,关于曲线126和128,在150摄氏度的高温操作下,曲线126表示根据本发明的一个实施例的混合LDMOSFET的功率处理性能,曲线128表示公知LDMOSFET器件的功率处理性能。对于150℃下大约为34伏特的VDS,德耳塔功率(或能量差)大约为百分之三十三(33%)。对于150℃下大约为54伏特的VDS,德耳塔功率(或能量差)大约为百分之二十四(44%)。因此,在低的高的温度下有明显的能量性能改善。此外,在失效测试期间,在根据本发明的一个实施例的LDMOSFET器件的中心测得的温度从650K增高到720K,这为能量的显著增高提供了一些解释。
图9是比较公知的体/源区短路的LDMOSFET和本发明的体/源区分离的混合LDMOSFET的功率处理性能,以瓦特表示的功耗对以摄氏度表示的温度的曲线表示图130。关于曲线132和134,曲线132表示根据本发明的一个实施例的混合LDMOSFET的功率处理性能,其中体接触和实际源区分离(即,彼此不直接接触)。曲线134表示公知LDMOSFET器件的功率处理性能,其中体接触和源区短接在一起(即,彼此直接接触)。在大约25℃的低温操作下,德耳塔功率(或能量差)大约为百分之四十四(44%)。在大约150℃的高温操作下,德耳塔功率(或能量差)大约为百分之五十六(56%)。
因此,半导体器件的一个实施例包括衬底、衬底中具有P型本底掺杂并具有顶表面的有源区、具有第一P级的P体区,形成于P体区的顶表面处并形成晶体管沟道的第一边界的N-型区、与P体区隔开并形成沟道的第二边界的N-漂移区和连接在P体区和形成在P体区中的N-型区之间的阻抗。P体区具有本征电阻。当高电流流经沟道时,N体区产生电子-空穴对。电子-空穴对中的至少一些空穴经过P体区,导致P体区中的电压降。经过沟道的电流流经阻抗,从而在源区和P体区之间产生反向偏压,以补偿P体区中的电压降。
另一个实施例中,具有寄生双极晶体管的MOS晶体管包括具有MOS晶体管的沟道并具有本征电阻的第一导电类型的第一体区。第一体区是寄生双极晶体管的基区。MOS晶体管还包括邻接沟道并作为寄生双极晶体管的发射区的源区。漏区邻接沟道区并作为寄生晶体管的集电区。此外,阻抗连接在第一体区和源区之间。响应于沟道中的高电流,漏区产生电子-空穴对。电子空穴对中的至少一些空穴经过第一体区到达源区,导致寄生双极晶体管的基区上的电压增高。经过沟道的电流流经阻抗。最后,阻抗使寄生晶体管的发射区的电压上升得足够高,以防止寄生双极晶体管导通。
在另一实施例中,体区内部具有栅极、漏区、源区和沟道的晶体管的操作方法包括以下步骤。从漏区经沟道向源区驱动高电流。响应于沟道中的高电流,漏区中产生电子-空穴对。电子空穴对中的至少一些空穴经过第一体区到达源区,导致体区中的电压差。最后,源区和体区之间产生电压差,以补偿体区中的电压差,其中产生包括高电流经过连接在源区和体区之间的阻抗。
在上述说明中,参照多个实施例描述了本发明。然而,本领域普通技术人员明白能够在不脱离下面权利要求给出的本实施例范围的情形下做各种修改和改变。例如,这里的实施例可以是集成电路的一部分。因此,说明书和附图将作为示例,而非限制性,并且所有修改都被包括在本实施例的范围内。
上面根据特定实施例描述了益处、优点和问题的解决方法。然而,引起任何益处、优点或解决方法产生或更加显著的益处、优点或解决方法并不构成为任一或所有权利要求的关键的、必需的或核心的特征或要素。这里用到的术语“包括”、“包含”或任一其它变化,意味着覆盖了非排它的内容,例如包括一系列要素的工艺、方法、物品、或装置不仅仅包括这些要素,而且包括没有明确列出或者这些工艺、方法、物品或装置固有的要素。
Claims (20)
1.一种半导体器件(50,51,53,55),包括:
衬底(72);
衬底(72)中的具有P型本底掺杂并具有顶表面的有源区;
具有第一P级的P体区(76,100);
形成于P体区(76,100)的顶表面处并形成晶体管沟道的第一边界的N-型区(80,102);
与P体区(76,100)隔开并形成沟道的第二边界的N-漂移区(74);和
连接在P体区(76,100)和形成在P体区中的N-型区(80,102)之间的阻抗(62)。
2.权利要求1的所述半导体器件,还包括N漂移区(74)中用作漏接触的N-型重掺杂区(78)。
3.权利要求1的所述半导体器件,其中:
P体区(76,100)具有本征电阻;
响应于高电流流经沟道,N漂移区(74)产生电子-空穴对;
电子-空穴对中的至少一些空穴经过P体区(76,100),导致P体区中的电压降;和
其中经过沟道的电流流经阻抗(62),从而在源区和P体区之间产生反向偏压,以补偿P体区中的电压降。
4.权利要求3的所述半导体器件,其中阻抗(62)包括电阻(66)或齐纳二极管(64)。
5.权利要求1的所述半导体器件,其中P体区(76,100)具有大于P-型本底掺杂(72)的掺杂浓度。
6.权利要求5的所述半导体器件,还包括P体区中用作形成阻抗(62)和P体区(76,100)之间的接触的P-型重掺杂区(82,104)。
7.权利要求1的所述半导体器件,其特征在于作为集成电路的一部分,其中阻抗(62)在集成电路的外部或在集成电路的内部。
8.一种具有寄生双极晶体管(38)的MOS晶体管(50,51,53,55),包括:
具有MOS晶体管的沟道并具有本征电阻的第一导电类型的第一体区(76,100),其中第一体区是寄生双极晶体管的基区;
邻接沟道并作为寄生双极晶体管的发射区的源区(80,102);
邻接沟道区并作为寄生晶体管的集电区的漏区(74);
连接在第一体区(76,100)和源区(80,102)之间的阻抗(62)。
9.权利要求8的所述MOS晶体管,其中:
响应于沟道中的高电流,漏区(74)产生电子-空穴对;
电子空穴对中的至少一些空穴经过第一体区(76,100)到达源区(80,102),并且导致寄生双极晶体管(38)的基区上的电压增高;
经过沟道的电流流经阻抗(62);和
阻抗(62)使寄生晶体管(38)的发射区上的电压上升得足够高,以防止寄生双极晶体管导通。
10.权利要求9的所述半导体器件,其中阻抗(62)包括电阻(66)或齐纳二极管(64)。
11.权利要求9的所述半导体器件,还包括第一体区(76,100)中用作形成阻抗(62)和第一体区(76,100)之间的接触的第一导电类型的重掺杂(104)。
12.权利要求9的所述半导体器件,其特征在于作为集成电路的一部分,其中阻抗(62)在集成电路的外部或在集成电路的内部。
13.一种具有MOS晶体管(53,55)的集成电路,包括:
衬底(72);
衬底(72)中的具有顶表面的有源区;
具有MOS晶体管的沟道并为第一导电类型的第一体区(100);
邻接沟道并为第二导电类型的MOS晶体管的源区(102);
邻接沟道区并为第二导电类型的漏区(74);
用于接收集成电路外部的第一连接并连接到第一体区的第一端子(116);
用于接收集成电路外部的第二连接并连接到源区(102)的第二端子(118)。
14.权利要求13的所述MOS晶体管,还包括连接在第一端子(116)和第二端子(118)之间的阻抗(62),其中:
响应于沟道中的高电流,漏区(74)产生电子-空穴对;
电子空穴对中的至少一些空穴经过第一体(100)到达源区(102),并且导致第一体区中的电压差;
经过沟道的电流流经阻抗(62);和
阻抗(62)使电压上升,以补偿第一体区(100)中的电压差。
15.权利要求14的所述半导体器件,其中阻抗包括电阻或齐纳二极管。
16.一种具有MOS晶体管的集成电路,包括:
衬底(72);
衬底(72)中的具有顶表面的有源区;
具有MOS晶体管的沟道的第一体区(76,100),第一体区在顶表面处;
邻接沟道的MOS晶体管的源区(80,102),源区在顶表面处;
邻接沟道区的MOS晶体管的漏区(74),漏区在顶表面处;和
用于在源区(80,102)和第一体区(76,100)之间连接阻抗的阻抗装置(62)。
17.权利要求16的所述MOS晶体管,还包括连接在源区(80,102)和第一体区(76,100)之间的阻抗(62),其中:
响应于沟道中的高电流,漏区(74)产生电子-空穴对;
电子空穴对中的至少一些空穴经过第一体区(80,102)到达源区(76,100),并且导致第一体区中的电压差;
经过沟道的电流流经阻抗(62);和
阻抗(62)使电压上升,以补偿第一体区中的电压差。
18.权利要求16的所述MOS晶体管,其中体区(100)接地,阻抗装置(62)用于在源区(80,102)和地之间产生电压差。
19.一种在体区(76,100)内部具有栅极(88)、漏区(74)、源区(80,102)和沟道的晶体管(50,51,53,55)的操作方法,包括:
从漏区(74)经沟道向源区(80,102)驱动高电流;
响应于沟道中的高电流,在漏区(74)中产生电子-空穴对;
电子空穴对中的至少一些空穴经过体区(76,100)到达源区(80,102),导致体区中的电压差;和
在源区(80,102)和体区之间产生电压差,以补偿体区中的电压差。
20.权利要求19的所述方法,其中产生包括高电流经过连接在源区(80,102)和体区(76,100)之间的阻抗(62)。
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US10/836,730 | 2004-04-30 | ||
US10/836,730 US20050242371A1 (en) | 2004-04-30 | 2004-04-30 | High current MOS device with avalanche protection and method of operation |
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US (1) | US20050242371A1 (zh) |
JP (1) | JP2007535813A (zh) |
KR (1) | KR20070004935A (zh) |
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CN102215039A (zh) * | 2010-04-07 | 2011-10-12 | 通用电气航空***有限公司 | 用于飞行器的功率开关 |
CN104716178A (zh) * | 2013-12-11 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | 具有深孔的ldmos器件及其制造方法 |
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JP5329118B2 (ja) | 2008-04-21 | 2013-10-30 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Dmosトランジスタ |
JP4587003B2 (ja) * | 2008-07-03 | 2010-11-24 | セイコーエプソン株式会社 | 半導体装置 |
US8608376B2 (en) * | 2010-05-26 | 2013-12-17 | Board Of Trustees Of The University Of Arkansas | Method for modeling and parameter extraction of LDMOS devices |
US20210408270A1 (en) * | 2020-06-24 | 2021-12-30 | Texas Instruments Incorporated | Silicide-block-ring body layout for non-integrated body ldmos and ldmos-based lateral igbt |
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JPS59210668A (ja) * | 1983-05-16 | 1984-11-29 | Fujitsu Ltd | 半導体装置 |
US4989058A (en) * | 1985-11-27 | 1991-01-29 | North American Philips Corp. | Fast switching lateral insulated gate transistors |
US6372586B1 (en) * | 1995-10-04 | 2002-04-16 | Texas Instruments Incorporated | Method for LDMOS transistor with thick copper interconnect |
US6593605B2 (en) * | 1998-06-01 | 2003-07-15 | Motorola, Inc. | Energy robust field effect transistor |
US6140184A (en) * | 1998-06-01 | 2000-10-31 | Motorola, Inc. | Method of changing the power dissipation across an array of transistors |
US6552406B1 (en) * | 2000-10-03 | 2003-04-22 | International Business Machines Corporation | SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks |
US6882023B2 (en) * | 2002-10-31 | 2005-04-19 | Motorola, Inc. | Floating resurf LDMOSFET and method of manufacturing same |
JP4225177B2 (ja) * | 2002-12-18 | 2009-02-18 | 株式会社デンソー | 半導体装置およびその製造方法 |
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2004
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2005
- 2005-04-06 KR KR1020067022733A patent/KR20070004935A/ko not_active Application Discontinuation
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CN102215039A (zh) * | 2010-04-07 | 2011-10-12 | 通用电气航空***有限公司 | 用于飞行器的功率开关 |
CN102215039B (zh) * | 2010-04-07 | 2015-09-23 | 通用电气航空***有限公司 | 用于飞行器的功率开关 |
US9246482B2 (en) | 2010-04-07 | 2016-01-26 | Ge Aviation Systems Limited | Power switches for aircraft |
CN104716178A (zh) * | 2013-12-11 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | 具有深孔的ldmos器件及其制造方法 |
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WO2005112134A2 (en) | 2005-11-24 |
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