CN1910757A - 具有改进沟槽结构的沟槽dmos晶体管 - Google Patents
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Abstract
提供一种沟槽DMOS晶体管单元,该沟槽DMOS晶体管单元包括第一导电性类型的衬底(104)和位于衬底上的体区(116),体区(116)具有第二导电性类型。至少一个沟槽(124)贯穿体区和衬底。绝缘层(150)内衬沟槽,导电电极(152)位于沟槽中覆盖绝缘层。第一导电性类型的源区(140)位于邻近沟槽的体区中。沟槽具有在衬底平面中限定多边形的侧壁,以便相邻的侧壁以大于90度的角度相互接触。
Description
相关申请的声明
本发明涉及1999年9月14日在美国专利商标局申请的美国申请序列号09/395,832、名称为“Trench DMOS Transistor Having ImprovedTrench Structure”的专利申请,该申请现在已被放弃。
技术领域
本发明一般涉及MOSFET晶体管,更一般涉及具有沟槽结构的DMOS晶体管。
背景技术
DMOS(双扩散MOS)晶体管是使用扩散形成晶体管区域的MOSFET(半导体上的金属场效应晶体管)的一种类型。DMOS晶体管一般用作功率晶体管,以提供用于功率集成电路应用的高压电路。当需要低的正向压降时,DMOS晶体管每一单位面积提供更高的电流。
一般的分立DMOS电路包括并行制造的两个或更多单个DMOS晶体管单元。单个DMOS晶体管单元共享公共漏极接触(衬底),而它们的源区全部与金属短接在一起,以及它们的栅极通过多晶硅短接在一起。因此,尽管分立DMOS电路由较小的晶体管矩阵构成,但是它们如同单个大的晶体管。对于分立DMOS电路,当通过栅极导通晶体管矩阵时,希望最大化每一单位面积的导电性。
DMOS晶体管的一种具体的类型是所谓的沟槽DMOS晶体管,其中垂直地形成沟道,以及在源区和漏区之间延伸的沟槽中形成栅极。该沟槽用薄氧化层内衬,并填充多晶硅,允许较小的阻塞电流,且由此提供更低的特定导通电阻值。美国专利号5,072,266、5,541,425和5,866,931中公开了沟槽DMOS晶体管的例子。
决定DMOS晶体管质量的一个重要性能是在多晶硅栅极和衬底之间产生的漏电流。不利地影响器件性能的这些电流部分地取决于内衬沟槽的栅氧化层的击穿电压。不幸地,由于沟槽的相邻侧壁一般以锐角会合,即,90度的角度,因此在多晶硅和衬底之间产生大的电场。这些电场又大大地减小栅氧化层的击穿电压,因此增加器件的漏电流。
由此,需要一种增加击穿电压的栅氧化层的沟槽DMOS晶体管。
发明内容
本发明提供一种沟槽DMOS晶体管单元,该沟槽DMOS晶体管单元包括第一导电性类型的衬底和位于衬底上的体区,体区具有第二导电性类型。至少一个沟槽贯穿体区和衬底。绝缘层内衬沟槽,导电电极位于沟槽中覆盖绝缘层。第一导电性类型的源区位于邻近沟槽的体区中。沟槽具有在衬底平面中限定多边形的侧壁,以便相邻的侧壁以大于90度的角度相互接触。
根据本发明的另一方面,由沟槽侧壁限定的多边形是六角形以及通过相邻侧壁形成的角度等于135度。
根据本发明的另一方面,沟槽在至少两个垂直平面中具有一般的矩形截面形状。DMOS晶体管单元还包括在与体区相对的衬底表面上布置的漏电极。
根据本发明的另一方面,绝缘层可以是氧化层,以及导电电极可以包括多晶硅。
根据本发明的又一方面,形成导电电极的多晶硅包括不掺杂的多晶硅层和掺杂的多晶硅层。
根据本发明的另一实施例,沟槽侧壁的圆润拐角具有约等于沟槽宽度的曲率半径。
附图说明
图1示出了常规DMOS晶体管的平面图。
图2示出了说明图1的常规晶体管中的单个单元的放大平面图。
图3示出了沿图2的线A-A′的图1-2所示的DMOS晶体管的示意性剖面图。
图4示出了根据本发明构成的DMOS晶体管单元的平面图。
图5是图4所示的DMOS晶体管的选择性实施例。
图6(a)-6(f)图示了形成图4-5的DMOS晶体管工序步骤的顺序。
图7示出了根据本发明构成的具有开放单元几何形状的DMOS晶体管结构的平面图。
图8示出了根据本发明构成的具有开放单元几何形状的DMOS晶体管结构的选择性实施例的平面图。
具体实施方式
图1-3图示了常规沟槽DMOS结构20的一个实施例,其中单个单元21的水平剖面形状是矩形。在该实施例中,该结构包括n+衬底100,其上生长轻n-掺杂的外延层104。在掺杂的外延层104内,提供相反导电性的体区116。覆盖大多数体区116的n-掺杂外延层140用作源区。在外延层中提供矩形沟槽124,外延层在结构的上表面被开口,并限定晶体管单元的周界。栅氧化层130内衬沟槽124的侧壁。沟槽124填有多晶硅,即多晶体硅。漏电极连接到半导体衬底100的背面,源电极连接到两个源区140和体区116,以及栅电极连接到填充沟槽124的多晶硅。如图1所示,在结构20的表面上连续地连接内衬沟槽124的多晶硅。此外,多晶硅接触129延伸超出结构20的表面,以用作互连。
如所示,图1中所示的MOSFET具有在垂直定向的沟槽中设置的栅极。该结构常常称作沟槽垂直DMOSFET。它是“垂直的”,因为在衬底的后面或下侧出现漏极接触,以及因为从源区到漏区的沟道电流流动是近似垂直的。这些最小化与弯曲或曲线的电流路径相关的较高电阻或与寄生场效应结构相关的较高电阻。该器件也是双扩散(由前缀“D”表示),因为在相反导电类型的部分先前-扩散的体区上源区扩散到外延材料中。该结构使用用于通过栅极控制电流的沟槽侧壁区,以及具有与其相关的基本上垂直的电流流动。如前面所述,该器件特别适于用作功率开关晶体管,其中穿过给定横向硅面积的载送电流被最大化。
应当指出对于基本晶体管工作,晶体管单元21不必具有矩形形状,而更普遍地可以具有任意多边形形状。但是,对于布局来说,规则的矩形形状和规则的六角形形状是最方便的。另外,除具有如图所绘的闭合-单元几何形状之外,晶体管单元可以具有开放或条纹几何形状。在先前提及的参考文献中示出了各种晶体管单元几何形状的例子。
如前面所述,内衬沟槽124的栅氧化层130的统一性是限定晶体管单元21质量的重要性能。不幸地,水平平面中的沟槽锐角135在填充沟槽的多晶硅和衬底之间产生大的电场。结果,在沟槽拐角135的附近中栅氧化层130的击穿电压大大地减小。
根据本发明,通过使沟槽的锐角钝化提高栅氧化层130的统一性。在图4的正方形单元中,通过用短内衬部分代替沟槽侧壁的90度拐角,有利地使拐角钝化,短内衬部分使两个连续的内衬部分成135度角度。例如,部分137a使部分137e和137f成135度角;部分137b使部分137g和137f成135度角;部分137c使部分137g和137h成135度角;以及部分137d使部分137h和137e成135度角。亦即,如图4所示,布置垂直延伸穿过衬底的沟槽侧壁,以便相邻侧壁不以垂直方式相互接触。相反,沟槽侧壁限定六角形形状。通过以此方式钝化沟槽拐角,减小拐角附近中的电场浓度,有利地增加器件的击穿电压。在本发明的某些实施例中,与图4所示相比,沟槽侧壁可以采用附加侧壁,以便相邻侧壁形成小于135度的角度,但是超过90度。
图5示出了本发明的选择性实施例,其中围绕晶体管的周边提供附加多晶硅沟槽140,互连图1描绘的接触129。该附加多晶硅沟槽有效地用作保护环,以减小由接触129的锐角另外产生的电场。以图4所示的方式通过使它们成六角形形状钝化多晶硅沟槽140的拐角。
如前面所述,晶体管单元21可以具有如图1-5所示的闭合-单元几何形状,另外,可以具有开放或条形几何形状。图7示出了具有开放几何形状的沟槽DMOS结构的平面图,其中根据本发明钝化沟槽224的锐角。图8示出了具有包括如图5所绘的沟槽保护环的开放单元几何形状的结构。
可以根据任意常规工艺技术制造图4-5所示的创造性DMOS器件。而且,下面论述在同一天申请的、名称为“Trench DMOS TransistorHaving Reduced Punch-Through”的共同待审专利申请中公开的一种示例性技术。但是,应当理解本发明的制造不局限于该技术,提出该技术仅作为例示。
图6(a)-6(f)示出了执行一系列示例性步骤以形成图4所绘的DMOS器件。在图6(a)中,在常规N+掺杂衬底100上生长N-掺杂的外延层104。对于30V器件,外延层104一般为5.5微米厚。接下来,在注入和扩散步骤中形成P体区116。由于注入的P体区均匀横穿衬底,因此不需要掩模。以40至60KeV,约5.5×1013/cm3的剂量将硼注入P体区。
在图6(b),通过用氧化层覆盖外延层104的表面形成掩模层,然后通常露出氧化层并构图,以留下掩模部分120。掩模部分120用来限定沟槽的位置。构图的掩模部分120限定图4所绘的钝沟槽侧壁。通过反应离子刻蚀穿过掩模开口干刻蚀沟槽124至一般为1.5至2.5微米范围的深度。
在图6(c)中,平滑每个沟槽的侧壁。首先,可以使用干化学刻蚀从沟槽侧壁除去薄氧化层(一般地约500-1000),以消除由反应离子刻蚀工艺引起的损坏。接着,在沟槽124和掩模部分120上生长牺牲二氧化硅层150。通过缓冲氧化刻蚀或HF刻蚀除去牺牲层150和掩模部分120,以便所得的沟槽侧壁尽可能的平滑。
如图6(d)所示,然后在整个结构上淀积栅氧化层130,以便它覆盖沟槽壁和p-体区116的表面。栅氧化层130一般具有500-800埃厚度。接下来,用多晶硅152,即多晶体硅,填充沟槽124。在淀积之前,一般用氯化磷掺杂多晶硅或注入砷或磷,以减小其电阻率,电阻率一般地在20Ω/m的范围内。在本发明的某些实施例中,可以以两个步骤工艺淀积多晶硅。在第一步骤中,淀积不掺杂的多晶硅层,以内衬沟槽的侧壁。在淀积不掺杂的多晶硅层之后淀积掺杂的多晶硅层。一般,掺杂多晶硅层的厚度大于不掺杂多晶硅层的厚度。例如,对于约8,000的总厚度,掺杂多晶硅层的厚度与不掺杂多晶硅层的厚度比可以是7∶1。不掺杂的多晶硅层有利地用作缓冲层,禁止掺杂材料渗透通过栅氧化层并进入p-体区,因此进一步减小穿通现象。
在图6(e)中,刻蚀多晶硅层152,以优化其厚度和露出在p体区116表面上延伸的部分栅氧化层130。接下来,使用光刻胶掩膜工艺形成构图的掩模层160。构图的掩模层160限定源区140。然后通过注入和扩散工艺形成源区140。例如,可以在80KeV下用砷注入源区至一般在8×1015至1.2×1016的浓度范围内。注入之后,砷扩散到大约0.5微米的深度。最后,用常规方法除去掩模层160,以形成图6(f)所绘的结构。
通过在结构上形成和构图BPSG层以限定与源和栅电极有关的BPSG区,以常规方法完成沟槽双扩散MOS晶体管。此外,在衬底的底表面上形成漏极接触层。最后,使用焊盘掩模限定焊盘接触。
尽管在此具体图示和描述了各种实施例,应当理解在不脱离本发明的精神和想要的范围条件下,对本发明的改进和改变都被上述教导所覆盖,且落在附加权利要求的范围内。例如,本发明的方法可以用来形成沟槽DMOS,其中各个半导体区的导电性与在此描述的相反。
Claims (26)
1.一种沟槽DMOS晶体管单元,包括:
第一导电类型的衬底;
衬底上的体区,所述体区具有第二导电类型;
贯穿体区和衬底的至少一个沟槽;
内衬沟槽的绝缘层;
覆盖绝缘层的沟槽中的导电电极;
邻近沟槽的体区中的第一导电性类型的源区;以及
其中所述沟槽具有在衬底平面中限定多边形的侧壁,以便相邻的侧壁以大于90度的角度相互接触。
2.根据权利要求1的DMOS晶体管单元,其中所述沟槽在至少两个垂直平面中具有一般矩形截面形状。
3.根据权利要求1的DMOS晶体管单元,还包括在与体区相对的衬底表面上布置的漏电极。
4.根据权利要求1的DMOS晶体管单元,其中所述绝缘层是氧化层。
5.根据权利要求1的DMOS晶体管单元,其中所述导电电极包括多晶硅。
6.根据权利要求5的DMOS晶体管单元,其中所述多晶硅包括掺杂材料。
7.根据权利要求5的DMOS晶体管单元,其中所述多晶硅包括不掺杂的多晶硅层和掺杂的多晶硅层。
8.根据权利要求1的DMOS晶体管单元,其中所述的多边形是六角形和所述的角度等于135度。
9.根据权利要求7的DMOS晶体管单元,其中所述的多边形是六角形和所述的角度等于135度。
10.一种沟槽DMOS晶体管结构,包括
在第一导电类型的衬底上形成多个单个沟槽DMOS晶体管单元,每个所述的单个沟槽DMOS晶体管单元包括:
衬底上的体区,所述体区具有第二导电类型;
贯穿体区和衬底的至少一个沟槽;
内衬沟槽的绝缘层;
覆盖绝缘层的沟槽中的导电电极;
邻近沟槽的体区中的第一导电性类型的源区;以及
其中所述沟槽具有在该衬底平面中限定多边形的侧壁,以便相邻的侧壁以大于90度的角度相互接触。
11.根据权利要求10的DMOS晶体管结构,其中所述沟槽在至少两个垂直平面中具有一般矩形截面形状。
12.根据权利要求10的DMOS晶体管结构,还包括在与体区相对的衬底表面上布置的漏电极。
13.根据权利要求10的DMOS晶体管结构,其中所述绝缘层是氧化层。
14.根据权利要求10的DMOS晶体管结构,其中所述导电电极包括多晶硅。
15.根据权利要求14的DMOS晶体管结构,其中所述多晶硅包括掺杂材料。
16.根据权利要求14的DMOS晶体管结构,其中所述多晶硅包括不掺杂的多晶硅层和掺杂的多晶硅层。
17.根据权利要求10的DMOS晶体管结构,其中至少一个所述的沟槽DMOS晶体管单元具有闭合的单元几何形状。
18.根据权利要求10的DMOS晶体管结构,其中至少一个所述的沟槽DMOS晶体管单元具有开放的单元几何形状。
19.根据权利要求10的DMOS晶体管结构,还包括分别连接到沿结构的周边设置的晶体管单元的多个多晶硅接触。
20.根据权利要求19的DMOS晶体管结构,还包括将所述多个多晶硅接触耦接在一起的多晶硅沟槽保护环。
21.根据权利要求17的DMOS晶体管结构,还包括分别连接到沿结构的周边设置的晶体管单元的多个多晶硅接触。
22.根据权利要求21的DMOS晶体管结构,还包括将所述多个多晶硅接触耦接在一起的多晶硅沟槽保护环。
23.根据权利要求18的DMOS晶体管结构,还包括分别连接到沿结构的周边设置的晶体管单元的多个多晶硅接触。
24.根据权利要求23的DMOS晶体管结构,还包括将所述多个多晶硅接触耦接在一起的多晶硅沟槽保护环。
25.根据权利要求10的DMOS晶体管结构,其中所述的多边形是六角形和所述的角度等于135度。
26.根据权利要求16的DMOS晶体管结构,其中所述的多边形是六角形和所述的角度等于135度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/094,932 US6781196B2 (en) | 2002-03-11 | 2002-03-11 | Trench DMOS transistor having improved trench structure |
US10/094,932 | 2002-03-11 |
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CN1910757A true CN1910757A (zh) | 2007-02-07 |
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CNA038058146A Pending CN1910757A (zh) | 2002-03-11 | 2003-03-11 | 具有改进沟槽结构的沟槽dmos晶体管 |
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US (1) | US6781196B2 (zh) |
EP (1) | EP1483791A4 (zh) |
JP (1) | JP2005520343A (zh) |
KR (1) | KR100949139B1 (zh) |
CN (1) | CN1910757A (zh) |
AU (1) | AU2003213832A1 (zh) |
TW (1) | TW200305286A (zh) |
WO (1) | WO2003079453A1 (zh) |
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CN102074478B (zh) * | 2009-11-24 | 2012-10-03 | 上海华虹Nec电子有限公司 | 一种沟槽式mos的制造工艺方法 |
CN112992682A (zh) * | 2019-12-13 | 2021-06-18 | 华润微电子(重庆)有限公司 | 沟槽型场效应晶体管结构及其制备方法 |
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JP4841829B2 (ja) * | 2004-11-17 | 2011-12-21 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
KR101095802B1 (ko) * | 2010-01-07 | 2011-12-21 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
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-
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- 2003-03-11 KR KR1020047014153A patent/KR100949139B1/ko not_active IP Right Cessation
- 2003-03-11 AU AU2003213832A patent/AU2003213832A1/en not_active Abandoned
- 2003-03-11 CN CNA038058146A patent/CN1910757A/zh active Pending
- 2003-03-11 WO PCT/US2003/007417 patent/WO2003079453A1/en active Application Filing
- 2003-03-11 JP JP2003577347A patent/JP2005520343A/ja active Pending
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Publication number | Priority date | Publication date | Assignee | Title |
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CN102074478B (zh) * | 2009-11-24 | 2012-10-03 | 上海华虹Nec电子有限公司 | 一种沟槽式mos的制造工艺方法 |
CN112992682A (zh) * | 2019-12-13 | 2021-06-18 | 华润微电子(重庆)有限公司 | 沟槽型场效应晶体管结构及其制备方法 |
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KR20040091709A (ko) | 2004-10-28 |
AU2003213832A1 (en) | 2003-09-29 |
US6781196B2 (en) | 2004-08-24 |
TW200305286A (en) | 2003-10-16 |
US20030168696A1 (en) | 2003-09-11 |
KR100949139B1 (ko) | 2010-03-25 |
WO2003079453A1 (en) | 2003-09-25 |
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EP1483791A4 (en) | 2009-11-11 |
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