CN1905371A - Voltage converting circuit - Google Patents
Voltage converting circuit Download PDFInfo
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- CN1905371A CN1905371A CN 200510085353 CN200510085353A CN1905371A CN 1905371 A CN1905371 A CN 1905371A CN 200510085353 CN200510085353 CN 200510085353 CN 200510085353 A CN200510085353 A CN 200510085353A CN 1905371 A CN1905371 A CN 1905371A
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Abstract
The invention provides a voltage converting circuit, converting an input signal with a first power supply as acting power supply and a reversed phase into an output signal with a second power supply as acting power supply, and comprising a voltage converting unit and a latching unit, where the voltage converting circuit receives two complementary input signals and converting their voltage reference; the latching unit is used to latch voltage reference of two output nodes in the state before low voltage supply is off, as the low voltage supply is off; on the condition that the low voltage is off, it can not creep but can determine output-end voltage reference and besides, has advantages of small circuit area and simple design.
Description
Technical field
The present invention relates to integrated circuit (integrated circuit), relate in particular to a kind of electric pressure converter (level shifter) circuit, when turning off (OFF) in LVPS, can be with the state of voltage level (voltage level) breech lock (latch) before LVPS is turned off of output node.
Background technology
Integrated circuit comprises the circuit of two runnings in different voltage levels or power domain (power domain) sometimes.For example; the voltage level VDDL (for example 3.3V) of the core of integrated circuit (core) part when running can be lower than the voltage level VDDH (for example 5V) of I/O (I/O) circuit usually; also therefore can use less transistor (transistor) to reduce power loss, thus the size of dwindling whole crystal grain (die).Therefore, integrated circuit often utilizes electric pressure converter to adjust the voltage level of input signal, and output signal can correctly be operated at another power supply localization circuit of higher or low voltage position standard.
Fig. 1 is the forming circuit figure of existing voltage conversion circuit.As shown in Figure 1, voltage conversion circuit 100 has the structure of input unit 11, voltage conversion unit 12 and output unit 13.The accurate VDDL in the first power source voltage position of supply input unit 11 is lower than the voltage level VDDH of the second source of supply voltage conversion unit 12 and output unit 13.Input unit 11 produces input signal IN and rp input signal XIN after receiving prime input signal INP.For reaching the power saving purpose, first power supply of low-voltage is turned off through regular meeting.After first power supply turned off, grid (gate) terminal voltage of n channel transistor 105,107 can be reduced under the critical voltage Vt, made n channel transistor 105,107 close and complementary output node 111, output node 112 suspension joints (float).The poorest situation is if the voltage of node 111,112 just is parked near the VDDH/2, will to cause electric leakage (the static current drain) phenomenon of the inverter 108,109 of output unit 13.This is because only a node (111 or 112) can only be pulled to VDDH against two p raceway groove gold oxygen half (PMOS) transistors 104,106, the leakage path that an other node lacks over the ground can be parked in VDDH/2, and then cause p raceway groove gold oxygen half (PMOS) transistor AND gate n raceway groove gold oxygen half (NMOS) transistor (not shown) conducting simultaneously in the inverter 108,109, make high-tension second source that leaky be arranged.In addition, because the voltage of output 110 is uncertain at this moment, might cause the mistake of back level.
Fig. 2 is the forming circuit figure of another existing voltage conversion circuit.As shown in Figure 2, electric pressure converter 200 also comprises input unit 11, voltage conversion unit 22 and output unit 13.Just voltage conversion unit 22 adds two p channel transistors 204,206 in the voltage conversion unit 12 of original Fig. 1, to increase the voltage decrease speed of node 111 or 112.As above-mentioned, when first power supply of low-voltage turn off after, the gate terminal voltage of n channel transistor 105,107 can be reduced under the critical voltage Vt, makes n channel transistor 105,107 close, 204,206 of p channel transistors are conducting state.Remaining situation is the same with Fig. 1, and node 111,112 also can suspension joint, if the voltage of node 111,112 just is parked near the VDDH/2, will cause the leaky of high-tension second source, and simultaneously, the voltage of output 110 is also uncertain.
Fig. 3 is again the forming circuit figure of an existing voltage conversion circuit.With reference to figure 3, american documentation literature the 6th, 600, propose for No. 358 a kind of when LVPS is turned off the voltage conversion circuit 300 of leakproof, utilize a low voltage detector (low voltage detector) 320 to detect the power supply of low-voltage.When first power supply of low-voltage is turned off,, can avoid the leaky that is produced because of the gate terminal suspension joint by input 101 and output 110 are isolated.Yet the output 110 of this voltage conversion circuit will be fixed on a kind of voltage quasi position after first power supply is turned off, and turns off preceding state but not maintain LVPS.In addition, the required transistor of low voltage detector 320 is a lot, and can become big along with the height voltage difference of two different electrical power localization, and needs the more multistage detection of doing low-voltage.In addition, the circuit layout of this voltage conversion circuit 300 (layout) area can be big more many than existing.
Fig. 4 is the forming circuit figure of another existing voltage conversion circuit.With reference to figure 4, american documentation literature the 6th, 819 proposes a kind of voltage conversion circuit 400 No. 159, form the speed that the voltage that utilizes transistor 405,407 to accelerate output 110 falls down by 405,407 in 430,440 and two transistors of two groups of electric pressure converters.When first power supply was turned off, if two groups of voltage transitions 430,440 are mated fully, transistor 405,407 can be treated as complementary output node 111, output node 112 leakage current path over the ground, can not cause other leaky.But, because of comprising the relation of two groups of electric pressure converters 430,440, the shared circuit area of voltage translator circuit 400 is bigger.The circuit layout of two groups of electric pressure converters 430,440 also need mate, and the circuit design difficulty is higher.
Similar above voltage conversion circuit, it is too numerous to enumerate to say so, yet no matter adopts which kind of design, and its purpose is exactly to adjust the voltage level of input signal exactly.Yet under the situation that LVPS is turned off, circuit is leakproof and can determine the voltage level of output still, simultaneously the coincident circuit area little with condition such as simplicity of design, be only the most practical voltage conversion circuit.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of electric pressure converter,, the voltage of output node can be latched in LVPS and turn off preceding voltage level even when LVPS is turned off.
For achieving the above object, voltage conversion circuit of the present invention will be converted to the output signal of second source as action power with an input signal and the rp input signal of first power supply as action power;
This voltage conversion circuit has a voltage conversion unit, produces output signal with second source as action power and after receiving described input signal and rp input signal, and voltage conversion unit has an output node and a complementary output node; One latch lock unit, with second source as action power, and be electrically connected to described output node, complementary output node and an earth terminal respectively, and when first power supply is turned off, the state before latch lock unit is latched in the voltage level of these two output nodes first power supply and turns off.
Described latch lock unit comprises:
One the one n channel transistor, its drain electrode are electrically connected to described complementary output node, grid is electrically connected to described output node and source ground;
One the 2nd n channel transistor, its drain electrode are electrically connected to described output node, grid is electrically connected to described complementary output node and source ground.
Described voltage conversion circuit also comprises: an input unit, as action power, this input unit receives a prime input signal with described first power supply, and produces described input signal and rp input signal.
Described input unit comprises:
One first inverter receives described prime input signal, and produces described rp input signal;
One second inverter is connected in series with described first inverter, and produces described input signal.
Described voltage conversion circuit also comprises: an output unit, as action power, this output unit receives the signal of described output node with described second source, and produces a described output signal and a reversed-phase output signal.
Described output unit comprises:
One the 3rd inverter receives the signal of described output node, and produces described reversed-phase output signal;
One the 4th inverter is connected in series with described the 3rd inverter, and produces described output signal.
Described voltage conversion unit comprises:
One the one p channel transistor, its source electrode is connected to described second source, and drain electrode is defined as described complementary output node, and grid is connected in described output node;
One the 2nd p channel transistor, its source electrode is connected to described second source, and drain electrode is defined as described output node, and grid is connected in described complementary output node;
One the 3rd n channel transistor, its grid receives described input signal, and drain electrode is electrically connected to described complementary output node, and source ground;
One the 4th n channel transistor, its grid receives described rp input signal, and drain electrode is electrically connected to described output node, and source ground.
Described voltage conversion unit comprises:
One the one p channel transistor, its source electrode is connected to described second source, and grid is connected in described output node;
One the 2nd p channel transistor, its source electrode is connected to described second source, and grid is connected in described complementary output node;
One the 3rd p channel transistor, its source electrode is connected to the drain electrode of a described p channel transistor, and drain electrode is defined as described complementary output node, and grid receives described input signal;
One the 4th p channel transistor, its source electrode is connected to the drain electrode of described the 2nd p channel transistor, and drain electrode is defined as described output node, and grid receives described rp input signal;
One the 3rd n channel transistor, its grid receives described input signal, and drain electrode is electrically connected to described complementary output node, and source ground;
One the 4th n channel transistor, its grid receives described rp input signal, and drain electrode is electrically connected to described output node, and source ground.
Compared to existing voltage conversion circuit circuit, the present invention only increases the leaky that two n channel transistors have just solved circuit when LVPS is turned off, and increasing under the minimum circuit area situation, just reaches purpose of power saving.Simultaneously, the output voltage of voltage conversion circuit maintains LVPS and turns off preceding state, makes the late-class circuit operate as normal.
Description of drawings
Fig. 1 is the forming circuit figure of an existing voltage conversion circuit;
Fig. 2 is the forming circuit figure of another existing voltage conversion circuit;
Fig. 3 is the forming circuit figure of an existing voltage conversion circuit again;
Fig. 4 is the forming circuit figure of another existing voltage conversion circuit;
Fig. 5 is the forming circuit figure of voltage conversion circuit of the present invention;
Fig. 6 is the voltage conversion circuit structural circuit figure of first embodiment of the invention;
Fig. 7 is the voltage conversion circuit structural circuit figure of second embodiment of the invention.
Embodiment
Fig. 5 is the forming circuit figure of voltage conversion circuit of the present invention.With reference to figure 5, voltage conversion circuit 500 of the present invention comprises voltage conversion unit 12 and latch lock unit 54.The main effect of voltage conversion unit 12 is that the amplitude voltage scope of two complementary input signals (being input signal IN and rp input signal XIN) is converted to the amplitude voltage scope 0-VDDH (output signal of VDDL＜VDDH) from 0-VDDL.Wherein, complementary input signal IN, XIN are supplied as the circuit of action power by first power supply with low-voltage VDDL.54 of voltage conversion unit 12 and latch lock units with than the high second source VDDH of first power source voltage as action power.The main effect of latch lock unit 54 is after first power supply of low-voltage is turned off (Poweroff), the state before the voltage of complementary output node 111 and output node 112 is latched in first power supply and turns off.
Voltage conversion unit 12 comprises one the one p channel transistor 104, one the 2nd p channel transistor 106, the first transistor device 505 and transistor seconds device 507.Latch lock unit 54 is electrically connected to output node 112, complementary output node 111 and earth terminal 113 (not shown)s.
The one p channel transistor 104 and the 2nd p channel transistor 106 are electrically connected to second source respectively.The first transistor device 505 receiving inputted signal IN, and be electrically connected to the drain electrode of a p channel transistor 104, the grid and the latch lock unit 54 of the 2nd p channel transistor 106 respectively.507 in transistor seconds device receives rp input signal XIN, and is electrically connected to the grid of a p channel transistor 104, the drain electrode and the latch lock unit 54 of the 2nd p channel transistor 106 respectively.
Fig. 6 is the structural circuit figure of the voltage conversion circuit of first embodiment of the invention.Voltage conversion circuit 600 with reference to figure 6, the first embodiment comprises input unit 11, voltage conversion unit 12, output unit 13 and latch lock unit 54.Input unit 11 be first power supply with low-voltage VDDL as action power, 54 of voltage conversion unit 12, output unit 13 and latch lock units with than the high second source VDDH of first power source voltage as action power.
The first transistor device and transistor seconds device utilize n channel transistor 105,107 to implement respectively in the present embodiment.Therefore, voltage conversion unit 12 has comprised one the one p channel transistor 104, one the 2nd p channel transistor 106, n channel transistor 105,107.54 of latch lock units comprise two n channel transistors 605,607, and the drain electrode of n channel transistor 605 is electrically connected to complementary output node 111, grid is electrically connected to output node 112 and source ground.The drain electrode of n channel transistor 607 is electrically connected to output node 112, grid is electrically connected to complementary output node 111 and source ground.
Under the situation of first power supply opening (ON), if being high logic level (logic high) VDDL, rp input signal XIN, input signal IN is low logic level (logic low) GND, then n channel transistor 105 conductings, the voltage of complementary output node 111 are pulled to low logic level GND.Then, 106 conductings of the 2nd p channel transistor, the voltage of output node 112 is pulled to high logic level VDDH, thereby causes 605 conductings of n channel transistor, has accelerated complementary output node 111 toward drop-down speed.On the other hand, if input signal IN is high logic level VDDL for low logic level GND, rp input signal XIN, then n channel transistor 107 conductings, the voltage of output node 112 is pulled to low logic level GND.Then, a p channel transistor 104 conductings, the voltage of complementary output node 111 is pulled to high logic level VDDH, thereby causes 607 conductings of n channel transistor, has accelerated output node 112 toward drop-down speed.Therefore, comprise the voltage conversion circuit 600 of latch lock unit 54, shortened complementary output node 111 and 112 past drop-down times (falling time) of output node, and then increase the highest frequency of operation of voltage conversion circuit 600.
Suppose to turn off (OFF) before at first power supply, complementary output node 111 is respectively low logic level and high logic level with output node 112.After for the power saving purpose first power supply being turned off, the gate terminal voltage of n channel transistor 105,107 can be reduced under the critical voltage Vt, makes n channel transistor 105,107 close.At this moment, n channel transistor 605 can conductings, with as complementary output node 111 leakage current path over the ground.Simultaneously, the 2nd also conducting of p channel transistor 106 is with the charging approach as 112 pairs of second sources of output node.Therefore, complementary output node 111 maintains low logic level and high logic level respectively with output node 112.
On the other hand, supposed before first power supply is turned off that complementary output node 111 is respectively high logic level and low logic level with output node 112.After first power supply was turned off, n channel transistor 607 can conductings, with as complementary output node 112 leakage current path over the ground.Simultaneously, an also conducting of p channel transistor 104 is with the charging approach as 111 pairs of second sources of output node.Therefore, complementary output node 111 maintains high logic level and low logic level respectively with output node 112.
So, because voltage conversion circuit 600 comprises latch lock unit 54, after first power supply is turned off, the voltage of complementary output node 111 and output node 112 can draw back fast to VDDH or GND, state before making the voltage of complementary output node 111 and output node 112 can maintain first power supply to turn off, even making late-class circuit still can normally work after first power supply is turned off, solve in the available circuit complementary output node 111 and output node 112 owing to suspension joint is parked in VDDH/2, and then caused the leaky of inverter 108,109.Simultaneously, voltage conversion circuit 600 reaches the power saving purpose that first power supply can be turned off increasing under the minimum circuit area situation.
Fig. 7 is the voltage conversion circuit structural circuit figure of second embodiment of the invention.Voltage conversion circuit 700 with reference to figure 7, the second embodiment comprises input unit 11, voltage conversion unit 22, output unit 13 and latch lock unit 54.The first transistor device in the voltage conversion unit 22 utilizes complementary transistor that n channel transistor 105 and p channel transistor 204 formed to implementing, and the transistor seconds device utilizes complementary transistor that n channel transistor 107 and p channel transistor 206 formed to implementing.Therefore, voltage conversion unit 22 comprises one the one p channel transistor 104, one the 2nd p channel transistor 106, n channel transistor 105,107 and p channel transistor 204,206.Complementary transistor is electrically connected to the grid of the 2nd p channel transistor 106 and the grid of n channel transistor 607 to 105,204 output by complementary output node 111.Complementary transistor is electrically connected to the grid of a p channel transistor 106 and the grid of n channel transistor 605 to 107,206 output by output node 112.
Compare with the voltage conversion circuit 600 of first embodiment, add the voltage conversion circuit 700 of p channel transistor 204,206, the effect of the voltage decrease speed of accelerating complementary output node 111 and output node 112 is arranged.Identical as for remaining circuit of second embodiment and first embodiment, repeat no more.
The foregoing description only is used to illustrate the present invention, and is not to be used to limit the present invention.
Claims (8)
1. a voltage conversion circuit will be converted to the output signal of second source as action power with an input signal and the rp input signal of first power supply as action power; It is characterized in that this voltage conversion circuit comprises:
One voltage conversion unit produces described output signal with described second source as action power and after receiving described input signal and rp input signal, and this voltage conversion unit has an output node and a complementary output node;
One latch lock unit as action power, and is electrically connected to described output node, complementary output node and an earth terminal respectively with described second source;
When wherein said latch lock unit is turned off at described first power supply, the state before being used for voltage level with described output node and complementary output node and being latched in described first power supply and turning off.
2. voltage conversion circuit as claimed in claim 1 is characterized in that, described latch lock unit comprises:
One the one n channel transistor, its drain electrode are electrically connected to described complementary output node, grid is electrically connected to described output node and source ground;
One the 2nd n channel transistor, its drain electrode are electrically connected to described output node, grid is electrically connected to described complementary output node and source ground.
3. voltage conversion circuit as claimed in claim 1, it is characterized in that described voltage conversion circuit also comprises: an input unit, with described first power supply as action power, this input unit receives a prime input signal, and produces described input signal and rp input signal.
4. voltage conversion circuit as claimed in claim 3 is characterized in that, described input unit comprises:
One first inverter receives described prime input signal, and produces described rp input signal;
One second inverter is connected in series with described first inverter, and produces described input signal.
5. voltage conversion circuit as claimed in claim 1, it is characterized in that described voltage conversion circuit also comprises: an output unit, with described second source as action power, this output unit receives the signal of described output node, and produces a described output signal and a reversed-phase output signal.
6. voltage conversion circuit as claimed in claim 5 is characterized in that, described output unit comprises:
One the 3rd inverter receives the signal of described output node, and produces described reversed-phase output signal;
One the 4th inverter is connected in series with described the 3rd inverter, and produces described output signal.
7. voltage conversion circuit as claimed in claim 1 is characterized in that, described voltage conversion unit comprises:
One the one p channel transistor, its source electrode is connected to described second source, and drain electrode is defined as described complementary output node, and grid is connected in described output node;
One the 2nd p channel transistor, its source electrode is connected to described second source, and drain electrode is defined as described output node, and grid is connected in described complementary output node;
One the 3rd n channel transistor, its grid receives described input signal, and drain electrode is electrically connected to described complementary output node, and source ground;
One the 4th n channel transistor, its grid receives described rp input signal, and drain electrode is electrically connected to described output node, and source ground.
8. voltage conversion circuit as claimed in claim 1 is characterized in that, described voltage conversion unit comprises:
One the one p channel transistor, its source electrode is connected to described second source, and grid is connected in described output node;
One the 2nd p channel transistor, its source electrode is connected to described second source, and grid is connected in described complementary output node;
One the 3rd p channel transistor, its source electrode is connected to the drain electrode of a described p channel transistor, and drain electrode is defined as described complementary output node, and grid receives described input signal;
One the 4th p channel transistor, its source electrode is connected to the drain electrode of described the 2nd p channel transistor, and drain electrode is defined as described output node, and grid receives described rp input signal;
One the 3rd n channel transistor, its grid receives described input signal, and drain electrode is electrically connected to described complementary output node, and source ground;
One the 4th n channel transistor, its grid receives described rp input signal, and drain electrode is electrically connected to described output node, and source ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100853537A CN100490325C (en) | 2005-07-26 | 2005-07-26 | Voltage converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100853537A CN100490325C (en) | 2005-07-26 | 2005-07-26 | Voltage converting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1905371A true CN1905371A (en) | 2007-01-31 |
| CN100490325C CN100490325C (en) | 2009-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100853537A Expired - Fee Related CN100490325C (en) | 2005-07-26 | 2005-07-26 | Voltage converting circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753122B (en) * | 2008-10-29 | 2011-12-07 | 盛群半导体股份有限公司 | Electric potential shifting circuit |
| CN102800295A (en) * | 2012-09-03 | 2012-11-28 | 旭曜科技股份有限公司 | Latchable voltage transforming system |
| CN105515560A (en) * | 2016-01-27 | 2016-04-20 | 灿芯半导体(上海)有限公司 | Voltage conversion circuit |
-
2005
- 2005-07-26 CN CNB2005100853537A patent/CN100490325C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753122B (en) * | 2008-10-29 | 2011-12-07 | 盛群半导体股份有限公司 | Electric potential shifting circuit |
| CN102800295A (en) * | 2012-09-03 | 2012-11-28 | 旭曜科技股份有限公司 | Latchable voltage transforming system |
| CN105515560A (en) * | 2016-01-27 | 2016-04-20 | 灿芯半导体(上海)有限公司 | Voltage conversion circuit |
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| Publication number | Publication date |
|---|---|
| CN100490325C (en) | 2009-05-20 |
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