CN1901007A

CN1901007A - Driving circuit on full p channel P-SITFT of integrated active OLED

Info

Publication number: CN1901007A
Application number: CNA2006100169655A
Authority: CN
Inventors: 司玉娟; 丁媛媛; 赵毅; 徐艳蕾; 徐小舟; 朱承基; 刘式墉
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2006-06-23
Filing date: 2006-06-23
Publication date: 2007-01-24

Abstract

The present invention relates to a kind of on-screen drive circuit structure for driving active OLED display screen to emit light, and the on-screen drive circuit structure consists of row driver, column driver and pixel drive circuit array, with all the circuit units being constituted with P-channel P-Si TFT's. The row driver generates the basic row signal R and row driving signal RD to on the switching TFT's in the OLED pixel drive circuit array one row by one row; the column driver generates the basic coloumn signal C and column driving signal CD to on all the transfer gates in corresponding BLOCK, so that the data signals Vdata1-VdataY from the data lines can pass through the transfer gates in the BLOCK for being fed to the corresponding data lines of the pixel drive circuit array to drive the active OLED display screen to emit light. The present invention has the features of low cost, less external leads, simple outer drive circuit, etc.

Description

Driving circuit on the full p raceway groove P-Si TFT screen of integrated-type active OLED

Technical field

The invention belongs to electroluminescence Driving technique field, specifically, relate to a kind of luminous integrated-type screen of active OLED display screen that drives and go up driving circuit structure, and this circuit structure is made by full P raceway groove P-Si TFT.

Background technology

OLED is a kind of emerging flat-panel display device, because its ultralight is thin, high brightness, wide viewing angle, autoluminescence, response speed are fast, high-resolution, low energy consumption, low temperature and anti-seismic performance excellence, low cost of manufacture, can make advantage such as flexible display screen, and it is had broad application prospects.

According to the different OLED display screens of type of drive can be divided into passive drive (Passive Matrix OLED, PMOLED) and active driving (Active Matrix OLED, AMOLED) two kinds.The pixel of PMOLED display screen does not have cell driving circuit, is by the formed matrix-scanning of the upper and lower electrode of OLED is finished display driver.In the passive drive mode, the working signal of OLED device is the very little pulse of dutycycle, along with increasing of number of pixels in the display screen, for making the OLED display screen reach enough brightness, need moment high electric current and voltage in the driving of passive matrix, produce a series of problems thus, as the average power consumption increase of the decline of device mission life, display screen, because this moment, luminescent device was operated in inefficient section; Voltage loss on causing simultaneously going between also increases etc.Passive matrix is difficult to realize high brightness and high resolving power, so PMOLED is confined to be lower than 4 inches display screen of 240 row.The OLED display screen of the monochromatic low information content of passive matrix (PM) has entered application at present.And in the AMOLED display screen, each pixel cell all has by memory capacitance and thin film transistor (TFT) (Thin Film Transistor, TFT) cell driving circuit of Zu Chenging.Even now can make the complex manufacturing technology of AMOLED display screen, cost of manufacture improves, but in active type of drive, light-emitting component is all in running order in the time of whole frame, can solve the problems referred to above that the passive OLED display screen is run into like this, make OLED be in low current (or low-voltage) work, display screen can obtain higher work efficiency and brightness, also helps improving the life-span of OLED display screen.

The driving circuit of AMOLED display screen mainly contains two kinds of solutions at present, and a kind of is to utilize amorphous silicon (a-Si:Amorphous silicon) TFT technology, and another is polysilicon (p-Si:ploy-crystalSilicon) TFT technology.A-Si TFT has that technology is simple, ripe, price is low, be easy to make than large tracts of land and TFT and prepare the yield rate advantages of higher.But a-Si TFT is because mobility is little, and the electric current that provides when the identity unit size is little, and has only the N channel device.And p-Si TFT is because its mobility height, response speed is fast, the view data write time is short, be easy to realize that large-area video shows, and p-Si TFT can adopt N raceway groove and two kinds of structures of P raceway groove, when the driving tube in the pixel-driving circuit is P raceway groove p-Si TFT, OLED can adopt the conventional structure device (hearth electrode bright dipping) of better performances to cooperate with it, and a-Si TFT has only the N channel device, when OLED adopts the conventional structure device, have problems, need to adopt performance to wait improved top electrode bright dipping type OLED.Use p-Si TFT the part peripheral drive circuit can be integrated on the substrate of display screen, significantly reduce external lead wire, reduce the complicacy of peripheral drive circuit.Therefore, adopt p-Si TFT to become a kind of trend of large scale AMOLED research and development at present in the world, also become one of the focus in current OLED field.

At present, be integrated in line driver, row driver and pixel-driving circuit on the display substrate, normally utilize complementary multi-crystal TFT technology to prepare.But the step of traditional complementary TFT of making is 2 times of making a-Si TFT, is 1.3 times of making P raceway groove P-Si TFT.The complicacy of complementary TFT manufacture craft causes decrease in yield.And the heat resistance of N channel TFT and stability all do not have the P channel TFT good.If driving circuit section on the whole screen all can be adopted P raceway groove P-Si TFT to make, will the manufacture craft of TFT greatly be simplified, cost also reduces and helps the raising of display screen yield rate.

Summary of the invention

The purpose of this invention is to provide driving circuit structure on a kind of screen that is used for integrated-type active OLED display screen, it can be integrated in the part peripheral drive circuit on the display substrate, and the manufacture craft of TFT is greatly simplified, reduce cost, improve yield rate, it can significantly reduce external lead wire, reduces the complicacy of peripheral drive circuit.

Display drive circuit of the present invention comprises line driver, row driver, pixel-driving circuit array, driving circuit all is that it is realized by following Method and circuits by P-Si (Poly-Silicon) TFT (the Thin Film Transistor) formation of full P raceway groove on the whole screen:

Line driver is made of line shift register and line buffer, and it can produce the horizontal-drive signal RD with specific waveforms, for pixel-driving circuit provides capable gating signal, opens the switching TFT pipe in the OLED pixel-driving circuit array line by line;

Each line shift register unit is made of 6 P raceway groove P-Si TFT, produces basic row signal R under the effect of basic clock signal CLKH1～CLKH6 and start signal VSTH; Wherein, CLKH1～CLKH6 is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/4 (dutycycle of Chu Xianing all is defined as the low level time of signal than the signal period herein), frequency is by resolution M * N * 3 of display screen and the refreshing frequency F decision of display screen, and size is

CLKH1, CLKH2, CLKH3, the low level pulse of CLKH4 postpones successively Time, CLKH5 shifts to an earlier date one-period than CLKH3 CLKH6 shifts to an earlier date one-period than CLKH4

VSTH is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle 1/M, frequency equates that with display screen refreshing frequency F when its low level in this frame time finished, clock signal clk H1 began the low level first time in this frame time; The basic row signal R that obtains through the line shift register unit is a kind of pulse signal, amplitude is-10V～+ 10V, dutycycle is 1/M, frequency is identical with the refreshing frequency F of display screen, low level and clock signal clk H1 the first time low level this frame time in of R1 in this frame time occurs simultaneously, low duration is identical with the low duration of clock signal clk H1, and the output of each grade shift register later on all postpones a low level time with respect to the output of previous stage.

The shift register cell of back delegation links to each other with the output terminal of the shift register cell of previous row, the shift register cell of every row is under the control of VSTH signal, two clock signals and a dc positive power signal VDDH, VSTH signal and output undersuing successively are shifted.

Each line shift register all is connected to line buffer, each line buffer constitutes by the phase inverter of four cascades, the input of first order phase inverter is the basic row signal R that line shift register produces, the output of first order phase inverter is as the input of second level phase inverter, the output of second level phase inverter is as the input of third level phase inverter, and the output of third level phase inverter is as the input of fourth stage phase inverter; Each grade inverter module constitutes by the P-Si TFT pipe of 4 P raceway grooves, works under the control of input signal and impressed voltage signal.

With described basic row signal R at different levels by behind the phase inverter of four cascades, generation has the horizontal-drive signal RD of specific waveforms, and RD also is a kind of pulse signal, and amplitude is-10V～+ 10V, frequency equates with the refreshing frequency F of display screen, with the waveform unanimity of basic row signal R.

Row driver is made of column shift register, column buffer and transmission gate.Each column shift register all is connected to column buffer, and each column shift register unit constitutes by 6 P raceway groove P-Si TFT, produces fundamental sequence signal C under the effect of basic clock signal CLKL1～CLKL6 and start signal VSTL; Wherein, CLKL1～CLKL6 is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/4, and frequency is by the number X decision of resolution M * N * 3, refreshing frequency F and the piecemeal of display screen, and size is

Wherein, N must be able to be divided exactly by X, and X is 4 multiple, and X and line number M are irrelevant.CLKL1, CLKL2, CLKL3, the low level pulse of CLKL4 postpones successively

Time, CLKL5 shifts to an earlier date one-period than CLKL3

CLKL6 shifts to an earlier date one-period than CLKL4

VSTL is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/X, frequency is by resolution M * N * 3 and the refreshing frequency F decision of display screen, size is FM, and when its low level in this line time finished, clock signal clk L1 began the low level first time in this line time; The fundamental sequence signal C that obtains through the column shift register unit is a kind of pulse signal, amplitude is-10V～+ 10V, frequency is by display screen refreshing frequency F and line number M decision, size is FM, its low level and clock signal clk L1 low level first time in this line time in this line time occurs simultaneously, low duration is identical with the low duration of clock signal clk L1, and the output of each grade shift register all postpones a low level time with respect to the output of previous stage.

The column shift register unit of the BLOCK in back links to each other with the output terminal of the column shift register unit of previous BLOCK, the column shift register unit of each BLOCK is under the control of VSTL signal, two clock signals and a dc positive power signal VDDL, VSTL signal and output undersuing successively are shifted.

Column buffer is made of the phase inverter of four cascades equally, the input of first order phase inverter is the fundamental sequence signal C that column shift register produces, the output of first order phase inverter is as the input of second level phase inverter, the output of second level phase inverter is as the input of third level phase inverter, and the output of third level phase inverter is as the input of fourth stage phase inverter; Each grade inverter module constitutes by the P-Si TFT pipe of 4 P raceway grooves, works under the control of input signal and impressed voltage signal.

Described fundamental sequence signal C at different levels by behind the phase inverter of four cascades, are generated the row drive signal CD with specific waveforms, and CD also is a kind of pulse signal, amplitude be-and 10V～+ 10V, frequency determines that by display screen refreshing frequency F and line number M size is FM.

The effect of impact damper is to improve the shift register output waveform, improves the driving force of circuit, forms horizontal-drive signal RD and row drive signal CD.

Each pixel-driving circuit constitutes by 2 P raceway groove P-Si TFT M1 and M2, memory capacitance C, luminescent device OLED, and wherein, RDQ is row gating signal (Q is an integer, and 1≤Q≤M, M represent the line number of display screen, and Q represents the Q of M in capable capable); DA _BBe that (X is a BLOCK number total in the column drive circuit to the data-signal that obtains through B transmission gate in A the BLOCK, i.e. block count; Y is the number of transmission gate in each BLOCK, and X * Y=3 * N, N are the columns of display screen; A is an integer, and 1≤A≤X represents X the A among the BLOCK; B is an integer, and 1≤B≤Y represents B transmission gate among each BLOCK).

When line scan signals RDQ is low level, the switching tube M1 conducting in this row in all pixel-driving circuits.At this moment, externally under the programmed control, produce the CDA signal, under the control of CDA signal, all Y transmission gate among A BLOCK is opened simultaneously.External data signal Vdata B will output on the data line of pixel-driving circuit, i.e. data-signal DA by B transmission gate among this BLOCK _BThereby, with horizontal-drive signal RDQ, drive that Q is capable, the OLED work in the pixel-driving circuit of the [Y * (A-1)+B] row.

Data-signal DA _BGive memory capacitance C charging by switching tube M1, driving OLED is luminous simultaneously; When RDQ became high level, the switching tube M1 in all pixel-driving circuits of corresponding row closed, but because capacitor C does not have discharge path, it is luminous therefore to continue to keep OLED, up to capable gating signal arrival next time.

This patent circuit is characterised in that: described circuit structure is integrated on the substrate of display screen, is made of full P raceway groove P-Si TFT, can effectively reduce peripheral leads, reduce the complicacy of peripheral drive circuit, simplify the manufacture craft of TFT, reduce cost, improve yield rate.

Be appreciated that above-mentioned about general introduction of the present invention and following detailed be to be used for for example and explanation, and attempt to provide further explanation for invention that claim is protected.

Description of drawings

Fig. 1: driving circuit one-piece construction synoptic diagram on the active OLED display screen;

Driving circuit schematic diagram on the active OLED display screen of Fig. 2: embodiment 1 correspondence;

The line driver schematic diagram of Fig. 3: embodiment 1 correspondence;

The row driver schematic diagram of Fig. 4: embodiment 1 correspondence;

The shift register schematic diagram of Fig. 5: embodiment 1 correspondence;

Fig. 6 (a): the line shift register clock signal of embodiment 1 correspondence and signal output waveform figure;

Fig. 6 (b): the column shift register clock signal of embodiment 1 correspondence and signal output waveform figure;

Fig. 7 (a): the impact damper of embodiment 1 correspondence (4 grades of phase inverters) schematic diagram;

Fig. 7 (b): the pulse voltage source VDDH1/VDDL1 oscillogram of embodiment 1 correspondence;

The pixel-driving circuit schematic diagram of Fig. 8: embodiment 1 correspondence.

Embodiment

Embodiment 1:

Y=24 in this embodiment corresponding diagram 1, X=40, M=240, N=320, thereby X * Y=N * 3=960.

Active OLED display screen with resolution QVGA (240 * 320 * 3), refreshing frequency 60Hz is an example, and the principle of work of driving circuit on the active OLED display screen is described.

Based on the above-mentioned example of this invention, the driving circuit schematic diagram mainly comprises three parts as shown in Figure 2 on the active OLED display screen: line driver, row driver, pixel-driving circuit array.

The external timing signal generator produces the VSTH signal shown in Fig. 6 (a), and this signal is a pulse signal, and amplitude is-10V～+ 10V, frequency is 60Hz, dutycycle is 1/240; The external timing signal generator produces the basic row clock signal clk H1～CLKH6 shown in Fig. 6 (a), and they are pulse signal, and amplitude is-10V～+ 10V, frequency is 3.6KHz, dutycycle is 1/4.Wherein, CLKH1, CLKH2, CLKH3, the low level pulse of CLKH4 postpone 1/4 cycle successively, i.e. 69.44 μ s, CLKH5 shifts to an earlier date one-period (277.76 μ s) than CLKH3, and CLKH6 shifts to an earlier date one-period (277.76 μ s) than CLKH4.Line shift register is under the control of above-mentioned start signal VSTH and clock signal clk H1～CLKH6, generate basic row signal (R1, the R2 of each row successively ... R240), they be amplitude be-10V～+ 10V, frequency are that 60Hz, dutycycle are 1/240 pulse signal, waveform is shown in Fig. 6 (a).These basic row signals are respectively by corresponding with it level Four phase inverter F1～F4, generation have specific waveforms horizontal-drive signal (RD1, RD2 ... RD240), they be amplitude be-10V～+ 10V, frequency are that 60Hz, dutycycle are 1/240 pulse signal, the basic row signal is through behind the buffer circuit, waveform improves, and has improved driving force.Horizontal-drive signal RD1～RD240 respectively with the 1st the row～the 240 the row all pixel-driving circuits in line scan signals link to each other, for the switch transistor T FT in the pixel-driving circuit provides start signal.

After line driver gating delegation pixel, row driver is started working.The method that row driver takes piecemeal (BLOCK) to handle, data line is divided into 40 BLOCK (BLOCK1～BLOCK40, X=40 in the corresponding diagram 1,1≤A≤40 in the corresponding technical scheme), each BLOCK is that 24 sub-pixels transmit data simultaneously, and shared 24 data lines of each BLOCK (Vdata1～Vdata24).The external timing signal generator produces the VSTL signal shown in Fig. 6 (b), and this signal is a pulse signal, and amplitude is-10V～+ 10V, frequency is 14.4KHz, dutycycle is 1/40; The external timing signal generator produces the fundamental sequence clock signal clk L1～CLKL6 shown in Fig. 6 (b), and they are pulse signal, and amplitude is-10V～+ 10V, frequency is 144KHz, dutycycle is 1/4.Wherein, CLKL1, CLKL2, CLKL3, the low level pulse of CLKL4 postpone 1/4 cycle successively, i.e. 1.736 μ s, CLKL5 shifts to an earlier date one-period (6.944 μ s) than CLKL3, and CLKL6 shifts to an earlier date one-period (6.944 μ s) than CLKL4.Column shift register is under the control of above-mentioned start signal VSTL and clock signal clk L1～CLKL6, generate fundamental sequence signal C1～C40 of each BLOCK successively, they be have amplitude for-10V～+ pulse signal of 10V, dutycycle is 1/40, frequency is 14.4KHz, these fundamental sequence signals are respectively by corresponding with it level Four phase inverter F1～F4, generation has the row drive signal CD1～CD40 of specific waveforms, same C1～the C40 of waveform, shown in Fig. 6 (b), it be amplitude be-10V～10V, frequency are that 14.4KHz, dutycycle are 1/40 pulse signal.

CD1～CD40 links to each other with the control end of 24 transmission gates among BLOCK1～BLOCK40 respectively, when being low level corresponding to the CD signal in A the BLOCK, 24 transmission gates among this BLOCK are all opened simultaneously, data-signal VdataB (1≤B≤24) from external data memory passes through corresponding transmission gate, the data-signal DA on the data line of this row, this BLOCK respective pixel driving circuit _B[24 * (A-1)+B] row that drive this active OLED display screen with this horizontal-drive signal are luminous according to the data voltage of being given.

Whole 24 transmission gates by this BLOCK as 24 external data line Vdata1～Vdata24, the data-signal DA on the data line of pixel-driving circuit ₁～DA ₂₄Just drive [24 * (A-1)+1～24 * (A-1)+24] row pixel cell work of this row with this horizontal-drive signal.

Among Fig. 2, VDD is the DC voltage of 18V; GND is 0 current potential; VSSL is-DC voltage of 10V, and VDDL is the DC voltage of 10V; VDDL1 is a pulse voltage, and waveform is shown in Fig. 7 (b); VSSH is-DC voltage of 10V; VDDH is the DC voltage of 10V; VDDH1 is a pulse voltage, and waveform is shown in Fig. 7 (b).

Fig. 3 is the line driver schematic diagram among the present invention, and it is made of 240 bit shift register and 240 groups of impact dampers that D1～D240 forms, and the impact damper of each group all is made up of level Four phase inverter F1～F4.Line driver produces the horizontal-drive signal RD1～RD240 with specific waveforms under the control of start signal VSTH, clock signal clk H1～CLKH6 and voltage signal, the same R1～R240 of waveform is shown in Fig. 6 (a).Every grade of shift register D1, D2, D3 ... the output of D240 is passed through respectively after 4 grades of corresponding phase inverter F1～F4, guarantees the polarity of original signal, but has increased the driving force of circuit.Waveform correlation figure is shown in Fig. 6 (a).Between the adjacent lines drive signal, the horizontal-drive signal in back always postpones a low level time (69.44 μ s) than previous horizontal-drive signal, relevant voltage is described below among Fig. 3: VSSH is-the 10V DC voltage, VDDH is the 10V DC voltage, GND is 0 current potential, and VDDH1 is pulse voltage (shown in Fig. 7 (b)).

Fig. 4 is a row driver schematic diagram among the present invention, and 960 transmission gates that the impact damper that 40 bit shift register that it is made up of D1～D40,40 groups of level Four phase inverter F1～F4 form, 40 groups of T1～T24 form constitute.Row driver is divided into 40 pieces with data-signal, transmits data for OLED pixel-driving circuit array in mode parallel in the piece, the interblock serial, effectively reduces peripheral leads, and it is luminous to drive the active OLED display screen.Concrete step is: after certain row pixel is by gating, row driver is started working, row driver is under the control of start signal VSTL, clock signal clk L1～CLKL6 and voltage signal, generation has the row drive signal CD1～CD40 of specific waveforms, 24 transmission gates that control signal CD1～CD40 is respectively among BLOCK1～BLOCK40 provide the unlatching control signal, and 24 data Vdata1～Vdata24 are simultaneously through the DA of the parallel corresponding pixel-driving circuit that is sent to the OLED display screen of 24 transmission gates of same BLOCK inside ₁～DA ₂₄, on (A is 1～40 integer, represents among 40 BLOCK), shared these 24 data lines of each BLOCK, thus reduced the number of peripheral leads, improved integrated level.Selected when logical when next line, row driver repeats said process, and to the last delegation's gating is finished the transmission and the demonstration of frame data.Relevant voltage is described below among Fig. 4: VSSL is the DC voltage of-10V, and VDDL is the DC voltage of 10V, and GND is 0 current potential, and VDDL1 is pulse voltage (shown in Fig. 7 (b)).

Fig. 5 is the shift-register circuit schematic diagram that relates among the present invention, and it is to constitute one of the line driver among the present invention, Key Circuit of row driver.As shown in Figure 5, each shift register cell is made of 6 P raceway groove P-Si TFT.This structure is subjected to input signal VSTH/VSTL (the shift register use VSTH of line driver as shown in Figure 6, the shift register VSTL of row driver) and the control of 6 clock signals (shift register of line driver uses CLKH1～CLKH6, the shift register CLKL1 of row driver～CLKL6).First order shift unit (D1) with the shift register in the line driver is an example, concrete principle of work and process are described: when the VSTH signal becomes low level, CLKH1 and CLKH3 and is high level, P1 manages conducting, the Q point is recharged, cause the conducting of P5 pipe, the grid source electric capacity of P5 pipe begins charging.Simultaneously P4 manages also conducting, moves the current potential that Qb order to high level, causes P2, P6 pipe to end, this moment CLKH1 signal or high level, it is high level that the first order is exported R1.When the VSTH signal becomes high level, CLKH3 is a high level, when CLKH1 becomes low level, the P1 pipe ends, but because the existence of grid source electric capacity makes the P5 pipe continue to maintain conducting state, this moment, the CLKH1 signal was a low level, made that first order output R1 is a low level.Next clock period VSTH and CLKH3 still are high level, and this moment, the P5 pipe continued to keep conducting, and CLKH1 also becomes high level, and R1 is a high level.P5 pipe is kept always and is conducting to the CLKH3 signal and becomes low level, P3 pipe conducting this moment, the Qb point is recharged, P2 pipe and the also conducting thereupon of P6 pipe, and the P5 pipe ends, make first order output R1 keep high level, after this, before new pumping signal VSTH not occurring, the P5 pipe will always work in cut-off state, output terminal is held high level by the P6 pipe with VDDHVDDL, until new pumping signal VSTH arrives.Back one-level shift unit is output as pumping signal with the previous stage shift unit, and principle of work is identical.

Shift register output signal R1, R2 ... the waveform of R240 is shown in Fig. 6 (a).It is worthy of note the 5th, 6 shift unit here.Produce CLKH5 by the external timing signal generator, be added on the 5th shift unit.When CLKH5 low level occurred for the first time, pumping signal did not also arrive, and had guaranteed that level V output keeps high level, till fourth stage output drive signal arrives.Produce CLKH6 by the external timing signal generator, be added on the 6th shift unit, principle is identical with Unit the 5th.

Fig. 6 is added clock signal of the shift register among the present invention and signal output waveform figure.For shift register shown in Figure 5, except preceding four shift units, with 4 shift units is one group, and added clock signal is followed successively by CLKH5/1 (CLKL5/1), CLKH6/2 (CLKL6/2), CLKH1/3 (CLKL1/3), CLKH2/4 (CLKL2/4), repeats with this.

Fig. 7 (a) is the buffer circuits schematic diagram that relates among the present invention, and it is to constitute the line driver among the present invention, the significant element of row driver, is made of 4 phase inverters.

Each inverter module of line buffer is controlled by 2 power supply signal VDDH/VDDH1, VSSH and 1 input signal, and first order phase inverter is applied the first power supply signal VDDH1 and the second dc negative supply signal VSSH; Apply the second dc negative supply signal VSSH and the 3rd dc positive power signal VDDH to second to fourth stage phase inverter.

Each inverter module of column buffer is controlled by 2 power supply signal VDDL/VDDL1, VSSL and 1 input signal, and first order phase inverter is applied the first power supply signal VDDL1 and the second dc negative supply signal VSSL; Apply the second dc negative supply signal VSSL and the 3rd dc positive power signal VDDL to second to fourth stage phase inverter.

The output of 4 grades of phase inverters and input homophase, but can improve output waveform, improve driving force.The input of first order phase inverter is the basic row signal R1～R240 of line shift register generation or fundamental sequence signal C1～C40 that column shift register produces, the output of first order phase inverter is as the input of second level phase inverter, the output of second level phase inverter is as the input of third level phase inverter, and the output of third level phase inverter is as the input of fourth stage phase inverter.Each grade inverter module is made of the P-Si TFT pipe of 4 P raceway grooves.

Under the control of input signal and 3 impressed voltage signals, work.Wherein, VSSH/VSSL is a 10V d. c. voltage signal, and VDDH/VDDL is+the 10V d. c. voltage signal that VDDH1/VDDL1 is pulse voltage (waveform is shown in Fig. 7 (b)).

First order inverter module with first group of impact damper in the line driver is an example, and the principle of work of phase inverter is described, as input R1 when being low level, T1 manages conducting, and the T2 pipe ends.The drain-source of T4 pipe links together, and is equivalent to an electric capacity.The charging in the conducting of T1 pipe of T4 pipe, voltage is the output voltage of this moment.At this moment the electric current by the T1 pipe only is the leakage current of T2 pipe, and very little leakage current is by the T1 of high conducting, and the output voltage OUT1 ten minutes that makes phase inverter is near VDDH1.When being input as high level, the T1 pipe ends, because the capacity effect of T4 pipe, T2 tube grid voltage will be lower than VSSH this moment, and VSSH is-the 10V DC voltage that this will make T2 manage complete conducting, make output very near VSSH.This impact damper is made of 4 grades of phase inverters, applies the first power supply signal VDDH1/VDDL1 shown in Fig. 7 (b) to first order inverter module, and amplitude is shown in Fig. 7 (b), and initial voltage value is that 18V continues 1us, keeps 12V constant then.Purpose is to be under the situation of high level at initial input, makes the conducting fully of T1 pipe when low level arrives, and reaches good anti-phase effect.Apply the second dc power signal VDDH/VDDL to other phase inverters at different levels, VDDH/VDDL is the DC voltage of 10V.

As shown in Figure 8, each pixel-driving circuit constitutes by 2 P raceway groove P-Si TFT, 1 memory capacitance C, 1 luminescent device OLED.Wherein, RDQ is a row gating signal (Q is an integer, 1≤Q≤240); DA _BIt is the data-signal that obtains through (1≤B≤24) transmission gate of the B in the individual BLOCK of A (1≤A≤40).With first pixel among first first BLOCK of row is the example explanation: when line scan signals RD1 is low level, and the switching tube M1 conducting in first all pixel-driving circuits of row, under the control of CD1,24 transmission gates among first BLOCK are opened simultaneously.Data D1 ₁Output on the data line of pixel-driving circuit this data-signal D1 by the transmission gate T1 among first BLOCK ₁Give memory capacitance C charging by switching tube M1, driving OLED is luminous simultaneously; When RD1 became high level, the switching tube M1 in first all pixel-driving circuits of going closed, but because capacitor C does not have discharge path, it is luminous therefore to continue to keep OLED, up to capable gating signal arrival next time.

The present invention is not limited to above-mentioned certain embodiments, the present invention should understand like this, under the prerequisite of the spirit and scope of the invention that claim limits under not breaking away from, those skilled in the art it is contemplated that out many other replacement, modifications and changes, and it all should comprise within the scope of the present invention.

Claims

1, a kind of integrated-type active OLED screen is gone up driving circuit, is made of line driver, row driver, pixel-driving circuit array, it is characterized in that:

(1) driving circuit all is that P-Si TFT by full P raceway groove constitutes on the whole screen;

(2) the line driver horizontal-drive signal RD that produces basic row signal R and have specific waveforms uses the horizontal-drive signal RD with specific waveforms that is produced to open switching TFT pipe in the OLED pixel-driving circuit array line by line;

(3) row driver produces fundamental sequence signal C and the row drive signal CD with specific waveforms, open all transmission gates among the corresponding BLOCK with the row drive signal CD that is produced with specific waveforms, data-signal Vdata1～VdataY of coming from data line is sent on the corresponding data line in the pixel-driving circuit array by the transmission gate among this BLOCK, and then it is luminous to drive the active OLED display screen.

2, integrated-type active OLED screen as claimed in claim 1 is gone up driving circuit, and it is characterized in that: line driver is made of line shift register and line buffer.

3, integrated-type active OLED screen as claimed in claim 2 is gone up driving circuit, it is characterized in that:

(1) each line shift register unit is made of 6 P raceway groove P-Si TFT, produces basic row signal R under the effect of basic clock signal CLKH1～CLKH6 and start signal VSTH; CLKH1～CLKH6 is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/4, and frequency is by resolution M * N * 3, the refreshing frequency F Hz decision of display screen, and size is

(2) low level pulse of CLKH1, CLKH2, CLKH3, CLKH4 postpones successively

CLKH5 shifts to an earlier date one-period than CLKH3

CLKH6 shifts to an earlier date one-period than CLKH4

VSTH is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/M, frequency equates that with display screen refreshing frequency F when its low level in this frame time finished, clock signal clk H1 began the low level first time in this frame time;

(3) the basic row signal R that obtains through the line shift register unit is a kind of pulse signal, amplitude is-10V～+ 10V, dutycycle is 1/M, frequency is identical with the refreshing frequency F of display screen, the low level of R1 and the clock signal clk H1 low level first time in this frame time occurs simultaneously, low duration is identical with the low duration of clock signal clk H1, and the output of each grade shift register all postpones a low level time with respect to the output of previous stage.

(4) each line buffer is made of the phase inverter of four cascades, the input of first order phase inverter is the basic row signal R that line shift register produces, the output of first order phase inverter is as the input of second level phase inverter, the output of second level phase inverter is as the input of third level phase inverter, and the output of third level phase inverter is as the input of fourth stage phase inverter;

(5) with described basic row signal R at different levels by behind the phase inverter of four cascades, generation has the horizontal-drive signal RD of specific waveforms, and RD also is a kind of pulse signal, and amplitude is-10V～+ 10V, frequency equates with the refreshing frequency F of display screen, with the waveform unanimity of basic row signal R.

4, integrated-type active OLED screen as claimed in claim 3 is gone up driving circuit, it is characterized in that: each of line buffer grade inverter module constitutes by the P-Si TFT pipe of 4 P raceway grooves, works under the control of input signal and 2 impressed voltage signals; First order phase inverter is applied the first power supply signal VDDH1 and the second dc negative supply signal VSSH, apply the second dc negative supply signal VSSH and the 3rd dc positive power signal VDDH to fourth stage phase inverter to second; VSSH is-the 10V d. c. voltage signal; VDDH is+the 10V d. c. voltage signal; The VDDH1 initial voltage value is 18V, continues to keep 12V constant behind the 1us.

5, integrated-type active OLED screen as claimed in claim 1 is gone up driving circuit, and it is characterized in that: row driver is made of column shift register, column buffer and transmission gate, and each column shift register all is connected to column buffer.

6, integrated-type active OLED screen as claimed in claim 5 is gone up driving circuit, it is characterized in that:

(1) each column shift register unit constitutes by 6 P raceway groove P-Si TFT, produces fundamental sequence signal C under the effect of basic clock signal CLKL1～CLKL6 and start signal VSTL; Wherein, CLKL1～CLKL6 is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/4, and frequency is by the number X decision of resolution M * N * 3, refreshing frequency F and the piecemeal of display screen, and size is

Wherein, N must be able to be divided exactly by X, and X is 4 multiple;

(2) low level pulse of CLKL1, CLKL2, CLKL3, CLKL4 postpones successively

Time, CLKL5 shifts to an earlier date one-period than CLKL3

CLKL6 shifts to an earlier date one-period than CLKL4 VSTL is a kind of pulse signal, amplitude is-and 10V～+ 10V, dutycycle is 1/X, frequency is by resolution M * N * 3 and the refreshing frequency F decision of display screen, size is FM, and when its low level in this line time finished, clock signal clk L1 began the low level first time in this line time;

(3) the fundamental sequence signal C that obtains through the column shift register unit is a kind of pulse signal, amplitude is-10V～+ 10V, frequency is by display screen refreshing frequency F and line number M decision, size is FM, the low level of C1 and the clock signal clk L1 low level first time in this line time occurs simultaneously, low duration is identical with the low duration of clock signal clk L1, and the output of each grade shift register all postpones a low level time with respect to the output of previous stage;

(4) column buffer is made of the phase inverter of four cascades equally, the input of first order phase inverter is the fundamental sequence signal C that column shift register produces, the output of first order phase inverter is as the input of second level phase inverter, the output of second level phase inverter is as the input of third level phase inverter, and the output of third level phase inverter is as the input of fourth stage phase inverter;

(5) with described fundamental sequence signal C at different levels by behind the phase inverter of four cascades, generation has the row drive signal CD of specific waveforms, and CD also is a kind of pulse signal, amplitude be a 10V～+ 10V, frequency is by display screen refreshing frequency F and line number M decision, and size is FM.

7, integrated-type active OLED screen as claimed in claim 6 is gone up driving circuit, it is characterized in that: each of column buffer grade inverter module constitutes by the P-Si TFT pipe of 4 P raceway grooves, works under the control of input signal and 2 impressed voltage signals; First order phase inverter is applied the first power supply signal VDDL1 and the second dc negative supply signal VSSL, apply the second dc negative supply signal VSSL and the 3rd dc positive power signal VDDL to fourth stage phase inverter to second; VSSL is-the 10V d. c. voltage signal; The VDDL+10V d. c. voltage signal; The VDDL1 initial voltage value is 18V, continues to keep 12V constant behind the 1us.

8, integrated-type active OLED screen as claimed in claim 1 is gone up driving circuit, it is characterized in that: each pixel-driving circuit constitutes by 2 P raceway groove P-Si TFT, memory capacitance C, luminescent device OLED; When line scan signals RDQ is low level, switching tube M1 conducting in this row in all pixel-driving circuits, under the control of CDA signal, Y transmission gate among A BLOCK opened simultaneously, external data signal Vdata B is by B the transmission gate of A BLOCK, output on the data line of pixel-driving circuit, i.e. data-signal DA _BThereby, with horizontal-drive signal RDQ, drive that Q is capable, the OLED work in the pixel-driving circuit of the [Y * (A-1)+B] row.

9, integrated-type active OLED screen as claimed in claim 3 is gone up driving circuit, it is characterized in that: the shift register cell of back delegation links to each other with the output terminal of the shift register cell of previous row, the shift register of every row is under the control of VSTH signal, two clock signals and a dc positive power signal VDDH, VSTH signal and output undersuing successively are shifted; Except preceding four shift units, be one group with 4 shift units, added clock signal is followed successively by CLKH5/1, CLKH6/2, CLKH1/3, CLKH2/4, repeats with this.

10, integrated-type active OLED screen as claimed in claim 6 is gone up driving circuit, it is characterized in that: the column shift register unit of a back BLOCK links to each other with the output terminal of the column shift register unit of previous BLOCK, the column shift register of each BLOCK is under the control of VSTL signal, two clock signals and a dc positive power signal VDDL, VSTL signal and output undersuing successively are shifted; Except preceding four shift units, be one group with 4 shift units, added clock signal is followed successively by CLKL5/1, CLKL6/2, CLKL1/3, CLKL2/4, repeats with this.