CN1894775A - 在MOSFET结构中形成应变Si-沟道的方法 - Google Patents
在MOSFET结构中形成应变Si-沟道的方法 Download PDFInfo
- Publication number
- CN1894775A CN1894775A CNA2004800373764A CN200480037376A CN1894775A CN 1894775 A CN1894775 A CN 1894775A CN A2004800373764 A CNA2004800373764 A CN A2004800373764A CN 200480037376 A CN200480037376 A CN 200480037376A CN 1894775 A CN1894775 A CN 1894775A
- Authority
- CN
- China
- Prior art keywords
- layer
- strain
- substrate
- amorphous
- sige
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 62
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 16
- 239000012212 insulator Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims abstract 69
- 239000002344 surface layer Substances 0.000 claims abstract 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract 2
- 238000000407 epitaxy Methods 0.000 claims description 18
- 238000002425 crystallisation Methods 0.000 claims description 15
- 230000008025 crystallization Effects 0.000 claims description 15
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 8
- 238000003475 lamination Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 101100379079 Emericella variicolor andA gene Proteins 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03104732.7 | 2003-12-16 | ||
EP03104732 | 2003-12-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1894775A true CN1894775A (zh) | 2007-01-10 |
CN100459042C CN100459042C (zh) | 2009-02-04 |
Family
ID=34684601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800373764A Active CN100459042C (zh) | 2003-12-16 | 2004-11-30 | 在MOSFET结构中形成应变Si-沟道的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7416957B2 (zh) |
EP (1) | EP1697976A1 (zh) |
JP (1) | JP2007515790A (zh) |
KR (1) | KR20060123334A (zh) |
CN (1) | CN100459042C (zh) |
WO (1) | WO2005059979A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101924138A (zh) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微***与信息技术研究所 | 防止浮体及自加热效应的mos器件结构及其制备方法 |
CN103033927A (zh) * | 2011-09-29 | 2013-04-10 | 斯坦雷电气株式会社 | 利用双蚀刻形成切割道的光学偏转器制造方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
US8293608B2 (en) * | 2008-02-08 | 2012-10-23 | Freescale Semiconductor, Inc. | Intermediate product for a multichannel FET and process for obtaining an intermediate product |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
CN101866834B (zh) * | 2009-12-11 | 2011-09-14 | 清华大学 | 高Ge组分SiGe材料的方法 |
DE102010029532B4 (de) * | 2010-05-31 | 2012-01-26 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Transistor mit eingebettetem verformungsinduzierenden Material, das in diamantförmigen Aussparungen auf der Grundlage einer Voramorphisierung hergestellt ist |
FR3003686B1 (fr) * | 2013-03-20 | 2016-11-04 | St Microelectronics Crolles 2 Sas | Procede de formation d'une couche de silicium contraint |
FR3006806A1 (fr) * | 2013-06-07 | 2014-12-12 | St Microelectronics Sa | Procede de formation de composants sur une couche de silicium-germanium |
US9105677B2 (en) | 2013-10-22 | 2015-08-11 | International Business Machines Corporation | Base profile of self-aligned bipolar transistors for power amplifier applications |
KR102085082B1 (ko) | 2013-10-30 | 2020-03-06 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US9570609B2 (en) | 2013-11-01 | 2017-02-14 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same |
US9484423B2 (en) | 2013-11-01 | 2016-11-01 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet III-V channel FETs |
US9647098B2 (en) | 2014-07-21 | 2017-05-09 | Samsung Electronics Co., Ltd. | Thermionically-overdriven tunnel FETs and methods of fabricating the same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6455398B1 (en) * | 1999-07-16 | 2002-09-24 | Massachusetts Institute Of Technology | Silicon on III-V semiconductor bonding for monolithic optoelectronic integration |
US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
US6603156B2 (en) * | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
US6855649B2 (en) * | 2001-06-12 | 2005-02-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US20030077882A1 (en) * | 2001-07-26 | 2003-04-24 | Taiwan Semiconductor Manfacturing Company | Method of forming strained-silicon wafer for mobility-enhanced MOSFET device |
JP2003078116A (ja) * | 2001-08-31 | 2003-03-14 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
CN1172376C (zh) * | 2001-12-29 | 2004-10-20 | 中国科学院上海微***与信息技术研究所 | 一种类似绝缘层上硅结构的材料及制备方法 |
US6793731B2 (en) * | 2002-03-13 | 2004-09-21 | Sharp Laboratories Of America, Inc. | Method for recrystallizing an amorphized silicon germanium film overlying silicon |
US6689671B1 (en) * | 2002-05-22 | 2004-02-10 | Advanced Micro Devices, Inc. | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate |
US6902991B2 (en) * | 2002-10-24 | 2005-06-07 | Advanced Micro Devices, Inc. | Semiconductor device having a thick strained silicon layer and method of its formation |
US6774015B1 (en) * | 2002-12-19 | 2004-08-10 | International Business Machines Corporation | Strained silicon-on-insulator (SSOI) and method to form the same |
-
2004
- 2004-11-30 EP EP04799280A patent/EP1697976A1/en not_active Withdrawn
- 2004-11-30 WO PCT/IB2004/052598 patent/WO2005059979A1/en not_active Application Discontinuation
- 2004-11-30 KR KR1020067011781A patent/KR20060123334A/ko not_active Application Discontinuation
- 2004-11-30 JP JP2006544616A patent/JP2007515790A/ja not_active Withdrawn
- 2004-11-30 US US10/596,422 patent/US7416957B2/en active Active
- 2004-11-30 CN CNB2004800373764A patent/CN100459042C/zh active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101924138A (zh) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微***与信息技术研究所 | 防止浮体及自加热效应的mos器件结构及其制备方法 |
CN101924138B (zh) * | 2010-06-25 | 2013-02-06 | 中国科学院上海微***与信息技术研究所 | 防止浮体及自加热效应的mos器件结构及其制备方法 |
CN103033927A (zh) * | 2011-09-29 | 2013-04-10 | 斯坦雷电气株式会社 | 利用双蚀刻形成切割道的光学偏转器制造方法 |
CN103033927B (zh) * | 2011-09-29 | 2016-04-06 | 斯坦雷电气株式会社 | 利用双蚀刻形成切割道的光学偏转器制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070166960A1 (en) | 2007-07-19 |
KR20060123334A (ko) | 2006-12-01 |
CN100459042C (zh) | 2009-02-04 |
JP2007515790A (ja) | 2007-06-14 |
EP1697976A1 (en) | 2006-09-06 |
US7416957B2 (en) | 2008-08-26 |
WO2005059979A1 (en) | 2005-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7211458B2 (en) | Methods of fabricating strained semiconductor-on-insulator field-effect transistors and related devices | |
CN1210763C (zh) | 半导体器件及其生产工艺 | |
CN1226775C (zh) | 半导体衬底的制造方法和半导体器件的制造方法 | |
US7615471B2 (en) | Method for producing a tensioned layer on a substrate, and a layer structure | |
CN1894775A (zh) | 在MOSFET结构中形成应变Si-沟道的方法 | |
CN1819201A (zh) | 具有提高的载流子迁移率的半导体结构及其制造方法 | |
CN101068004A (zh) | 半导体器件及其制造方法 | |
US7416965B2 (en) | Method for producing a strained layer on a substrate and corresponding layer structure | |
CN1574387A (zh) | 载流子迁移率提高的双栅极晶体管 | |
CN101076889A (zh) | 双应力soi衬底 | |
CN1770391A (zh) | 半导体结构及其制造方法 | |
CN1574395A (zh) | 用于提高mos性能的引入栅极的应变 | |
US20140151802A1 (en) | Semiconductor Device Having SSOI Substrate | |
CN1956199A (zh) | 半导体结构及其制造方法 | |
CN1705077A (zh) | 半导体材料和形成半导体材料的方法 | |
WO2007046150A1 (ja) | フィン型半導体装置及びその製造方法 | |
US20100084691A1 (en) | Semiconductor component with stress-absorbing semiconductor layer, and associated fabrication method | |
JP6525554B2 (ja) | 基板構造体を含むcmos素子 | |
CN1259694C (zh) | 半导体衬底生产方法及半导体衬底和半导体器件 | |
JP2003249641A (ja) | 半導体基板、その製造方法及び半導体装置 | |
CN1956214A (zh) | 场效应晶体管及其制造方法 | |
US20230395376A1 (en) | Semiconductor substrates and methods of producing the same | |
US9396935B1 (en) | Method of fabricating ultra-thin inorganic semiconductor film and method of fabricating three-dimensional semiconductor device using the same | |
CN114999921A (zh) | 具有硅锗鳍片的半导体结构及其制造方法 | |
JP3933405B2 (ja) | 半導体基板、半導体装置及びそれらの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20070810 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20070810 Address after: Holland Ian Deho Finn Applicant after: Koninkl Philips Electronics NV Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: IMEC CORP. Free format text: FORMER OWNER: KONINKL PHILIPS ELECTRONICS NV Effective date: 20120326 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20120326 Address after: Leuven Patentee after: IMEC Corp. Address before: Holland Ian Deho Finn Patentee before: Koninkl Philips Electronics NV |