CN1889274A - Silicon nano line homo pn junction diode and producing method thereof - Google Patents
Silicon nano line homo pn junction diode and producing method thereof Download PDFInfo
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- CN1889274A CN1889274A CN 200610019781 CN200610019781A CN1889274A CN 1889274 A CN1889274 A CN 1889274A CN 200610019781 CN200610019781 CN 200610019781 CN 200610019781 A CN200610019781 A CN 200610019781A CN 1889274 A CN1889274 A CN 1889274A
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Abstract
The present invention relates to a silicon nano wire homogeneity PN junction diode and preparation method. Said silicon nano wire homogeneity PN junction diode junction is prepared by utilizing boron diffusion technology diffusing forming P-type conduction layer on n-type conduction silicon wafer, forming plane homogeneity pn junction, then using non-electrode metal electrochemical deposition method self assembly forming nano structure as templet, etching forming nano wire on said plane pn junction silicon wafer, then obtaining silicon nano wire homogeneity pn junction. Said method features the required temp. approaching room temperature, simple equipment, low cost, capable of large area rapid preparation with easy controlled technological parameter. Said prepared silicon nano wire pn junction array has greater positive direction firing current density and reverse saturation current density than that of plane pn junction.
Description
Technical field
The present invention relates to a kind of silicon nano line homo pn junction diode and preparation method thereof, belong to field of nanometer material technology, also belong to field of electronic materials.
Background technology
Silicon nanowires is because self peculiar optics, electrical properties have important effect in nanoelectronics, and it both can be used as interconnection line, also can constitute function element, had great application prospect.Nano wire pn knot is the basic structure that constitutes nano electron device.Therefore, assembling silicon nanowires pn knot has great importance.The preparation method of nano electron device mainly contains two kinds at present, i.e. " from top to bottom " method and " from bottom to top " method.What is called is meant from top to bottom from the body material, utilizes film growth and nanoimprinting technology (electron beam lithography etc.) preparation nanostructure and device, the method good reproducibility, but with high costs, be difficult to a large amount of synthetic; And be meant from bottom to top from atom and molecule, self-assembled growth goes out needed nano material and structure, this just requires in the growth course of material its structure, component, size and position to be controlled, thereby direct growth is provided the nano-device of needed structure and performance, the method is with low cost, can synthesize in batches, but often be difficult to accurately control synthetic product.Original adoption photolithography etching technique and scanning tunneling microscopic method obtained silicon nanowires in the world, but output is very little, adopted laser scorification method up to 1998, and silicon nanowires has been realized a large amount of preparations first.The method of a large amount of synthetic silicon nanowires mainly comprises laser scorification method, thermal vapor deposition method, chemical vapour deposition technique etc. at present.Growth mechanism comprises based on the growth mechanism of gas-liquid-solid (VLS), oxide assisting growth mechanism etc.But these preparation methods often need high temperature, high vacuum, template, complex apparatus or needs to use some pernicious gases (as SiH
4), and be difficult to prepare the bulk silicon nanometer line ordered array.
Summary of the invention
At problems of the prior art, the purpose of this invention is to provide a kind of silicon nano line homo pn junction diode and preparation method thereof, this silicon nano line homo pn junction diode with low cost, and the preparation method has fast, large tracts of land, repeatable high advantage.
The technical scheme that realizes the object of the invention is a kind of silicon nano line homo pn junction diode, at least comprise pn knot and metal electrode, wherein the pn knot is to diffuse to form p type conductive layer with boron diffusion technology on n type conductive silicon chip, form the plane homogeneous pn junction, the nanostructure that forms with the self assembly of electrodeless metal electrochemical deposition method is a template again, etching forms nano wire, the silicon nano line homo pn junction of preparing on this plane pn knot silicon chip.
The method of this silicon nano line homo pn junction diode of preparation provided by the invention is to diffuse to form p type conductive layer with boron diffusion technology on n type conductive silicon chip earlier, form the plane homogeneous pn junction, the nanostructure that forms with the self assembly of electrodeless metal electrochemical deposition method is a template again, etching forms nano wire on this pn knot silicon chip, prepare silicon pn junction nanowire array, at last with photoresist or after insulating polymer fills between the nano wire space and solidifies, respectively with InGa alloy or Al at the n type silicon back side, Pt forms Ohm contact electrode in p type nanowire surface.
Wherein used electrodeless metal electrochemical deposition method (EMD) preparation silicon nanowires is that silicon substrate is placed the nitrate solution that contains silver ion or contains gold chloride radical ion AuCl
-Salting liquid and the mixed solution of hydrofluoric acid HF solution in, by the electrochemical action plated metal, etch silicon nanowire array in surface of silicon simultaneously.
The concrete steps that the method for preparing silicon nano line homo pn junction diode provided by the invention adopts are as follows:
(1) adopt cleaning method cleaning silicon chip commonly used in the semiconductor technology, and oven dry;
(2) using boron diffusion source, adopt two step diffusion methods, be divided into pre-deposited and distributed for two steps again, at first is pre-deposited, and pre-deposited is that constant surface source spreads, promptly at N
2Under the Buchholz protection; the surface of silicon chip is contacted with the thick-and-thin boron diffusion source of concentration; kept 20～30 minutes in 920～970 ℃; then distribute again; be distributed as the diffusion of defining surface source again; silicon chip after the pre-deposited soon hockets in 1100～1150 ℃ of logical dried oxygen-wet oxygen-dried oxygen, and the time is 1～2 hour, at last at N
2Buchholz protection drops to 20～40 ℃;
(3) abrasive disc: the oxide layer that grinds off the non-burnishing surface of silicon chip with conventional abrasive disc technology in the semiconductor;
(4) preparation of nano wire: first repeating step (1) cleans the silicon chip of abrasive disc, removes oxide layer in 3～10 minutes with mass percent 1～10% hydrofluoric acid dips silicon chip again, with argentiferous ion A g
+0.01 the nitrate of～0.1mol/L or contain gold chloride radical ion AuCl
-0.01 being 8～12% hydrofluoric acid, the salting liquid of～0.1mol/L and mass percent make reaction solution according to the equal-volume ratio, getting an amount of reaction solution pours in the polytetrafluoroethylcontainer container, silicon wafer polishing faced up immerse in the reaction solution, with autoclave as in the insulating box, in 30～80 ℃ of maintenances 30 minutes～10 hours, remove the silver or the gold grain of surface deposition at last with nitric acid or chloroazotic acid, use rinsed with deionized water, oven dry obtains the pn junction nanowire;
(5) fill: with photoresist or insulating polymer is filler, adopts spin-coating method to fill space between the nano wire, puts into baking oven then and carries out post bake, makes photoresist or insulating polymer solidify, stable, and high-insulation;
(6) electrode preparation: adopt splash-proofing sputtering metal Pt in p type nanowire surface, indium gallium InGa alloy or aluminium Al form Ohm contact electrode in the n type silicon back side.
Because the present invention utilizes boron diffusion to form p type layer on n type silicon chip, obtain plane pn knot, utilize self assembly to form unique orderly metal Nano structure again and be template, this plane of etching pn knot, thus make preparation n type, p type nano wire and homogeneous pn junction array thereof are finished synchronously, therefore not only equipment is simple for this preparation method, and is with low cost, and the preparation nano wire is temperature required near room temperature, but large tracts of land prepares fast, and technological parameter is also more easy to control.
Description of drawings
Accompanying drawing is a preparation method's of the present invention process chart.
Embodiment
Below in conjunction with specific embodiment technical scheme of the present invention is described in further detail:
As shown in drawings, silicon nano line homo pn junction diode provided by the invention comprises pn knot and metal electrode 1,3 at least, its pn knot is to diffuse to form p type conductive layer with boron diffusion technology on n type conductive silicon chip, form the plane homogeneous pn junction, the nanostructure that forms with the self assembly of electrodeless metal electrochemical deposition method is a template again, etching forms nano wire on this plane pn knot silicon chip, and between the nano wire space with photoresist or insulating polymer solidify and fill the silicon nano line homo pn junction of preparing.
Preparation method embodiment 1:
Below be example with single-sided polishing (100) orientation silicon chip, divide 6 steps to specify preparation process (seeing accompanying drawing):
(1) clean: used silicon chip is in this example: single-sided polishing (100) orientation silicon chip.Adopt No. 1 liquid commonly used in the semiconductor technology and the method for No. 2 liquid to come cleaning silicon chip.The prescription of No. 1 liquid is: concentrated ammonia liquor: 30% hydrogen peroxide: deionized water=1: 2: 7; The prescription of No. 2 liquid is: concentrated hydrochloric acid: 30% hydrogen peroxide: deionized water=1: 2: 7.Earlier boil silicon chip, make it boiling for a moment, treat that its cooling cleans up with deionized water again with No. 1 liquid.Put into No. 2 liquid then and boil silicon chip, make it boiling for a moment, treat the last taking-up of its cooling, clean up with deionized water again, at last oven dry.
(2) diffusion: use boron diffusion source, adopt two step diffusion methods.Be divided into pre-deposited and distributed again for two steps.Pre-deposited belongs to constant surface source diffusion, at N
2Under the Buchholz protection, 950 ℃ kept 20 minutes, and the surface of silicon chip contacts with the thick-and-thin impurity source of concentration.Distributing belongs to the diffusion of defining surface source again, hockets at 1130 ℃ of logical dried oxygen-wet oxygen-dried oxygen, and the time was assigned as 10 minutes, 30 minutes, 20 minutes.In diffusion process, the total impurities in the silicon chip remains unchanged.Do not have replenishing of exogenous impurity, only rely on that one deck a limited number of foreign atoms of pre-deposited on silicon chip surface, in wafer bulk, proceed diffusion.Distributed process is accompanied by surface oxidation and carries out simultaneously again, and the purpose of oxide layer is to stop foreign atom further to spread.At last at N
2Buchholz protection drops to 30 ℃ of room temperatures.
(3) abrasive disc: in front in Kuo San the process, silicon chip back is not owing to there is the protection of oxide layer, therefore diffused into boron yet and becomes the p type, occurs the pn knot of a parasitism so overleaf again, so must grind off the diffusion layer at the back side.At first, coat the wax water of fusing in the front of silicon chip and be adjacent to, can not leave bubble at sheet glass.On the focussing glass that abrasive disc is used, sprinkle clear water and MgO powder then, with the silicon chip reverse side down, the sheet glass that press...withes one's finger, mill " 8 " font on the abrasive disc plate.Up to the red complete obiteration of silicon chip reverse side, and return to till the initial color of silicon chip.With deionized water the silicon chip reverse side is rinsed well again.Boil sheet glass at last and make wax fusing, and remove surperficial wax with acetone is ultrasonic.
(4) preparation of nano wire: first repeating step 1 cleans the silicon chip of abrasive disc, removes oxide layer in 5 minutes with 10% hydrofluoric acid dips silicon chip again.For the EMD process, it is reaction vessel that employing has the teflon-lined high-pressure hydrothermal reaction kettle, and its volume is 60mL.With 0.02mol/LAgNO
3Solution and 10% hydrofluoric acid are mixed with reaction solution according to the equal-volume ratio, get about 40mL solution and pour in the polytetrafluoroethylcontainer container, silicon wafer polishing is faced up immerse in the reaction solution, and as in the insulating box, 50 ℃ kept one hour with autoclave.Remove silver with nitric acid at last, use rinsed with deionized water, oven dry.Gained pn junction nanowire always is about 10 μ m, the about 40～100nm of diameter.
(5) fill: the negative photoresist BN-302 that selects for use Beijing Inst. of Chemical Reagent to produce is a filler 2, adopts spin-coating method to fill space between the nano wire.With 3000 rev/mins speed rotations 25 seconds, put into baking oven then and carry out post bake.Heated 1 hour down at 120 ℃, make photoresist solidify, stable, and high-insulation.
(6) electrode preparation: adopt splash-proofing sputtering metal Pt in the n type silicon back side, the about 100nm of thickness makes top electrode 1, and indium gallium (InGa) alloy is made hearth electrode 3 in p type nanowire surface, forms Ohm contact electrode.
Preparation method embodiment 2:
(1) clean: used silicon chip is in this example: single-sided polishing (100) orientation silicon chip.Adopt No. 1 liquid commonly used in the semiconductor technology and the method for No. 2 liquid to come cleaning silicon chip.The prescription of No. 1 liquid is: concentrated ammonia liquor: 30% hydrogen peroxide: deionized water=1: 2: 7; The prescription of No. 2 liquid is: concentrated hydrochloric acid: 30% hydrogen peroxide: deionized water=1: 2: 7.Earlier boil silicon chip, make it boiling for a moment, treat that its cooling cleans up with deionized water again with No. 1 liquid.Put into No. 2 liquid then and boil silicon chip, make it boiling for a moment, treat the last taking-up of its cooling, clean up with deionized water again, at last oven dry.
(2) diffusion: use boron diffusion source, adopt two step diffusion methods.Be divided into pre-deposited and distributed again for two steps.Pre-deposited belongs to constant surface source diffusion, at N
2Under the Buchholz protection, 930 ℃ kept 20 minutes, and the surface of silicon chip contacts with the thick-and-thin impurity source of concentration.Distributing belongs to the diffusion of defining surface source again, hockets at 1120 ℃ of logical dried oxygen-wet oxygen-dried oxygen, and the time was assigned as 15 minutes, 45 minutes, 30 minutes.In diffusion process, the total impurities in the silicon chip remains unchanged.Do not have replenishing of exogenous impurity, only rely on that one deck a limited number of foreign atoms of pre-deposited on silicon chip surface, in wafer bulk, proceed diffusion.Distributed process is accompanied by surface oxidation and carries out simultaneously again, and the purpose of oxide layer is to stop foreign atom further to spread.At last at N
2Buchholz protection drops to 35 ℃ of room temperatures.
(3) abrasive disc: in front in Kuo San the process, silicon chip back is not owing to there is the protection of oxide layer, therefore diffused into boron yet and becomes the p type, occurs the pn knot of a parasitism so overleaf again, so must grind off the diffusion layer at the back side.At first, coat the wax water of fusing in the front of silicon chip and be adjacent to, can not leave bubble at sheet glass.On the focussing glass that abrasive disc is used, sprinkle clear water and MgO powder then, with the silicon chip reverse side down, the sheet glass that press...withes one's finger, mill " 8 " font on the abrasive disc plate.Up to the red complete obiteration of silicon chip reverse side, and return to till the initial color of silicon chip.With deionized water the silicon chip reverse side is rinsed well again.Boil sheet glass at last and make wax fusing, and remove surperficial wax with acetone is ultrasonic.
(4) preparation of nano wire: first repeating step 1 cleans the silicon chip of abrasive disc, removes oxide layer in 10 minutes with 5% hydrofluoric acid dips silicon chip again.For the EMD process, it is reaction vessel that employing has the teflon-lined high-pressure hydrothermal reaction kettle, and its volume is 60mL.To contain gold chloride radical ion AuCl
-0.02mol/L potassium salt soln and 12% hydrofluoric acid be mixed with reaction solution according to the equal-volume ratio, getting about 40mL solution pours in the polytetrafluoroethylcontainer container, silicon wafer polishing faced up immerse in the reaction solution, as in the insulating box, 60 ℃ kept one hour with autoclave.Remove gold grain with chloroazotic acid at last, use rinsed with deionized water, oven dry gets the pn junction nanowire.
(5) fill: selecting polyvinyl alcohol, polystyrene or resin etc. for use is filler 2, adopts spin-coating method to fill space between the nano wire.With 3000 rev/mins speed rotations 25 seconds, put into baking oven then and carry out post bake.Heated 1 hour down at 120 ℃, make insulating polymer solidify, stable, and high-insulation.
(6) electrode preparation: adopt splash-proofing sputtering metal Pt in the n type silicon back side, the about 100nm of thickness makes top electrode 1, and aluminium Al makes hearth electrode 3 in p type nanowire surface, forms Ohm contact electrode.
Prepared silicon nano line homo pn junction performance is tested, show that the forward firing current density of silicon nano line homo pn junction array and reverse saturation current density all increase to some extent with respect to the plane p-n junction.
Claims (5)
1. silicon nano line homo pn junction diode, at least comprise pn knot and metal electrode, it is characterized in that: the pn knot is to diffuse to form p type conductive layer with boron diffusion technology on n type conductive silicon chip, form the plane homogeneous pn junction, the nanostructure that forms with the self assembly of electrodeless metal electrochemical deposition method is a template again, etching forms nano wire, the silicon nano line homo pn junction of preparing on this plane pn knot silicon chip.
2. method for preparing the described silicon nano line homo pn junction diode of claim 1, it is characterized in that: on n type conductive silicon chip, diffuse to form p type conductive layer with boron diffusion technology earlier, form the plane homogeneous pn junction, the nanostructure that forms with the self assembly of electrodeless metal electrochemical deposition method is a template again, etching forms nano wire on this plane pn knot silicon chip, at last with photoresist or after insulating polymer fills between the nano wire space and solidifies, respectively with InGa alloy or Al at the n type silicon back side, Pt forms Ohm contact electrode in p type nanowire surface.
3. the preparation method of silicon nano line homo pn junction diode according to claim 2, it is characterized in that: preparing silicon nanowires with the electrodeless metal electrochemical deposition method is that silicon substrate is placed the nitrate solution that contains silver ion or contains gold chloride radical ion AuCl
-Salting liquid and the mixed solution of hydrofluoric acid HF solution in, by the electrochemical action plated metal, etch silicon nanowire array in surface of silicon simultaneously.
4. the preparation method of silicon nano line homo pn junction diode according to claim 2 is characterized in that adopting following concrete steps:
(1) adopt cleaning method cleaning silicon chip commonly used in the semiconductor technology, and oven dry;
(2) using boron diffusion source, adopt two step diffusion methods, be divided into pre-deposited and distributed for two steps again, at first is pre-deposited, and pre-deposited is that constant surface source spreads, promptly at N
2Under the Buchholz protection; the surface of silicon chip is contacted with the thick-and-thin boron diffusion source of concentration; kept 20～30 minutes in 920～970 ℃; then distribute again; be distributed as the diffusion of defining surface source again; silicon chip after the pre-deposited soon hockets in 1100～1150 ℃ of logical dried oxygen-wet oxygen-dried oxygen, and the time is 1～2 hour, at last at N
2Buchholz protection drops to 20～40 ℃;
(3) abrasive disc: the oxide layer that grinds off the non-burnishing surface of silicon chip with conventional abrasive disc technology in the semiconductor;
(4) preparation of nano wire: first repeating step (1) cleans the silicon chip of abrasive disc, removes oxide layer in 3～10 minutes with mass percent 1～10% hydrofluoric acid dips silicon chip again, with argentiferous ion A g
+0.01 the nitrate of～0.1mol/L or contain gold chloride radical ion AuCl
-0.01 being 8～12% hydrofluoric acid, the salting liquid of～0.1mol/L and mass percent make reaction solution according to the equal-volume ratio, getting an amount of reaction solution pours in the polytetrafluoroethylcontainer container, silicon wafer polishing faced up immerse in the reaction solution, with autoclave as in the insulating box, in 30～80 ℃ of maintenances 30 minutes～10 hours, remove the silver or the gold grain of surface deposition at last with nitric acid or chloroazotic acid, use rinsed with deionized water, oven dry obtains the pn junction nanowire;
(5) fill: with photoresist or insulating polymer is filler, adopts spin-coating method to fill space between the nano wire, puts into baking oven then and carries out post bake, makes photoresist or insulating polymer solidify, stable, and high-insulation;
(6) electrode preparation: adopt splash-proofing sputtering metal Pt in p type nanowire surface, indium gallium InGa alloy or aluminium Al form Ohm contact electrode in the n type silicon back side.
5. according to the preparation method of claim 2 or 4 described silicon nano line homo pn junction diodes, it is characterized in that: used insulating polymer is polyvinyl alcohol, polystyrene or resin.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894884A (en) * | 2010-06-10 | 2010-11-24 | 中国科学院苏州纳米技术与纳米仿生研究所 | Manufacture method of III group nitride nanometer array structure solar battery |
| CN102157621A (en) * | 2011-03-03 | 2011-08-17 | 郑州大学 | Square silicon nanometer hole and preparation method thereof |
| CN102592996A (en) * | 2012-03-05 | 2012-07-18 | 华东师范大学 | Preparation method for Schottky diode based on core/shell structure silicon nanowire set |
| CN111965158A (en) * | 2020-07-13 | 2020-11-20 | 江苏大学 | Single-step rapid preparation method of porous silicon-gold dendritic crystal composite structure |
| CN113161414A (en) * | 2021-04-29 | 2021-07-23 | 齐鲁工业大学 | Preparation method of PN micron line |
-
2006
- 2006-08-01 CN CN 200610019781 patent/CN1889274A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894884A (en) * | 2010-06-10 | 2010-11-24 | 中国科学院苏州纳米技术与纳米仿生研究所 | Manufacture method of III group nitride nanometer array structure solar battery |
| CN101894884B (en) * | 2010-06-10 | 2012-04-18 | 中国科学院苏州纳米技术与纳米仿生研究所 | Manufacture method of III group nitride nanometer array structure solar battery |
| CN102157621A (en) * | 2011-03-03 | 2011-08-17 | 郑州大学 | Square silicon nanometer hole and preparation method thereof |
| CN102157621B (en) * | 2011-03-03 | 2013-03-13 | 郑州大学 | Square silicon nanometer hole and preparation method thereof |
| CN102592996A (en) * | 2012-03-05 | 2012-07-18 | 华东师范大学 | Preparation method for Schottky diode based on core/shell structure silicon nanowire set |
| CN111965158A (en) * | 2020-07-13 | 2020-11-20 | 江苏大学 | Single-step rapid preparation method of porous silicon-gold dendritic crystal composite structure |
| CN113161414A (en) * | 2021-04-29 | 2021-07-23 | 齐鲁工业大学 | Preparation method of PN micron line |
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