CN100424892C - Heterojunction pn diode based on silicon nanoline and producing method thereof - Google Patents
Heterojunction pn diode based on silicon nanoline and producing method thereof Download PDFInfo
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- CN100424892C CN100424892C CNB2006100197829A CN200610019782A CN100424892C CN 100424892 C CN100424892 C CN 100424892C CN B2006100197829 A CNB2006100197829 A CN B2006100197829A CN 200610019782 A CN200610019782 A CN 200610019782A CN 100424892 C CN100424892 C CN 100424892C
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Abstract
The present invention relates to a heterogenous pn junction diode based on silicon nano wire and preparation method. Said diode features that it is p- silicon nano wire/n- wide bandgap oxide heterogenous pn junction formed by depositing n-type wide bandgap oxide in vertical orientation grown p - type silicon nano wire array. Said diode preparation method is: using non - electrode metal electrochemical deposition method to etch forming p type silicon nano wire on p type silicon wafer, then using formed vertical arrangement p type silicon nano array as templet depositing n-type wide bandgap oxide, finally respectively sputtering metal electrode on p type silicon back and n-type zinc oxide surface, forming ohmic contact electrode through annealing alloying. Said method prepared p - Si/n wide bandgap oxide heterogenous pn junction diode fully utilizes nano structure possessed large specific surface area, increasing carrier recombination probability and having lower positive direction cut-in voltage and large forward current density.
Description
Technical field
The present invention relates to a kind of novel diode of heterogenous pn junction based on silicon nanowires and preparation method thereof, belong to field of nanometer material technology, also belong to field of electronic materials.
Background technology
Existing pn junction diode is generally plane pn junction diode.It is reported, the Peng Kuiqing of material system of Tsing-Hua University, Zhu Jing seminar form the p-n junction structure by the CVD method at the top of p type silicon chip growth one deck n type silicon through research, be made into the p-n junction nano-wire array, and after the I-V curve of this p-n junction nano wire of testing out analyzed, find that this p-n junction nano wire has the peculiar rectifying effect of p-n junction.The I-V curve of this p-n junction nano wire is to adopt the AFM test.Nano wire is uncured, and surface of silicon nanowires does not adopt metal electrode.But yet there are no all reports in the world based on the oxide heterogeneous pn junction diode of the p-Si/n-broad-band gap of silicon nanowires at present.
Summary of the invention
For improving the performance of traditional plane pn junction diode, the invention provides a kind of diode of heterogenous pn junction based on silicon nanowires and preparation method thereof, the oxide heterogeneous pn junction diode of p-Si/n-broad-band gap of preparation has lower forward cut-in voltage and big forward current density, has improved the performance of conventional planar pn junction diode.
The oxide heterogeneous pn junction diode of p-Si/n-broad-band gap that technical scheme of the present invention is based on silicon nanowires comprises pn knot and metal electrode at least, and its pn knot is the oxide heterogeneous pn knot of p-silicon nanowires/n-broad-band gap that deposition n molded breadth band gap oxide forms in the p-type silicon nanowire array of vertical oriented growth.Wherein n-broad-band gap oxide comprises intrinsic n type ZnO, perhaps aluminium and/or gallium and/or indium doping zinc-oxide, perhaps SnO
2, ITO, In
2O
3, TiO
2Or Ga
2O
3
This method based on the oxide heterogeneous pn junction diode of p-Si/n-broad-band gap of silicon nanowires of preparation provided by the invention is that the metal Nano structure that forms with the self assembly of electrodeless metal electrochemical deposition method earlier is a template, etching forms silicon nanowire array on p type silicon chip, p type silicon nanowire array with the vertical arrangement that forms is a template deposition n molded breadth band gap oxide again, thereby prepare the oxide heterogeneous pn knot of p-silicon nanowires/n-broad-band gap, last deposit metal electrodes forms Ohm contact electrode by the after annealing alloying.
The employing concrete steps are as follows:
(1) adopts cleaning method cleaning silicon chip commonly used in the semiconductor technology and oven dry;
(2) preparation of p type silicon nanowires: will contain 0.01～0.1mol/L silver ion Ag
+Nitrate and mass percent be that 8～12% hydrofluoric acid are mixed with reaction solution according to the equal-volume ratio, or contain 0.01～0.1mol/L gold chloride radical ion AuCl
-Salting liquid and mass percent be that 8～12% hydrofluoric acid are mixed with reaction solution according to the equal-volume ratio, it is reaction vessel that employing has the teflon-lined high-pressure hydrothermal reaction kettle, getting an amount of reaction solution pours in the polytetrafluoroethylcontainer container, silicon wafer polishing faced up immerse in the reaction solution, high-pressure hydrothermal reaction kettle is placed insulating box, kept 30 minutes～10 hours in 30～80 ℃, remove silver or remove gold with nitric acid at last with chloroazotic acid, use rinsed with deionized water, oven dry gets p type silicon nanowires;
(3) deposition n molded breadth band gap oxide: before deposition, soak p type silicon nanowires with 1～10% hydrofluoric acid solution earlier and removed nanowire surface SiO in 3～10 minutes
2Layer, with n molded breadth band gap oxide is filler, adopt direct current magnetron sputtering process to coat p type silicon nanowires, fill p type silicon nanowires space, used conditional parameter is when carrying out magnetically controlled DC sputtering: target is that the good oxide ceramics target of conductivity, base vacuum degree are less than 10
-3Pa, underlayer temperature is 100～150 ℃, Ar air pressure is that 1～10Pa, power bracket 80～120W, sputtering time are 30 minutes～2 hours during deposition;
(4) preparation of electrode:, and, form Ohm contact electrode by the after annealing alloying at n type zinc oxide surface splash-proofing sputtering metal silver in p type silicon back spatter metal platinum.
Because the present invention is the p-type silicon nanowire array with vertical oriented growth is template deposition n molded breadth band gap oxide, again at the p type silicon back side and n molded breadth band gap oxide surface difference splash-proofing sputtering metal electrode, form Ohm contact electrode by the after annealing alloying, prepare the oxide heterogeneous pn junction diode of novel p-Si/n-broad-band gap based on silicon nanowires, the characteristics of the big specific area that nanostructure had have been made full use of, increased the charge carrier recombination probability, has lower forward cut-in voltage, big forward current density, thereby improved the performance of traditional plane pn junction diode, therefore, aspect photoelectricity, as aspects such as semiconductor laser and LED, has potential using value.
Description of drawings
Accompanying drawing is a preparation method's of the present invention process chart.
Embodiment
Below in conjunction with specific embodiment technical scheme of the present invention is described in further detail.
As shown in drawings, the oxide heterogeneous pn junction diode of p-Si/n-broad-band gap based on silicon nanowires provided by the invention comprises pn knot and metal electrode 1,4 at least, and its pn knot is the oxide heterogeneous pn knot of p-silicon nanowires/n-broad-band gap that deposition n molded breadth band gap oxide 2 forms in p-type silicon nanowires 3 arrays of vertical oriented growth.
Preparation method embodiment 1:
Be that example specifies preparation process with single-sided polishing (100) orientation silicon chip below.
(1) clean: used silicon chip is single-sided polishing (a 100) orientation silicon chip in this example.Adopt No. 1 liquid commonly used in the semiconductor technology and the method for No. 2 liquid to come cleaning silicon chip.The prescription of No. 1 liquid is: concentrated ammonia liquor: 30% hydrogen peroxide: deionized water=1: 2: 7; The prescription of No. 2 liquid is: concentrated hydrochloric acid: 30% hydrogen peroxide: deionized water=1: 2: 7.Earlier boil silicon chip, make it boiling for a moment, treat that its cooling cleans up with deionized water again with No. 1 liquid.Put into No. 2 liquid then and boil silicon chip, make it boiling for a moment, treat the last taking-up of its cooling, clean up with deionized water again, at last oven dry.
(2) preparation of p type silicon nanowires: it is reaction vessel that employing has the teflon-lined high-pressure hydrothermal reaction kettle, and its volume is 60mL.With 0.02mol/L AgNO
3Solution and 10% hydrofluoric acid are mixed with reaction solution according to the equal-volume ratio, get about 40mL solution and pour in the polytetrafluoroethylcontainer container, silicon wafer polishing is faced up immerse in the reaction solution, and as in the insulating box, 50 ℃ kept one hour with autoclave.Remove silver with nitric acid at last, use rinsed with deionized water, oven dry.Gained p type nano wire is about 10 μ m, the about 40～100nm of diameter.
(3) deposition n molded breadth band gap oxide.The ZnO (AZO) that chooses the aluminium doping of n type conduction is a filler, adopts the method for magnetically controlled DC sputtering to coat silicon nanowires, fills the silicon nanowires space.Before deposition AZO, soak 3 minutes place to go nanowire surface SiO with 10% hydrofluoric acid solution
2Layer.Target is selected the good AZO ceramic target of conductivity for use, and base vacuum is less than 10
-3Pa, underlayer temperature: 150 ℃, deposition is Ar air pressure: 3.9Pa, power 100W, sputtering time: 60min.
(4) electrode preparation.At the p type silicon back side and n type zinc oxide surface difference splash-proofing sputtering metal platinum and silver, form Ohm contact electrode by the after annealing alloying.
Preparation method embodiment 2:
Be that example specifies preparation process with single-sided polishing (100) orientation silicon chip below.
(1) clean: used silicon chip is single-sided polishing (a 100) orientation silicon chip in this example.Adopt No. 1 liquid commonly used in the semiconductor technology and the method for No. 2 liquid to come cleaning silicon chip.The prescription of No. 1 liquid is: concentrated ammonia liquor: 30% hydrogen peroxide: deionized water=1: 2: 7; The prescription of No. 2 liquid is: concentrated hydrochloric acid: 30% hydrogen peroxide: deionized water=1: 2: 7.Earlier boil silicon chip, make it boiling for a moment, treat that its cooling cleans up with deionized water again with No. 1 liquid.Put into No. 2 liquid then and boil silicon chip, make it boiling for a moment, treat the last taking-up of its cooling, clean up with deionized water again, at last oven dry.
(2) preparation of p type silicon nanowires: it is reaction vessel that employing has the teflon-lined high-pressure hydrothermal reaction kettle, and its volume is 60mL.To contain gold chloride radical ion AuCl
-0.02mol/L potassium salt soln and 12% hydrofluoric acid be mixed with reaction solution according to the equal-volume ratio, getting about 40mL solution pours in the polytetrafluoroethylcontainer container, silicon wafer polishing faced up immerse in the reaction solution, as in the insulating box, 60 ℃ kept one hour with autoclave.Remove gold grain with chloroazotic acid at last, use rinsed with deionized water, oven dry obtains p type nano wire.
(3) deposition n molded breadth band gap oxide.Choose SnO
2, ITO, In
2O
3, TiO
2Or Ga
2O
3Be filler, adopt the method for magnetically controlled DC sputtering to coat silicon nanowires, fill the silicon nanowires space.Before deposition, soak 10 minutes place to go nanowire surface SiO with 5% hydrofluoric acid solution
2Layer.Target is selected the good oxide ceramics target of conductivity for use, and base vacuum is less than 10
-3Pa, underlayer temperature: 150 ℃, deposition is Ar air pressure: 3.9Pa, power 120W, sputtering time: 45min.
(4) electrode preparation.At the p type silicon back side and n type zinc oxide surface difference splash-proofing sputtering metal platinum and silver, form Ohm contact electrode by the after annealing alloying.
Claims (4)
1. diode of heterogenous pn junction based on silicon nanowires, at least comprise pn knot and metal electrode, it is characterized in that: the pn knot is the oxide heterogeneous pn knot of p-silicon nanowires/n-broad-band gap that deposition n molded breadth band gap oxide forms in the p-type silicon nanowire array of vertical oriented growth.
2. the diode of heterogenous pn junction based on silicon nanowires according to claim 1 is characterized in that: n-broad-band gap oxide comprises intrinsic n type ZnO, perhaps aluminium and/or gallium and/or indium doping zinc-oxide, perhaps SnO
2, ITO, In
2O
3, TiO
2Or Ga
2O
3
3. the preparation method of the described diode of heterogenous pn junction based on silicon nanowires of a claim 1, it is characterized in that: the metal Nano structure that forms with the self assembly of electrodeless metal electrochemical deposition method is a template earlier, etching forms silicon nanowire array on p type silicon chip, p type silicon nanowire array with the vertical arrangement that forms is a template deposition n molded breadth band gap oxide again, thereby prepare the oxide heterogeneous pn knot of p-silicon nanowires/n-broad-band gap, last deposit metal electrodes forms Ohm contact electrode by the after annealing alloying.
4. the preparation method of the diode of heterogenous pn junction based on silicon nanowires according to claim 3 is characterized in that adopting step specific as follows:
(1) adopts cleaning method cleaning silicon chip commonly used in the semiconductor technology and oven dry;
(2) preparation of p type silicon nanowires: will contain 0.01～0.1mol/L silver ion Ag
+Nitrate and mass percent be that 8～12% hydrofluoric acid are mixed with reaction solution according to the equal-volume ratio, or contain 0.01～0.1mol/L gold chloride radical ion AuCl
-Salting liquid and mass percent be that 8～12% hydrofluoric acid are mixed with reaction solution according to the equal-volume ratio, it is reaction vessel that employing has the teflon-lined high-pressure hydrothermal reaction kettle, getting an amount of reaction solution pours in the polytetrafluoroethylcontainer container, silicon wafer polishing faced up immerse in the reaction solution, high-pressure hydrothermal reaction kettle is placed insulating box, kept 30 minutes～10 hours in 30～80 ℃, remove silver or remove gold with nitric acid at last with chloroazotic acid, use rinsed with deionized water, oven dry gets p type silicon nanowires;
(3) deposition n molded breadth band gap oxide: before deposition, soak p type silicon nanowires with 1～10% hydrofluoric acid solution earlier and removed nanowire surface SiO in 3～10 minutes
2Layer, with n molded breadth band gap oxide is filler, adopt direct current magnetron sputtering process to coat p type silicon nanowires, fill p type silicon nanowires space, used conditional parameter is when carrying out magnetically controlled DC sputtering: target is that the good oxide ceramics target of conductivity, base vacuum degree are less than 10
-3Pa, underlayer temperature is 100～150 ℃, Ar air pressure is that 1～10Pa, power bracket 80～120W, sputtering time are 30 minutes～2 hours during deposition;
(4) preparation of electrode:, and, form Ohm contact electrode by the after annealing alloying at n type zinc oxide surface splash-proofing sputtering metal silver in p type silicon back spatter metal platinum.
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| CN101921986A (en) * | 2010-07-16 | 2010-12-22 | 北京工业大学 | Zinc oxide doped PN homojunction and preparation method thereof |
| US8772144B2 (en) * | 2011-11-11 | 2014-07-08 | Alpha And Omega Semiconductor Incorporated | Vertical gallium nitride Schottky diode |
| CN103943733B (en) * | 2014-03-24 | 2016-08-17 | 上海交通大学 | A kind of preparation method of LED hyperparallels light source based on vertical nano-wire |
| CN108535337B (en) * | 2018-05-30 | 2021-04-20 | 杨丽娜 | Flexible gas sensor based on tin oxide/gallium oxide heterojunction nano array and preparation method thereof |
Citations (3)
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|---|---|---|---|---|
| CN1454841A (en) * | 2003-05-19 | 2003-11-12 | 清华大学 | Lurge area p-n junction nano silicon line array and preparing method thereof |
| CN1549279A (en) * | 2003-05-12 | 2004-11-24 | 财团法人工业技术研究院 | Method for producing high conducting electric nano-thin film type probe card |
| WO2004114422A1 (en) * | 2003-06-26 | 2004-12-29 | Postech Foundation | P-n heterojunction structure of zinc oxide-based nanorod and semiconductor thin film, preparation thereof, and nano-device comprising same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549279A (en) * | 2003-05-12 | 2004-11-24 | 财团法人工业技术研究院 | Method for producing high conducting electric nano-thin film type probe card |
| CN1454841A (en) * | 2003-05-19 | 2003-11-12 | 清华大学 | Lurge area p-n junction nano silicon line array and preparing method thereof |
| WO2004114422A1 (en) * | 2003-06-26 | 2004-12-29 | Postech Foundation | P-n heterojunction structure of zinc oxide-based nanorod and semiconductor thin film, preparation thereof, and nano-device comprising same |
Non-Patent Citations (4)
| Title |
|---|
| Dendrite-assisted growth of silicon nanowires in electrolessmetal deposition. Peng KQ, Yan YJ, Gao SP, Zhu J.ADVANCED FUNCTIONAL MATERIALS,Vol.13 No.2. 2003 |
| Dendrite-assisted growth of silicon nanowires in electrolessmetal deposition. Peng KQ, Yan YJ, Gao SP, Zhu J.ADVANCED FUNCTIONAL MATERIALS,Vol.13 No.2. 2003 * |
| Fabrication of large-area silicon nanowire p-njunctiondiodearrays. Peng KQ, Huang ZP, Zhu J.ADVANCED MATERIALS,Vol.16 No.1. 2004 |
| Fabrication of large-area silicon nanowire p-njunctiondiodearrays. Peng KQ, Huang ZP, Zhu J.ADVANCED MATERIALS,Vol.16 No.1. 2004 * |
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