CN1885723A - Signal amplitude section divided charge redistribution successive approximation A/D converter - Google Patents

Abstract

The related successive approximating ADC comprises: a capacitor array with a T-shaped contact switch S1 on input end connected to input voltage end and reference voltage end and half reference voltage end respectively, an operational amplifier, a successive approximation logic module, and a switch. This invention can obtain better conversion precision with almost same structure.

Description

The charge redistribution of signal amplitude interval division is approached A/D converter one by one

Technical field

The present invention's " charge redistribution of signal amplitude interval division is approached A/D converter one by one " relates to technical field of electronic devices.

Technical background

A/D (Analog-to-Digital) transducer is the indispensable interface between analog signal and the digital signal in all electronic systems, and its conversion accuracy directly influences the indicators of overall performance of whole electronic system.A/D converter is of a great variety, but mainly can be classified as three classes: low resolution high-speed type (as: Flash, Folding, Pipelined etc.), high-resolution low speed type (as: Sigma-delta, Dual-integrating etc.) and intermediate resolution medium speed type (as: SuccessiveApproximation).(Successive Approximation) A/D converter that approaches one by one based on charge redistribution on the capacitor array (Charge Redistribution) is resolution and the compromise ideal scheme (circuit theory as shown in Figure 1) of conversion speed, have less circuit power consumption and area, lower circuit complexity, the conversion figure place can be adjusted by the logical circuit programming neatly, advantages such as analog input signal voltage easy switching, be specially adapted to multi-channel signal acquiring, and multiple signals amplitude difference is bigger, resolution and conversion speed require very not harsh occasion, as: the portable medical instrument, multiple microsensor input, applications of ultrasound, integrated control system etc.

Because the fabrication error that cmos device exists, the used capacitor array of charge redistribution successive approximation A/D converter can not reach the ideal matching precision after processing.If the maximal phase reduced value deviation between electric capacity is defined as δ (δ＜1), pass through theoretical derivation can obtain A/D converter under δ and the worst case may reach resolution figure place N the pass be:

$N={\log }_2\left(\frac{1+\mathrm{\δ}+\sqrt{1+2\mathrm{\δ}-3{\mathrm{\δ}}^2}}{2\mathrm{\δ}}\right)---(1-1)$

By formula (1-1) as can be known, the resolution that existing charge redistribution is approached A/D converter one by one is not high, and very big limitation is arranged.

Summary of the invention

The present invention is directed to this limitation problem of prior art, a kind of circuit structure that approaches A/D converter based on the charge redistribution of signal amplitude interval division is one by one proposed, thereby under the prerequisite of given δ, can improve the resolution (N) of approaching A/D converter by the represented charge redistribution of formula (1-1) one by one.

For achieving the above object, technical solution of the present invention provides a kind of charge redistribution of signal amplitude interval division and approaches A/D converter one by one, comprises capacitor array, operational amplifier, approaches logic module and switch one by one, and each parts connects routinely; Its capacitor array input is provided with one or three contact-making switch S1, and three contact points of switch S 1 are connected with input voltage signal end, reference voltage end and 1/2nd reference voltage end respectively; Wherein, the electrode input end of 1/2nd reference voltage end and operational amplifier is by switching circuit ground connection.

Described A/D converter, its described switching circuit is made up of switch and electric capacity, comprises switch S 5, capacitor C _REF, switch S 6, switch S 4, three switches be 2 contact-making switches, wherein one point earths; / 2nd reference voltage end are in proper order by switch S 5, capacitor C _REF, switch S 6 ground connection, simultaneously, the electrode input end of operational amplifier is by switch S 4 ground connection; The electrode input end of exclusive disjunction amplifier is in proper order by switch S 4, switch S 6, capacitor C _REF, switch S 5 ground connection.

The course of work of described A/D converter, it comprises following flow process:

(1) sample states: the by-pass switch S of operational amplifier ₂Closure, capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the right, switch S ₁Meet V _InSide, switch S ₄Ground connection, input voltage V at this moment _InElectric capacity master array is charged; Switch S ₆Ground connection, switch S ₅Beat to Side makes reference voltage To capacitor C _REFCharging is so that the use during for the III district is prepared;

(2) hold mode: the by-pass switch S of operational amplifier ₂Open, simultaneously capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the left, switch S ₄Ground connection, the electric charge on the electric capacity master array remains unchanged V _XThe current potential of point is-V _InSwitch S ₆Beat to the right switch S ₅Ground connection, switch S ₁Beat to V _RefSide is for to V _InDeclaring " section " subregion state prepares;

(3) declare " section " state: the by-pass switch S of operational amplifier ₂Stay open switch S ₁Remain on V _RefSide, switch S ₄Still ground connection is approached A-B-C-D-E-F-G branch " section " form of logic module according to the register pre-stored, one by one with capacitance switch b _N-1, b _N-2... b ₁, b ₀Be set to corresponding assembled state, obtain corresponding current potential V _X, by V _XThe point current potential and " " comparative result, can judge the aanalogvoltage V that inserts this moment _InBe positioned at which interval range;

(4) approach state by turn: declare " section " and finish capacitance switch b _N-1, b _N-2... b ₁, b ₀By the high position beginning, sound out respectively and beat contact to the right, change V _XThe potential value of point $V_X=V_{X0}+V_{\mathrm{com}}(\frac{1}{2}{b}_{n-1}+\frac{1}{2^2}{b}_{n-2}+\·\·\·+\frac{1}{2^{n-1}}{b}_1+\frac{1}{2^n}{b}_0),$ Circulate by turn in I, II, IV district and to approach V _X=0, circulate by turn in the III district and to approach $V_X=-\frac{1}{2}{V}_{\mathrm{ref}},$ Thereby can determine corresponding V _InDigital quantity D=D _N-1D _N-2D ₁D ₀

(5) final transformation result: for the input voltage in I, IV district, the output digital quantity is wanted corresponding reference voltage V _RefAnd corresponding reference voltage is wanted in the output in II district

The pairing digital quantity of voltage that the output in III district is deducted in the time of will adding input, its pairing reference voltage also is

Approach Digital Logic in the logic module one by one according to the different digital quantity (D=D of the corresponding bias voltage in each district and reference voltage to output _N-1D _N-2D ₁D ₀) carry out normalized.

The course of work of described A/D converter, its described (3) declare " section " state, are that utilization dichotomous search algorithm is judged the aanalogvoltage V that insert this moment _InBe positioned at which interval range; When declaring the end of " section " state, with capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the left, recover V _XThe initial potential V of point _X0For-V _In

The course of work of described A/D converter, its described recovery V _XThe initial potential V of point _X0For-V _InAfter,

1. if V _InBe positioned at I, IV district, then switch S ₁Remain on V _RefSide, reference voltage V _Com=V _Ref, switch S ₄Ground connection still is for NextState is prepared;

2. if V _InBe positioned at the II district, then switch S ₁Beat to

Side, reference voltage $V_{\mathrm{com}}=\frac{1}{2}{V}_{\mathrm{ref}},$ Switch S ₄Ground connection still is for NextState is prepared;

3. if V _InBe positioned at the III district, then switch S ₁Beat to

Side, reference voltage $V_{\mathrm{com}}=\frac{1}{2}{V}_{\mathrm{ref}},$ Switch S ₄Beat contact to the left, this has inserted one with regard to the in-phase end that is equivalent to operational amplifier Bias voltage, for NextState is prepared.

" charge redistribution of signal amplitude interval division is approached A/D converter one by one " of the present invention can be constant substantially at hardware configuration, obtain conversion accuracy preferably under the situation that circuit complexity is less.

Description of drawings

The basic block diagram that Fig. 1 approaches A/D converter one by one for existing charge redistribution;

Fig. 2 approaches the error profile curve chart (N=6 of A/D converter with the output digital quantity one by one for charge redistribution; δ=0.001);

Fig. 3 approaches the A/D converter electrical block diagram one by one for the charge redistribution of signal amplitude interval division of the present invention.

Embodiment

Under given CMOS fabrication error condition, the uncertainty of capacitance ratio has limited the resolution that charge redistribution is approached A/D converter one by one, for reducing this influence, the error model that is approached A/D converter by charge redistribution one by one sets out, and has invented from the research of its analysis result and a kind ofly can improve the circuit structure of resolution more than one at least.Following mask body is introduced the invention thinking.

Please refer to document: " J.L.Mccreary; P.R.Gray; " All-MOS ChargeRedistribution Analog-to-digital Conversion Techniques-Part I "; IEEE J.Solid-State Circuits; Dec.1975; SC-10 (6): 60-68. " from the basic principle of charge redistribution successive approximation A/D converter, the ideal potential that x is ordered among Fig. 1 is $V_x=-V_{\mathrm{in}}+\underset{i=1}{\overset{N}{\mathrm{\Σ}}}\frac{1}{2^i}{V}_{\mathrm{ref}}{D}_{N-i},$ And consider the technology coupling deviation of capacitor array, then the x actual potential of ordering is: $V_{\mathrm{real}}=\left({-V}_{\mathrm{in}}\right)+V_{\mathrm{ref}}\underset{i=1}{\overset{N}{\mathrm{\Σ}}}\left(\frac{C_{N-i}}{\underset{k=1}{\overset{N}{\mathrm{\Σ}}}{C}_k+C}{D}_{N-i}\right),$ C _N-iBe the actual capacitance value of corresponding position, C _kBe ideal capacitance value, C is the specific capacitance value, D _N-iBe output digital quantity, V _RefBe reference voltage, V _InBe input voltage signal.Definition error voltage Δ V=V _Real-V _x, to a certain δ and the ceiling effect after considering the capacitance random distribution, then can derive the relative error voltage Δ V/V that charge redistribution is approached A/D converter one by one _RefWith output digital quantity (D _N-1D _N-2... D ₀) relation.Its curve is parabolic shape, promptly when the output digital quantity when less and big relative error voltage less, and maximum relative error voltage occurs in MSB (Most Significant Bit)=1, all the other positions are at 0 o'clock.Being without loss of generality, is example with 6 A/D converters, its error profile curve such as Fig. 2 (A-B-J-F-G section).Consider that simultaneously when the ADC figure place was big, the value of missing by a mile was almost irrelevant with figure place N, and only linear with the maximum technology relative deviation of electric capacity δ, has:

ΔV _max≈V _ref· ^δ/ ₂ (2-1)

Resolution is mainly according to Δ V _Max/ V _{In, max}, have:

${\mathrm{\ΔV}}_{\max }/V_{\mathrm{in},\max }=V_{\mathrm{ref}}\·\frac{\mathrm{\δ}}{2}/V_{\mathrm{in},\max }---(2-2)$

V _{In, max}For input voltage the maximum that can allow, be changeless.In traditional circuit, select reference voltage V _RefAnd V _{In, max}Equate.Because therefore the A/D converter distribution curve rule of isotopic number is not without loss of generality all as shown in Figure 2, we are that example is set forth proposed invention thought with 6 ADC still:

1. the relative error curve is carried out interval division, the foundation of dividing is to be benchmark with half of relative error peak value, and as shown in Figure 2: the half-sum symmetry axis with maximum relative error voltage is divided into four interval: I (A-B), II (C-D), III (D-E), IV (F-G) district with it.The pairing output digital quantity of breakover point (being A, B, C, D, E, F, G) to four intervals can precompute, and stores then as the segmentation form.

2. different interval input voltages are adopted different processing methods.Set out by (2-1) formula, if reference voltage V _RefReduce by 1/2, Δ V _MaxValue also will reduce half, can know that according to (2-2) formula resolution will obtain one raising.Based on this, we can be by reducing V _RefImprove the conversion accuracy of ADC.Still adopt original reference voltage in I, IV district, promptly the relative error curve still is the respective regions inner curve.In II, III district reference voltage is reduced by half, and the III district also will deduct input voltage former reference voltage half in advance, this is because at this moment reference voltage has limited the maximum of corresponding input voltage.Handle later error curve like this shown in Fig. 2 (AB-CHDIE-FG section).Conversion accuracy also just can improve one.And the like, can in proper range, improve long precision.

Circuit structure of the present invention as shown in Figure 3.A kind of charge redistribution of signal amplitude interval division is approached A/D converter one by one, comprises capacitor array, operational amplifier, approaches logic module and switch one by one, and each parts connects routinely; Its capacitor array input is provided with one or three contact-making switch S1, three contact points of switch S 1 respectively with input voltage signal end V _In, reference voltage end V _RefWith 1/2nd reference voltage end Be electrically connected; Wherein, 1/2nd reference voltage end Link to each other or ground connection with the electrode input end of operational amplifier by switching circuit.

Wherein, switching circuit is made up of switch and electric capacity, comprises switch S 5, capacitor C _REF, switch S 6, switch S 4, three switch S 4, S5, S6 be 2 contact-making switches, wherein one point earths; / 2nd reference voltage end

Order is by switch S 5, capacitor C _REF, switch S 6 ground connection, simultaneously, the electrode input end of operational amplifier is by switch S 4 ground connection; The electrode input end of exclusive disjunction amplifier is in proper order by switch S 4, switch S 6, capacitor C _REF, switch S 5 ground connection.

Approach a plurality of digital output end D of logic module one by one _N-1... D ₁D ₀, link to each other with treatment facility during use.

The concrete course of work that the charge redistribution of signal amplitude interval division of the present invention is approached A/D converter one by one is as follows:

(1) sample states: the by-pass switch S of operational amplifier ₂Closure, capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the right, switch S ₁Meet V _InSide, switch S ₄Ground connection, input voltage V at this moment _InElectric capacity master array is charged.In addition, switch S ₆Ground connection, switch S ₅Beat to

Side makes reference voltage

To capacitor C _REFCharging is so that the use during for the III district is prepared.

(2) hold mode: the by-pass switch S of operational amplifier ₂Open, simultaneously capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the left, switch S ₄Ground connection, the electric charge on the electric capacity master array remains unchanged V _XThe current potential of point is-V _InThen, switch S ₆Beat to the right switch S ₅Ground connection, switch S ₁Beat to V _RefSide is for to V _InDeclaring " section " subregion state prepares.

(3) declare " section " state: the by-pass switch S of operational amplifier ₂Stay open switch S ₁Remain on V _RefSide, switch S ₄Still ground connection is approached A-B-C-D-E-F-G branch " section " form of logic module according to the register pre-stored, one by one with capacitance switch b _N-1, b _N-2... b ₁, b ₀Be set to corresponding assembled state, obtain corresponding current potential V _X, by V _XThe point current potential and " " comparative result, can judge the aanalogvoltage V that inserts this moment _InBe positioned at which interval range.Be example still, earlier capacitance switch be set to (100000) of ordering corresponding to D, if comparative result with 6 $V_X={-V}_{\mathrm{in}}+\frac{1}{2}{V}_{\mathrm{ref}}<0,$ V then _InThe interval at place is positioned at D point right side, is the III district.Next capacitance switch is set to (110101) of ordering, if comparative result corresponding to E $V_X={-V}_{\mathrm{in}}+(\frac{1}{2}+\frac{1}{2^2}+\frac{1}{2^4}+\frac{1}{2^6})V_{\mathrm{ref}}<0,$ V then _InBe positioned at E point right side between the location, be the IV district.To other situation, can use this dichotomous search algorithm (Binary Search) to judge.When declaring the end of " section " state, with capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the left, recover V _XThe initial potential V of point _X0For-V _In:

1. if V _InBe positioned at I, IV district, then switch S ₁Remain on V _RefSide, reference voltage V _Com=V _Ref, switch S ₄Ground connection still is for NextState is prepared;

2. if V _InBe positioned at the II district, then switch S ₁Beat to

Side, reference voltage $V_{\mathrm{com}}=\frac{1}{2}{V}_{\mathrm{ref}},$ Switch S ₄Ground connection still is for NextState is prepared;

3. if V _InBe positioned at the III district, then switch S ₁Beat to

Side, reference voltage $V_{\mathrm{com}}=\frac{1}{2}{V}_{\mathrm{ref}},$ Switch S ₄Beat contact to the left, this has inserted one with regard to the in-phase end that is equivalent to operational amplifier Bias voltage, for NextState is prepared;

(4) approach state by turn: declare " section " and finish capacitance switch b _N-1, b _N-2... b ₁, b ₀By the high position beginning, sound out respectively and beat contact to the right, change V _XThe potential value of point $V_X=V_{X0}+V_{\mathrm{com}}(\frac{1}{2}{b}_{n-1}+\frac{1}{2^2}{b}_{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;+\frac{1}{2^{n-1}}{b}_1+\frac{1}{2^n}{b}_0),$ Circulate by turn in I, II, IV district and to approach V _X=0, circulate by turn in the III district and to approach $V_X=-\frac{1}{2}{V}_{\mathrm{ref}},$ Thereby can determine corresponding V _InDigital quantity D=D _N-1D _N-2D ₁D ₀

(5) final transformation result: for the input voltage in I, IV district, the output digital quantity is wanted corresponding reference voltage V _RefAnd corresponding reference voltage is wanted in the output in II district

The pairing digital quantity of voltage that the output in III district is deducted in the time of will adding input, its pairing reference voltage also is Approach Digital Logic in the logic module one by one according to the different digital quantity (D=D of the corresponding bias voltage in each district and reference voltage to output _N-1D _N-2D ₁D ₀) carry out normalized.

Claims (5)

1. the charge redistribution of a signal amplitude interval division is approached A/D converter one by one, comprises capacitor array, operational amplifier, approaches logic module and switch one by one, and each parts connects routinely; It is characterized in that the capacitor array input is provided with one or three contact-making switch S1, three contact points of switch S 1 are connected with input voltage signal end, reference voltage end and 1/2nd reference voltage end respectively; Wherein, the electrode input end of 1/2nd reference voltage end and operational amplifier is by switching circuit ground connection.

2. A/D converter as claimed in claim 1 is characterized in that, described switching circuit is made up of switch and electric capacity, comprises switch S 5, capacitor C _REF, switch S 6, switch S 4, three switches be 2 contact-making switches, wherein one point earths; / 2nd reference voltage end are in proper order by switch S 5, capacitor C _REF, switch S 6 ground connection, simultaneously, the electrode input end of operational amplifier is by switch S 4 ground connection; The electrode input end of exclusive disjunction amplifier is in proper order by switch S 4, switch S 6, capacitor C _REF, switch S 5 ground connection.

3. the course of work of A/D converter as claimed in claim 1 is characterized in that, comprises following flow process:

(1) sample states: the by-pass switch S of operational amplifier ₂Closure, capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the right, switch S ₁Meet V _InSide, switch S ₄Ground connection, input voltage V at this moment _InElectric capacity master array is charged; Switch S ₆Ground connection, switch S ₅Beat to

Side makes reference voltage To capacitor C _REFCharging is so that the use during for the III district is prepared;

(2) hold mode: the by-pass switch S of operational amplifier ₂Open, simultaneously capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the left, switch S ₄Ground connection, the electric charge on the electric capacity master array remains unchanged V _XThe current potential of point is-V _InSwitch S ₆Beat to the right switch S ₅Ground connection, switch S ₁Beat to V _RefSide is for to V _InDeclaring " section " subregion state prepares;

(3) declare " section " state: the by-pass switch S of operational amplifier ₂Stay open switch S ₁Remain on V _RefSide, switch S ₄Still ground connection is approached A-B-C-D-E-F-G branch " section " form of logic module according to the register pre-stored, one by one with capacitance switch b _N-1, b _N-2... b ₁, b ₀Be set to corresponding assembled state, obtain corresponding current potential V _X, by V _XThe point current potential and " " comparative result, can judge the aanalogvoltage V that inserts this moment _InBe positioned at which interval range;

(4) approach state by turn: declare " section " and finish capacitance switch b _N-1, b _N-2... b ₁, b ₀By the high position beginning, sound out respectively and beat contact to the right, change V _XThe potential value of point $V_X=V_{X0}+V_{\mathrm{com}}(\frac{1}{2}{b}_{n-1}+\frac{1}{2^2}{b}_{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;+\frac{1}{2^{n-1}}{b}_1+\frac{1}{2^n}{b}_0),$ Circulate by turn in I, II, IV district and to approach V _X=0, circulate by turn in the III district and to approach $V_X=-\frac{1}{2}{V}_{\mathrm{ref}},$ Thereby can determine corresponding V _InDigital quantity D=D _N-1D _N-2D ₁D ₀

(5) final transformation result: for the input voltage in I, IV district, the output digital quantity is wanted corresponding reference voltage V _RefAnd corresponding reference voltage is wanted in the output in II district The pairing digital quantity of voltage that the output in III district is deducted in the time of will adding input, its pairing reference voltage also is

Approach Digital Logic in the logic module one by one according to the different digital quantity (D=D of the corresponding bias voltage in each district and reference voltage to output _N-1D _N-2D ₁D ₀) carry out normalized.

4. the course of work of A/D converter as claimed in claim 3 is characterized in that, described (3) declare " section " state, is that utilization dichotomous search algorithm is judged the aanalogvoltage V that insert this moment _InBe positioned at which interval range; When declaring the end of " section " state, with capacitance switch S ₃, b _N-1, b _N-2... b ₁, b ₀Beat contact to the left, recover V _XThe initial potential V of point _X0For-V _In

5. the course of work of A/D converter as claimed in claim 6 is characterized in that, described recovery V _XThe initial potential V of point _X0For-V _InAfter,

1. if V _InBe positioned at I, IV district, then switch S ₁Remain on V _RefSide, reference voltage V _Com=V _Ref, switch S ₄Ground connection still is for NextState is prepared;

2. if V _InBe positioned at the II district, then switch S ₁Beat to Side, reference voltage $V_{\mathrm{com}}=\frac{1}{2}{V}_{\mathrm{ref}},$ Switch S ₄Ground connection still is for NextState is prepared;

3. if V _InBe positioned at the III district, then switch S ₁Beat to

Side, reference voltage $V_{\mathrm{com}}=\frac{1}{2}{V}_{\mathrm{ref}},$ Switch S ₄Beat contact to the left, this has inserted one with regard to the in-phase end that is equivalent to operational amplifier

Bias voltage, for NextState is prepared.

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