CN1841333A - Dynamic random memory testing method and system thereof - Google Patents
Dynamic random memory testing method and system thereof Download PDFInfo
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- CN1841333A CN1841333A CN 200510059920 CN200510059920A CN1841333A CN 1841333 A CN1841333 A CN 1841333A CN 200510059920 CN200510059920 CN 200510059920 CN 200510059920 A CN200510059920 A CN 200510059920A CN 1841333 A CN1841333 A CN 1841333A
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Abstract
The related dynamic random memory (DRM) with auto testing mechanism comprises: a DRM unit, and a dynamic random memory controller (DAMC) to receive testing command from a system CPU, execute the auto testing and return the result to the CPU.
Description
Technical field
The present invention relates to a kind of internal memory and a kind of automatic test approach, particularly relate to a kind of dynamic random memory with automatic test machine system and this internal memory is carried out automatic test method.
Background technology
Dynamic random memory (DRAM) is quite important in computing machine, has played the part of the role of temporary transient storage data.Central processing unit (CPU) can program or data that some are commonly used read in dynamic random memory earlier, because the access speed of dynamic random memory is faster than permanent storage medium (for example hard disk, Hard Disk), therefore can increase the speed of computer processing data.
All can carry out the action that dynamic random memory is tested during computer booting.After computer system determines that dynamic random memory is no problem, just can carry out the action of system boot.
Common method of testing is to utilize the execution cycle of central processing unit, directly to the fixing some execution cycles of dynamic random memory controller, removes to check the storage element of each address of dynamic random memory.
Such method of testing makes central processing unit must tell some times and handles the test action of dynamic random memory that therefore, reduced the efficient of central processing unit, the dynamic random memory test duration also can extend simultaneously.
Summary of the invention
At the defective that above-mentioned method of testing exists, technical matters to be solved by this invention is to provide a kind of method of testing that shortens the dynamic random memory test duration,
Another technical matters to be solved by this invention is to provide a kind of and the corresponding dynamic random memory with automatic test machine system of said method.
For achieving the above object, the automatic test approach step of this dynamic random memory is as follows:
One central processing unit, a dynamic random memory are provided, and this dynamic random memory comprises a dynamic random memory controller and dynamic random memory storage element;
Described central processing unit is assigned a test command to described dynamic random memory controller;
Described dynamic random memory controller is tested this dynamic random memory storage element automatically because of accepting this test command, and test result is back to this central processing unit.
After described central processing unit is received this test result, can write down the fault block of this dynamic random memory storage element, and when access, keep away this fault block.
Described dynamic random memory can be DRAM, DDR or other internal memory.
A kind of dynamic random memory with automatic test machine system can be because of accepting the action that a certain test command that central processing unit assigns is tested automatically, and it comprises:
One dynamic random memory controller can be accepted the test command that this central processing unit is assigned;
One dynamic random memory storage element, be electrically connected to this dynamic random memory controller, this dynamic random memory controller can be tested automatically this dynamic random memory storage element, and test result is back to described central processing unit because of accepting test command.
After described central processing unit is received this test result, can write down the fault block of this dynamic random memory storage element, and when access, keep away this fault block.
Described dynamic random memory can be DRAM, DDR or other internal memory.
From the above, begin system and method that the dynamic random memory storage element is tested automatically owing to adopt central processing unit to assign test command to the dynamic random memory controller, central processing unit can " necessary " be told some times and is handled the test action of dynamic random memory, therefore, improve the efficient of central processing unit, shortened the time of dynamic random memory test.
Description of drawings
Fig. 1 is the calcspar of most preferred embodiment of the present invention.
Detailed description of main elements
11: central processing unit
12: dynamic random memory
122: the dynamic random memory storage element
121: the dynamic random memory controller
1211: automatic testing equipment
Embodiment
The present invention is described further below in conjunction with drawings and Examples.
Fig. 1 is a most preferred embodiment calcspar of the present invention.Generally speaking, central processing unit 11 can carry out data access to the dynamic random memory storage element 122 of dynamic random memory 12.Under test (Test) pattern or debug (Debug) pattern, 11 need of central processing unit are assigned a test command to dynamic random memory controller 121, the dynamic random memory controller promptly starts inner automatic testing equipment 1211, comes the action that the dynamic random memory storage element is tested automatically.
Thus, can improve the work efficiency of central processing unit, make it have more time to handle other action.After the test action of dynamic random memory storage element was finished, the dynamic random memory controller only needed to send signal to central processing unit 11, and central processing unit can be learnt test result.
Test result further can comprise the state of each block of dynamic random memory storage element, if run into out of order storage block, can be recorded as the fault block, so when normal operation, can avoid this fault block makes computing machine continue normal operation, even if minority fault block is arranged, whole dynamic random memory 12 still can use.
Certainly, the dynamic random memory with automatic test machine system as described wherein, after central processing unit is received this test result, can write down the fault block of this dynamic random memory storage element, and when access, keep away this fault block.This dynamic random memory can be DRAM or DDR or other can carry out the internal memory of access.
For the disclosed technology of the present invention, those skilled in the art can implement according to this.The foregoing description still is not enough to contain the claimed claim of the present invention, and is therefore within the spirit and principles in the present invention all, any modification of being done, is equal to replacement, transformation etc., all should be included within the claim scope of the present invention.
Claims (6)
1. the automatic test approach of a dynamic random memory, its step is as follows:
One central processing unit, a dynamic random memory are provided, and this dynamic random memory comprises a dynamic random memory controller and dynamic random memory storage element;
Described central processing unit is assigned a test command to described dynamic random memory controller;
Described dynamic random memory controller is tested this dynamic random memory storage element automatically because of accepting this test command, and test result is back to this central processing unit.
2. the automatic test approach of dynamic random memory according to claim 1 is characterized in that, after described central processing unit is received this test result, can write down the fault block of this dynamic random memory storage element, and when access, keeps away this fault block.
3. the automatic test approach of dynamic random memory according to claim 1 is characterized in that, described dynamic random memory can be DRAM or DDR.
4. dynamic random memory with automatic test machine system can is characterized in that because of accepting the action that a certain test command that central processing unit assigns is tested automatically, comprising:
One dynamic random memory controller can be accepted the test command that this central processing unit is assigned;
One dynamic random memory storage element, be electrically connected to this dynamic random memory controller, this dynamic random memory controller can be tested automatically this dynamic random memory storage element, and test result is back to described central processing unit because of accepting test command.
5. the dynamic random memory with automatic test machine system according to claim 4, it is characterized in that, after described central processing unit is received this test result, can write down the fault block of this dynamic random memory storage element, and when access, kept away this fault block.
6. the dynamic random memory with automatic test machine system according to claim 4 is characterized in that described dynamic random memory can be DRAM or DDR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510059920 CN1841333A (en) | 2005-04-01 | 2005-04-01 | Dynamic random memory testing method and system thereof |
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| CN 200510059920 CN1841333A (en) | 2005-04-01 | 2005-04-01 | Dynamic random memory testing method and system thereof |
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| CN1841333A true CN1841333A (en) | 2006-10-04 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103699463A (en) * | 2012-09-28 | 2014-04-02 | 国际商业机器公司 | Memory test method and memory test system of server utilizing Xeon processor |
| US9406401B2 (en) | 2012-05-30 | 2016-08-02 | Industrial Technology Research Institute | 3-D memory and built-in self-test circuit thereof |
| CN108646980A (en) * | 2018-04-27 | 2018-10-12 | 江苏华存电子科技有限公司 | A method of efficiently using memory bandwidth |
-
2005
- 2005-04-01 CN CN 200510059920 patent/CN1841333A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9406401B2 (en) | 2012-05-30 | 2016-08-02 | Industrial Technology Research Institute | 3-D memory and built-in self-test circuit thereof |
| CN103699463A (en) * | 2012-09-28 | 2014-04-02 | 国际商业机器公司 | Memory test method and memory test system of server utilizing Xeon processor |
| CN103699463B (en) * | 2012-09-28 | 2017-12-05 | 联想企业解决方案(新加坡)有限公司 | Memory test method and system for server using Xeon processor |
| CN108646980A (en) * | 2018-04-27 | 2018-10-12 | 江苏华存电子科技有限公司 | A method of efficiently using memory bandwidth |
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