CN1819177A - 半导体器件的金属互连及其形成方法 - Google Patents
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- 239000010937 tungsten Substances 0.000 claims abstract description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 11
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Abstract
本发明公开了一种半导体器件的金属互连及其形成方法,其中,通过氮化层的“自阻止”功能避免过蚀刻和欠蚀刻,以防止铜互连中的断路和孔隙的发生,并获得恒定的沟道深度。该方法包括以下步骤:通过初步退火在半导体衬底上形成氮化膜,半导体衬底具有第一IMD膜和钨插头;在其上形成有氮化膜的半导体衬底上沉积第二IMD膜;在第二IMD膜上沉积光刻胶,并使光刻胶形成图样;利用形成图样的光刻胶蚀刻第二IMD膜,用于形成沟道;利用化学制品去除氮化膜;在从中去除了氮化物膜的沟道中沉积铜阻挡金属膜和铜晶种层,然后沉积铜;将其上沉积有铜的衬底二次退火;以及通过化学机械抛光使已二次退火的衬底平坦化。
Description
相关申请的交叉引用
本申请要求于2004年12月29日提交的第10-2004-0114635号韩国专利申请的优先权,其全部内容结合于此供参考。
技术领域
本发明涉及半导体器件中的金属互连(metal interconnection)及其形成方法,更具体地,涉及一种用于形成半导体器件的金属互连的方法,其中,在使用下部和上部内金属介电(inter-metaldielectric,IMD)膜的单大马士革工艺(damascene process,镶嵌工艺)中,很薄地沉积氮化层,并且当在上部IMD膜中形成沟道之前退火,以避免形成沟道时过蚀刻或欠蚀刻来获得恒定的沟道深度,从而防止铜互连中断路(open)和孔隙(void)的发生。
背景技术
半导体器件中的电互连通过使金属层形成图样而形成,该金属层通常由铜制成,以提高器件的操作速度。为了克服蚀刻困难,通常通过大马士革工艺形成金属互连,该工艺可以是双大马士革工艺或单大马士革工艺。
在双大马士革工艺中,使蚀刻阻止层(etch-stop layer)与IMD膜相堆叠,然后进行蚀刻,以在该堆叠的层中形成过孔(接触孔)和沟道。在所得到的结构的整个表面上(即,包括过孔和沟道的衬底上)顺序地形成扩散阻止层和晶种层(seed layer)。此处,铜互连的晶种层是Cu晶种层,于是扩散阻止层是铜阻挡金属膜。铜通过电镀沉积,然后通过例如化学机械抛光平坦化,以同时形成过孔中的过孔插头(via plug)和沟道中的铜互连。
然而,在铜沉积期间,下部晶体管可能会被铜原子通过接触孔的扩散而污染。因此,此情况下的电接触通过单大马士革工艺而形成,其中,首先用钨的沉积以填充过孔,然后仅在位于接触孔之上的沟道中形成铜互连。图1A和图1B示出了利用单大马士革工艺的用于形成半导体器件的金属互连的现有方法。
参照图1A和图1B,在形成于半导体衬底(未示出)上的第一IMD膜101上形成接触孔,以及将钨插头102填充该接触孔。在第一IMD膜101上沉积第二IMD膜103,以覆盖被填充的接触孔,然后进行选择性地蚀刻,以形成沟道,在该沟道中顺序地沉积铜阻挡金属膜104和铜105。
然而,该蚀刻以形成沟道可能会遭受欠蚀刻(图1A)或过蚀刻(图1B)。例如,在图1A所示的欠蚀刻中,在铜互连中存在断路,而在图1B的过蚀刻中,往往沿钨插头102的边缘发生铜阻挡金属膜104的过度沉积,因而生成悬挂物106,在该悬挂物之下可能生成孔隙107。铜互连中的断路和铜沉积物中的孔隙增大了金属互连的电阻,使器件性能下降。
发明内容
因此,本发明旨在提供一种半导体器件的金属互连及其形成方法,其很好地解决了由于相关技术的局限性和缺陷导致的一个或多个问题。
本发明的一个目的在于,提供一种用于形成半导体器件的金属互连的方法,其中,通过氮化层的“自阻止(sellf-stop)”功能避免过蚀刻和欠蚀刻,以防止铜互连中的断路和孔隙的发生。
本发明的又一个目的在于,提供了一种用于形成半导体器件的金属互连的方法,其实现了恒定的沟道深度。
本发明的又一个目的在于,提供了一种用于形成半导体器件的金属互连的方法,其实现了金属互连的均匀电阻。
本发明的其它优点、目的、和特征将在随后的说明中部分地阐述,并且,对于本领域的技术人员而言,部分地从说明书中变得显而易见,或者通过实施本发明而了解。本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
为获得根据本发明意图的这些目的和其他优点,如已概括和充分说明的,一种半导体器件的金属互连结构,包括:氮化膜,其通过初步退火形成于半导体衬底上,所述半导体衬底具有第一内金属介电膜和钨插头;第二内金属介电膜,沉积于其上形成有所述氮化膜的所述半导体衬底上;光刻胶,其沉积于所述第二内金属介电膜上,并被形成图样;其中,利用所述形成图样的光刻胶蚀刻所述第二内金属介电膜,用于形成沟道;利用化学制品去除所述氮化膜的预定部分;在从中去除了所述氮化物膜的所述预定部分的沟道中沉积铜阻挡金属膜和铜晶种层,然后沉积铜;将其上沉积有所述铜的所述衬底二次退火;以及通过化学机械抛光使所述已二次退火的衬底平坦化。
根据本发明的另一方面,提供了一种用于形成半导体器件的金属互连的方法。该方法包括以下步骤:通过初步退火(primaryannealing)在半导体衬底上形成氮化膜,所述半导体衬底具有第一IMD膜和钨插头;在其上形成有所述氮化膜的所述半导体衬底上沉积第二IMD膜;在所述第二IMD膜上沉积光刻胶,并使所述光刻胶形成图样;利用所述形成图样的光刻胶蚀刻所述第二IMD膜,用于形成沟道;利用化学制品去除氮化膜的预定部分;在从中去除了所述氮化物膜的所述预定部分的所述沟道中沉积铜阻挡金属膜和铜晶种层,然后沉积铜;将其上沉积有所述铜的所述衬底二次退火;以及通过化学机械抛光使所述已二次退火的衬底平坦化。
应该理解,以上对本发明的一般性描述和以下的详细描述都是示例性和说明性质的,目的在于对要求保护的本发明提供进一步的说明。
附图说明
附图构成本说明书的一部分,有助于进一步理解本发明,这些附图示出了本发明的一些实施例,并可与说明书一起用来说明本发明的原理。附图中:
图1A是根据现有方法形成的半导体器件的金属互连的剖视图,示出了欠蚀刻;
图1B是根据现有方法形成的半导体器件的金属互连的剖视图,示出了过蚀刻;以及
图2A和图2B是根据本发明的方法形成的半导体器件的金属互连的剖视图。
具体实施方式
以下将详细参照本发明的优选实施例,其实例在附图中示出。尽可能地,在所有附图中使用相同的参考标号表示相同或相似的部件。
参照图2,示出了根据本发明的用于形成半导体器件的金属互连的方法,在由硅形成于半导体衬底(未示出)上的第一IMD膜201中形成接触孔(未示出),并用钨插头202填充该接触孔。通过在氮环境下进行的初步退火而在第一IMD膜201上形成氮化层,从而形成氮化膜203和204;即,在第一IMD膜201的表面上形成氮化硅膜203,在钨插头202的表面上形成氮化钨膜204。
在沟道的蚀刻期间,氮化膜起到“自阻止”层的作用,但是,由于其高介电常数而减缓了器件的操作速度。因此优选地,通过退火(初步退火)很薄地形成氮化膜,以最小化其介电常数。优选地,以200℃到700℃之间的温度,利用快热处理或加热炉进行初步退火。氮气(N2)、无水氨(NH3)、或者下部层可用于氮化的材料可用作氮化层。
在具有氮化膜的衬底上沉积第二IMD膜205。然后在IMD膜205上沉积光刻胶,并形成用于沟道形成的图样,蚀刻第二IMD膜205,以形成沟道(未示出)。沟道的蚀刻在自阻止层处停止,暴露氮化膜的预定部分,接下来优选地利用H2SO4、H2O2、和NH3的混合物(coumpound)来去除该预定部分。
在沟道中沉积铜阻挡金属膜206和铜晶种层(未示出),其中,氮化膜是被从该沟道中去除的。然后,沉积铜207。通过二次退火和化学机械抛光完成半导体器件的金属互连。
再来参照图2,通过根据本发明的方法所形成的半导体器件的金属互连包括:氮化膜203和204,其通过初步退火形成于半导体衬底上,半导体衬底具有第一IMD膜201和钨插头202;第二IMD膜205,沉积于其上形成有氮化膜的半导体衬底上;光刻胶,其沉积于第二IMD膜上,并被形成图样;其中,利用形成图样的光刻胶蚀刻第二IMD膜,用于形成沟道;利用化学制品去除氮化膜的预定部分;在从中去除了氮化物膜的预定部分的沟道中沉积铜阻挡金属膜和铜晶种层,然后沉积铜207;将其上沉积有铜的衬底二次退火;以及通过化学机械抛光使已二次退火的衬底平坦化。
通过采用根据本发明的用于形成半导体器件的金属互连的方法,使得通过氮化膜的自阻止功能避免了过蚀刻或欠蚀刻,以防止金属互连中断路和孔隙的发生,并实现了由恒定的沟道深度导致的金属互连的均匀电阻。另外,由于通过退火很薄地形成氮化膜,所以可使氮化膜的介电常数最小化。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种半导体器件的金属互连,包括:
氮化膜,其通过初步退火形成于半导体衬底上,所述半导体衬底具有第一内金属介电膜和钨插头;
第二内金属介电膜,沉积于其上形成有所述氮化膜的所述半导体衬底上;
光刻胶,其沉积于所述第二内金属介电膜上,并被形成图样;其中,
利用所述形成图样的光刻胶蚀刻所述第二内金属介电膜,用于形成沟道;
利用化学制品去除所述氮化膜的预定部分;
在从中去除了所述氮化物膜的所述预定部分的沟道中沉积铜阻挡金属膜和铜晶种层,然后沉积铜;
将其上沉积有所述铜的所述衬底二次退火;以及
通过化学机械抛光使所述已二次退火的衬底平坦化。
2.根据权利要求1所述的金属互连,其中所述第一内金属介电膜由硅制成,其中,所述氮化膜是氮化硅膜和氮化钨膜。
3.根据权利要求1所述的金属互连,其中所述氮化膜利用N2、NH3、和下部层可用于氮化的材料中的任意一种形成。
4.根据权利要求1所述的金属互连,其中所述初步退火处理利用快热工艺和加热炉中的一种,以200℃到700℃之间的温度进行。
5.根据权利要求1所述的金属互连,其中所述化学制品是H2SO4、H2O2、和NH3的混合物。
6.一种用于形成半导体器件的金属互连的方法,包括以下步骤:
通过初步退火在半导体衬底上形成氮化膜,所述半导体衬底具有第一内金属介电膜和钨插头;
在其上形成有所述氮化膜的所述半导体衬底上沉积第二内金属介电膜;
在所述第二内金属介电膜上沉积光刻胶,并使所述光刻胶形成图样;
利用所述形成图样的光刻胶蚀刻所述第二内金属介电膜,用于形成沟道;
利用化学制品去除所述氮化膜的预定部分;
在从中去除了所述氮化物膜的所述预定部分的沟道中沉积铜阻挡金属膜和铜晶种层,然后沉积铜;
将其上沉积有所述铜的所述衬底二次退火;以及
通过化学机械抛光使所述已二次退火的衬底平坦化。
7.根据权利要求6所述的方法,其中所述第一内金属介电膜由硅制成,其中,所述氮化膜是氮化硅膜和氮化钨膜。
8.根据权利要求6所述的方法,其中所述氮化膜利用N2、NH3以及下部层可用于氮化的材料中的任意一种形成。
9.根据权利要求6所述的方法,其中所述初步退火处理利用快热工艺和加热炉中的一种,以200℃到700℃之间的温度进行。
10.根据权利要求6所述的方法,其中所述化学制品是H2SO4、H2O2、和NH3的混合物。
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