CN1808736A - Phase changeable memory cells and methods of forming the same - Google Patents

Phase changeable memory cells and methods of forming the same Download PDF

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Publication number
CN1808736A
CN1808736A CNA200510129743XA CN200510129743A CN1808736A CN 1808736 A CN1808736 A CN 1808736A CN A200510129743X A CNA200510129743X A CN A200510129743XA CN 200510129743 A CN200510129743 A CN 200510129743A CN 1808736 A CN1808736 A CN 1808736A
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layer
phase
interlayer dielectric
dielectric layer
change material
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CN100456513C (en
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李智惠
赵炳玉
赵性来
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8615—Hi-lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Abstract

A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug is in contact with a phase change material pattern disposed on the lower interlayer dielectric layer. The phase change material pattern and the lower interlayer dielectric layer are covered with an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern, which is disposed in a plate line contact hole passing through the upper interlayer dielectric layer.

Description

Phase-change memory cell and the method that forms it
Technical field
The present invention relates to a kind of semiconductor device and forming method thereof, more specifically, the present invention relates to phase-change memory cell and forming method thereof.
Background technology
Even non-volatile memory device also keeps the data that they are stored when their power supply is closed, so non-volatile memory device is used in conjunction with computer, mobile communication system, storage card etc. widely.For example, the widely used non-volatile memory device of a class is a flush memory device.Many flush memory devices have used the memory cell with laminated gate structure.The laminated gate structure of flush memory device generally includes tunnel oxidation layer, floating grid, gate dielectric layer and control grid electrode, and they are stacked gradually on channel region.In addition, for reliability and the programming efficiency that improves flash cell, should improve the film quality of tunnel oxidation layer and should increase the coupling ratio of flash cell.
Recently, the non-volatile memory device of other types, for example phase change memory device is used to replace flush memory device.The unit cell of phase change memory device generally includes switching device and is connected in series to the data storage elements of this switching device.The data storage elements of phase change memory device comprises: be electrically connected to switching device bottom electrode, be arranged at the phase-change material pattern on the bottom electrode and be arranged at the top electrode of phase-change material pattern.Generally, bottom electrode is as calandria.For example, when write current flow through switching device and bottom electrode, the interface between phase-change material pattern and bottom electrode produced the heat of measuring with Joule energy unit.The heat of measuring with Joule energy unit is amorphous state or crystalline state with the phase-change material pattern transition.
Fig. 1 is the cross-sectional view that the conventional phase-change memory cell of part is shown.
With reference to figure 1, following interlayer dielectric layer 3 is arranged on the Semiconductor substrate 1.Semiconductor substrate 1 is electrically connected to contact bolt 5, and this contact bolt 5 passes down interlayer dielectric layer 3.Contact bolt 5 is as bottom electrode.Phase-change material pattern 7 is layered in down covers bottom electrode 5 on the interlayer dielectric layer 3.In addition, the top surface of phase-change material pattern 7 contacts with top electrode 9.Top electrode 9 and 7 autoregistrations of phase-change material pattern are to have the width identical with phase-change material pattern 7.
Phase-change material pattern 7 can be formed by the sulfide material layer, such as GeSbTe layer (hereinafter to be referred as the GST layer).The GST layer easily reacts with conductive material layer, such as polysilicon (poly-Si) layer.For example, when the GST layer directly contacted with polysilicon layer, the silicon atom in the polysilicon layer infiltrated through the GST layer, has increased the resistance of GST layer thus.Therefore, reduced the characteristic of GST layer.Therefore, bottom electrode 5 that directly contacts with phase-change material pattern 7 and top electrode 9 are by not forming with the stable conductive layer of phase-change material pattern 7 reactions.For example, the metal nitride layer such as titanium nitride layer is widely used in forming bottom electrode 5 and top electrode 9.
In addition, interlayer dielectric layer 11 coverings are used on the whole surface with Semiconductor substrate 1 of top electrode 9.Printed line 13 is arranged on the interlayer dielectric layer 11 and by the printed line contact hole 11a that passes interlayer dielectric layer 11 and is electrically connected to top electrode 9.
In order to store desired data in the phase-change memory cell with phase-change material pattern 7, write current IW should flow through top electrode 9, phase-change material pattern 7 and bottom electrode 5.The part 7a of phase-change material pattern 7 contacts with bottom electrode 5, and can be changed into crystalline state or amorphous state according to the amount of write current IW.And the width of printed line contact hole 11a usually can be less than the width of top electrode 9.But, although can make above-mentioned variation, because top electrode 9 has the resistivity lower than phase-change material pattern 7, so write current IW will flow through the whole zone of top electrode 9 equably, as shown in Figure 1 to the phase-change memory cell of routine.Therefore, write current density in the body region of the phase-change material pattern 7 of above conventional phase-change memory cell is lower than the write current density at the interface between bottom electrode 5 and phase-change material pattern 7, has reduced the phase change efficiency in the body region of phase-change material pattern 7 of these conventional devices thus.
In the U.S. Patent No. 6 of the exercise question of authorizing Wu for " Self-Aligned Resistive Plugs for Forming MemoryCell with Phase Change Material (forming the self aligned resistance bolt of memory cell with phase-change material) ", another conventional phase-change memory cell is disclosed in 545,903.Phase-change memory cell described in the Wu patent comprise be separately positioned under the phase-change material layers and the top on the first high-resistance material layer and the second high-resistance material layer.In addition, self aligned each other first time resistance bolt and second time resistance bolt are arranged at respectively in the first and second high-resistance material layers.The first and second high-resistance material layers are formed by polysilicon or amorphous silicon (a-Si), thereby and by using ion implantation technology that foreign ion is injected high-resistance material layer formation autoregistration low resistance bolt.Therefore, the phase-change material layers of the phase-change memory cell described in the Wu patent directly contacts with silicon layer, and it has caused the phase-change material layers of memory element that should routine and interfacial characteristics instability between the silicon layer again.
Summary of the invention
In one exemplary embodiment of the present invention, provide phase-change memory cell.Phase-change memory cell comprises following interlayer dielectric layer that is formed on the Semiconductor substrate and the following conductive plugs of passing down the interlayer dielectric layer.The phase-change material pattern setting contacts on following interlayer dielectric layer and with following conductive plugs.Phase-change material pattern and following interlayer dielectric layer are used interlayer dielectric layer and are covered.The phase-change material pattern directly contacts with conductive layer by the printed line contact hole that passes the interlayer dielectric layer.
In another one exemplary embodiment of the present invention, provide phase-change memory cell.Phase-change memory cell comprises that the separator in the presumptive area that is formed at Semiconductor substrate defines the source region.Switching device is arranged at the active area place.Following interlayer dielectric layer is arranged on the substrate with switching device.Switching device is electrically connected to the following conductive plugs of passing down the interlayer dielectric layer.The phase-change material pattern setting contacts on following interlayer dielectric layer and with following conductive plugs.Phase-change material pattern and following interlayer dielectric layer are used interlayer dielectric layer and are covered.Printed line is arranged on the interlayer dielectric layer and by the printed line contact hole that passes the interlayer dielectric layer and directly contacts with the phase-change material pattern.
In another one exemplary embodiment of the present invention, provide phase-change memory cell.Phase-change memory cell comprises that the separator in the presumptive area that is formed at Semiconductor substrate defines the source region.Switching device is arranged at the active area place.Following interlayer dielectric layer is arranged on the substrate with switching device.Switching device is electrically connected to the following conductive plugs of passing down the interlayer dielectric layer.The phase-change material pattern setting contacts on following interlayer dielectric layer and with following conductive plugs.Phase-change material pattern and following interlayer dielectric layer are used interlayer dielectric layer and are covered.The phase-change material pattern directly contacts with last conductive plugs, and last conductive plugs is filled the printed line contact hole that passes the interlayer dielectric layer.Printed line is arranged on the interlayer dielectric layer and with printed line and is electrically connected to conductive plugs.
In another one exemplary embodiment, provide phase-change memory cell.Phase-change memory cell comprises following interlayer dielectric layer that is formed on the Semiconductor substrate and the following conductive plugs of passing down the interlayer dielectric layer.Bottom electrode and following interlayer dielectric layer cover with shape layer.The phase-change material pattern setting on shape layer and the phase-change material pattern contact with bottom electrode by the phase-change material contact hole that passes shape layer.Last interlayer dielectric layer is arranged on the substrate with phase-change material pattern.The phase-change material pattern is directly contacted with conductive layer pattern by the printed line contact hole that passes the interlayer dielectric layer.
In another one exemplary embodiment of the present invention, provide phase-change memory cell.Phase-change memory cell comprises that the separator in the presumptive area that is formed at Semiconductor substrate defines the source region.Switching device is arranged at the active area place.Following interlayer dielectric layer is arranged on the substrate with switching device.Switching device is electrically connected to the following conductive plugs of passing down the interlayer dielectric layer.Bottom electrode is arranged at down on the interlayer dielectric layer and bottom electrode contacts with following conductive plugs.Bottom electrode and following interlayer dielectric layer cover with shape layer.The phase-change material pattern setting on shape layer and the phase-change material pattern contact with bottom electrode by the phase-change material contact hole that passes shape layer.Last interlayer dielectric layer is arranged on the substrate with phase-change material pattern.Printed line is arranged on the interlayer dielectric layer and printed line directly contacts with the phase-change material pattern by the printed line contact hole that passes the interlayer dielectric layer.
In another one exemplary embodiment of the present invention, provide phase-change memory cell.Phase-change memory cell comprises that the separator in the presumptive area that is formed at Semiconductor substrate defines the source region.Switching device is arranged at the active area place.Following interlayer dielectric layer is arranged on the substrate with switching device.Switching device is electrically connected to the following conductive plugs of passing down the interlayer dielectric layer.Bottom electrode is arranged at down on the interlayer dielectric layer and bottom electrode contacts with following conductive plugs.Bottom electrode and following interlayer dielectric layer cover with shape layer.The phase-change material pattern setting on shape layer and the phase-change material pattern contact with bottom electrode by the phase-change material contact hole that passes shape layer.Last interlayer dielectric layer is arranged on the substrate with phase-change material pattern.The phase-change material pattern directly contacts with the last conductive plugs of filling the printed line contact hole that passes the interlayer dielectric layer.Printed line is arranged on the interlayer dielectric layer and with printed line and is electrically connected to conductive plugs.
In another one exemplary embodiment of the present invention, provide a kind of method that forms phase-change memory cell.The following conductive plugs that the interlayer dielectric layer was passed down in interlayer dielectric layer and formation under this method was included in and forms on the Semiconductor substrate.Forming the phase-change material pattern on the interlayer dielectric layer down.Form the phase-change material pattern and contact down conductive plugs.On phase-change material pattern and following interlayer dielectric layer, form the interlayer dielectric layer.The interlayer dielectric layer forms the printed line contact hole of the phase-change material pattern of expose portion on the composition.Forming conductive layer pattern comes directly to contact by the exposed portions of printed line contact hole with the phase-change material pattern.
In another one exemplary embodiment of the present invention, provide a kind of method that forms phase-change memory cell.The following conductive plugs that the interlayer dielectric layer was passed down in interlayer dielectric layer and formation under this method was included in and forms on the Semiconductor substrate.Forming bottom electrode with conductive plugs under contacting on the interlayer dielectric layer down.On bottom electrode and following interlayer dielectric layer, form shape layer.The composition shape layer forms the phase-change material contact hole that exposes bottom electrode.On shape layer, form the phase-change material pattern.Forming the phase-change material pattern contacts with bottom electrode by the phase-change material contact hole.Forming the interlayer dielectric layer on the substrate with phase-change material pattern.The interlayer dielectric layer forms the printed line contact hole of the phase-change material pattern of expose portion on the composition.Forming conductive layer pattern comes directly to contact by the exposed portions of printed line contact hole with the phase-change material pattern.
Description of drawings
Fig. 1 is the cross-sectional view of conventional phase-change memory cell.
Fig. 2 A is the cross-sectional view that illustrates according to a pair of phase-change memory cell of one exemplary embodiment of the present invention.
Fig. 2 B is the cross-sectional view that illustrates according to a pair of phase-change memory cell of one exemplary embodiment of the present invention.
Fig. 3 A is the cross-sectional view that illustrates according to the limited phase-change memory cell of one exemplary embodiment of the present invention.
Fig. 3 B is the cross-sectional view that illustrates according to the limited phase-change memory cell of one exemplary embodiment of the present invention.
Fig. 4 is the cross-sectional view that illustrates according to the formation method of the phase-change memory cell of one exemplary embodiment of the present invention to Fig. 8.
Fig. 9 illustrates conventional phase-change memory cell and according to the curve chart of the switching characteristic of the phase-change memory cell of one exemplary embodiment of the present invention.
Embodiment
With reference to the accompanying drawing that wherein shows embodiments of the invention one exemplary embodiment of the present invention is described more all sidedly thereafter.But the present invention can realize and should not be construed as being limited to the embodiment of explaination here with many different forms.In the accompanying drawings, for clear layer and the regional thickness exaggerated.Run through the identical reference marker of specification and be used to indicate components identical.
Fig. 2 A is the vertical cross-section view that illustrates according to the phase-change memory cell of one exemplary embodiment of the present invention, and Fig. 2 B is the vertical cross-section view that illustrates according to the phase-change memory cell of other one exemplary embodiment of the present invention.
With reference to figure 2A and 2B, the presumptive area that separator 23 is arranged at Semiconductor substrate 21 defines source region 23a.The first word line 27a is set and the second word line 27b strides across active area 23a.The first and second word line 27a and 27b are by gate dielectric 25 and active area 23a electric insulation.Common source region 29s is arranged among the active area 23a between the first and second word line 27a and the 27b.The first drain region 29d ' is arranged among the active area 23a, adjacent to the first word line 27a and common source region 29s setting relatively, the second drain region 29d " be arranged among the active area 23a, adjacent to the second word line 27b and common source region 29s setting relatively.Therefore, the first word line 27a is set strides across channel region between the first drain region 29d ' and the common source region 29s, and the second word line 27b is set comes across the second drain region 29d " and common source region 29s between channel region.The first word line 27a, common source region 29s and the first drain region 29d ' have constituted first switching device, the i.e. first access MOS transistor, and the second word line 27b, common source region 29s and the second drain region 29d " constituted second switch device, the i.e. second access MOS transistor.
In other one exemplary embodiment of the present invention, first and second switching devices can be respectively first bipolar transistor and second bipolar transistor.In this situation, the first and second word line 27a and 27b can be electrically connected to the base region of first and second bipolar transistors respectively.
Following interlayer dielectric layer 38 is arranged on the substrate with first and second switching devices.Bit line 35s is arranged at down in the interlayer dielectric layer 38.Bit line 35s is electrically connected to common source region 29s by source electrode contact bolt 33s.When plane graph was watched, bit line 35s can be provided with and be parallel to word line 27a and 27b.Perhaps, when plane graph was watched, bit line 35s can be provided with perpendicular to word line 27a and 27b.Simultaneously, when first and second switching devices are during as above-mentioned first and second bipolar transistors, bit line 35s can be electrically connected to the emitter region of first and second bipolar transistors.
The first drain region 29d ' can be electrically connected to down first in the interlayer dielectric layer 38 drain electrode contact bolt 33d ', and can be with the second drain region 29d " be electrically connected to down the contact bolt 33d that drains of second in the interlayer dielectric layer 38 ".The top surface of the first drain electrode contact bolt 33d ' can contact with the basal surface of the first drain pad 35d ' in the following interlayer dielectric layer 38, and the second contact bolt 33d that drains " top surface can with the second drain pad 35d in the following interlayer dielectric layer 38 " basal surface contact.In addition, the top surface of the first drain pad 35d ' can contact with the basal surface of first time conductive plugs 39a in first interlayer dielectric layer 38, and the second drain pad 35d " top surface can contact with the basal surface of second time conductive plugs 39b in first interlayer dielectric layer 38.The top surface of first and second times conductive plugs 39a and 39b has the level identical with the top surface of following interlayer dielectric layer 38.
When first and second switching devices are during as above-mentioned first and second bipolar transistors, first and second times conductive plugs 39a and 39b can be electrically connected to the collector region of first bipolar transistor and the collector region of second bipolar transistor respectively.
The first phase-change material pattern 41a and the second phase-change material pattern 41b are arranged at down on the interlayer dielectric layer 38.The first hard mask pattern 43a and the second hard mask pattern 43b can additionally be laminated in respectively on the first phase-change material pattern 41a and the second phase-change material pattern 41b.In this situation, the first and second hard mask pattern 43a and 43b respectively with the first and second phase- change material pattern 41a and 41b autoregistration.That is, the first hard mask pattern 43a can have the identical width with the first phase-change material pattern 41a, and the second hard mask pattern 43b can have the identical width with the second phase-change material pattern 41b.The first and second hard mask pattern 43a and 43b can be the material layers that has etching selectivity with respect to the first and second phase-change material pattern 41a and 41b.For example, the first and second hard mask pattern 43a and 43b can comprise and be selected from least a of silicon oxide layer, silicon nitride layer and insulating metal oxide layer.The insulating metal oxide layer can be alumina layer or titanium oxide layer.
As mentioned above, the top electrode that generally uses in conventional phase-change memory cell is not arranged on the phase- change material pattern 41a and 41b of phase-change memory cell of one exemplary embodiment of the present invention.The top electrode that uses in conventional phase-change memory cell can be formed by metal nitride layer usually, such as titanium nitride layer.But one of difficulty of conventional phase-change memory cell is because the adhesive force of the difference between top electrode and phase-change material pattern 41a and the 41b may be peeled off top electrode during technology subsequently.Attempting to remedy in the above difficulty, designing other conventional phase-change memory cells, wherein will insert between top electrode and phase-change material pattern 41a and the 41b such as the adhesion layer of titanium layer.Adhesion layer is set strengthens adhesive force between top electrode and phase-change material pattern 41a and the 41b.Yet, adopting these other conventional device, the metallic atom in the adhesion layer (for example, titanium atom) still can spread as phase- change material pattern 41a and 41b to reduce the characteristic of phase-change material pattern 41a and 41b.But, adopt the phase-change memory cell of one exemplary embodiment, can avoid the difficulty of above-mentioned conventional device, owing to do not use top electrode and adhesion layer for the device of one exemplary embodiment.
Refer again to one exemplary embodiment of the present invention, the first and second phase- change material pattern 41a and 41b are set to contact with 39b with first and second times conductive plugs 39a respectively.Therefore, preferably first and second times conductive plugs 39a and 39b by not forming with the electric conducting material of phase- change material pattern 41a and 41b reaction.For example, first and second times conductive plugs 39a and 39b can be metal level, metal nitride layer or metal silicide layer.More specifically, first and second times conductive plugs 39a and 39b can be by including but not limited to that following material constitutes: tungsten (W) layer, titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, molybdenum nitride (MoN) layer, niobium nitride (NbN) layer, silicon titanium nitride (TiSiN) layer, aluminium titanium nitride (TiAlN) layer, boron titanium nitride (TiBN) layer, silicon zirconium nitride (ZrSiN) layer, tungsten silicon nitride (WSiN) layer, boron tungsten nitride (WBN) layer, aluminium zirconium nitride (ZrAlN) layer, silicon molybdenum nitride (MoSiN) layer, aluminium molybdenum nitride (MoAlN) layer, silicon tantalum nitride (TaSiN) layer, aluminium tantalum nitride (TaAlN) layer, titanium (Ti) layer, molybdenum (Mo) layer, tantalum (Ta) layer, titanium silicide (TiSi) layer, tantalum silicide (TaSi) layer, titanium tungsten (TiW) layer, oxynitriding titanium (TiON) layer, alumina titanium nitride (TiAlON) layer, oxynitriding tungsten (WON) layer, tantalum nitride oxide (TaON) layer or copper (Cu) layer.
In addition, first and second times conductive plugs 39a and 39b can have the width less than the first and second phase-change material pattern 41a and 41b.That is, the following contact area between conductive plugs 39a and 39b and phase-change material pattern 41a and the 41b can be respectively less than the area of plane of phase-change material pattern 41a and 41b.Perhaps, following conductive plugs 39a can have the width identical with 41b with phase-change material pattern 41a with 39b.
Simultaneously, phase- change material pattern 41a and 41b can be for comprising the material layer of at least a chalcogen such as tellurium (Te) or selenium (Se).For example, phase- change material pattern 41a and 41b can be sulfurized layer, such as GeSbTe layer (hereinafter referred GST layer).
Last interlayer dielectric layer 45 is arranged on the substrate with hard mask pattern 43a and 43b.Last interlayer dielectric layer 45 can be for being widely used as the silicon oxide layer of conventional interlayer dielectric layer.The first phase-change material pattern 41a of part directly contacts with first conductive layer pattern by the first printed line contact hole 45a that penetrates interlayer dielectric layer 45.In addition, Bu Fen the second phase-change material pattern 41b directly contacts with second conductive layer pattern by the second printed line contact hole 45b that penetrates interlayer dielectric layer 45.For example, shown in Fig. 2 A, the first and second phase- change material pattern 41a and 41b can be respectively with pass interlayer dielectric layer 45 first on the conductive plugs 49a and second conductive plugs 49b directly contact.Conductive plugs 49a on first and second and 49b can be electrically connected to the printed line 51 that is arranged on the interlayer dielectric layer 45.In this situation, printed line 51 can be set across first and second word line 27a and the 27b, shown in Fig. 2 A.Perhaps, conductive plugs 49a on first and second and 49b can be electrically connected to first and second printed lines that are arranged on the interlayer dielectric layer 45 respectively.In this situation, first and second printed lines can be provided with to such an extent that be parallel to word line 27a and 27b, and bit line 35s can be provided with across word line 27a and 27b.
In other one exemplary embodiment of the present invention, the first and second phase- change material pattern 41a and 41b can with conductive layer pattern on being arranged at top electrode dielectric layer 45 promptly the printed line shown in Fig. 2 B 51 ' directly contact.In this situation, interlayer dielectric layer 45 is passed in printed line 51 ' extension.Perhaps, the first and second phase- change material pattern 41a and 41b can be respectively be arranged at interlayer dielectric layer 45 on first and second printed lines directly contact.In this situation, first and second printed lines can be provided with and be parallel to word line 27a and 27b, and bit line 35s can be provided with across word line 27a and 27b.
When the first and second hard mask pattern 43a and 43b being laminated in the first and second phase- change material pattern 41a and 41b respectively and going up, last conductive plugs (49a of Fig. 2 A and 49b) or bit line (Fig. 2 B 51 ') can penetrate hard mask pattern 43a and directly contact with 41b with phase-change material pattern 41a with last interlayer dielectric layer 45 with 43b.Contact area between last conductive plugs 49a and 49b and phase-change material pattern 41a and the 41b can be less than the area of plane of phase-change material pattern 41a and 41b.Similarly, the contact area between printed line 51 ' and phase-change material pattern 41a and the 41b can be less than the area of plane of phase- change material pattern 41a and 41b.
Shown in Fig. 2 A, insulation contact separator 47 can additionally be arranged between the sidewall of the sidewall of conductive plugs 49a and 49b and printed line contact hole 45a and 45b.In this situation, further reduced the contact area between last conductive plugs 49a and 49b and phase-change material pattern 41a and the 41b.Insulation contact separator 47 can be silicon nitride layer or silicon oxynitride layer.Similarly, insulation contact separator 47 can be arranged between the sidewall of printed line 51 ' and printed line contact hole 45a and 45b, shown in Fig. 2 B.
Preferably go up conductive plugs 49a and 49b by not forming, directly contact with 41b with phase-change material pattern 41a with 49b because go up conductive plugs 49a with the material layer of phase- change material pattern 41a and 41b reaction.For example, last conductive plugs 49a and 49b can be by including but not limited to that following material constitutes: tungsten (W) layer, titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, molybdenum nitride (MoN) layer, niobium nitride (NbN) layer, silicon titanium nitride (TiSiN) layer, aluminium titanium nitride (TiAlN) layer, boron titanium nitride (TiBN) layer, silicon zirconium nitride (ZrSiN) layer, tungsten silicon nitride (WSiN) layer, boron tungsten nitride (WBN) layer, aluminium zirconium nitride (ZrAlN) layer, silicon molybdenum nitride (MoSiN) layer, aluminium molybdenum nitride (MoAlN) layer, silicon tantalum nitride (TaSiN) layer, aluminium tantalum nitride (TaAlN) layer, titanium (Ti) layer, molybdenum (Mo) layer, tantalum (Ta) layer, titanium silicide (TiSi) layer, tantalum silicide (TaSi) layer, titanium tungsten (TiW) layer, oxynitriding titanium (TiON) layer, alumina titanium nitride (TiAlON) layer, oxynitriding tungsten (WON) layer, tantalum nitride oxide (TaON) layer or copper (Cu) layer.
As mentioned above, the basal surface of phase- change material pattern 41a and 41b directly contacts with 39b with following conductive plugs 39a, and in the situation of not inserting top electrode, the top surface of phase- change material pattern 41a and 41b directly contacts with 49b or printed line 51 ' with last conductive plugs 49a.The contact area between last conductive plugs 49a and 49b (or following conductive plugs 39a and 39b) and phase- change material pattern 41a and 41b, the contact area between printed line 51 ' and phase-change material pattern 41a and the 41b also can be less than the area of plane of phase-change material pattern 41a and 41b.Therefore, when write current IW ' flows through (for example, the first phase-change material pattern 41a) that is selected from phase- change material pattern 41a and 41b, compare with routine techniques, the density of the write current IW ' in the body region of the phase-change material pattern 41a of selection is increased.So, the phase change memory of this one exemplary embodiment but in the phase change efficiency (that is heating efficiency) of phase-change material pattern 41a of selection increased.In other words, adopt the phase-change memory cell of one exemplary embodiment of the present invention, compare with conventional phase-change memory cell, significantly increased the hear rate of the phase-change material pattern 41a that writes efficient and significantly reduced to select of memory cell, because under the situation of one exemplary embodiment, there is not to use top electrode with high heat conductance.
In the one exemplary embodiment shown in Fig. 2 A, be arranged on the sidewall of printed line contact hole 45a and 45b when insulation contacts spacer body 47, the contact area between last conductive plugs 49a and 49b and phase-change material pattern 41a and the 41b can be less than the contact area between following conductive plugs 39a and 39b and phase-change material pattern 41a and the 41b.In this situation, if write current IW ' flows through the first phase-change material pattern 41a, phase transformation occurs in the interface between the conductive plugs 49a and the first phase-change material pattern 41a on first.Similarly, in the one exemplary embodiment shown in Fig. 2 B, be arranged on the sidewall of printed line contact hole 45a and 45b when insulation contacts separator 47, the contact area between printed line 51 ' and printed line contact hole 45a and the 45b is less than the contact area between following conductive plugs 39a and 39b and phase-change material pattern 41a and the 41b.In this situation, if write current IW ' flows through the first phase-change material pattern 41a, phase transformation occurs between the printed line 51 ' and the first phase-change material pattern 41a at the interface so.
Above-mentioned one exemplary embodiment is applied to a last phase-change memory cell and from the axle phase-change memory cell.That is, the vertical center axis 45x ' of the first printed line contact hole 45a can be same as the vertical center axis 39x ' of first time conductive plugs 39a or from the vertical center axis 39x ' of first time conductive plugs 39a separately.Similarly, the vertical center axis 45x of the second printed line contact hole 45b " can be same as the vertical center axis 39x of second time conductive plugs 39b " or from the vertical center axis 39x of second time conductive plugs 39b " separately.
In addition, aforesaid one exemplary embodiment is applied to limited phase-change memory cell, shown in Fig. 3 A and 3B.
With reference to figure 3A and 3B, with reference to figure 2A and the described switching device of 2B, i.e. access MOS transistor or access bipolar transistor can be arranged at Semiconductor substrate 251 places.Following interlayer dielectric layer 253 is arranged on the substrate with switching device.Switching device is electrically connected to the following conductive plugs 259 of passing down interlayer dielectric layer 253.Following conductive plugs 259 can be with reference to figure 2A and 2B described conductive plugs 39a and 39b identical materials layer down.Bottom electrode 261 is arranged at down on the interlayer dielectric layer 253.Bottom electrode 261 is set covers down conductive plugs 259.That is, bottom electrode 261 is electrically connected to down conductive plugs 259.Bottom electrode 261 can be metal nitride layer, such as titanium nitride layer.
Bottom electrode 261 and following interlayer dielectric layer 253 usefulness shape layers 263 cover.Shape layer 263 can be insulating barrier, such as silicon oxide layer.Phase-change material pattern 265 is arranged on the shape layer 263, and phase-change material pattern 265 directly contacts with the bottom electrode 261 of part by the phase-change material contact hole 263h that penetrates shape layer 263.The vertical center axis 263x of phase-change material contact hole 263h can separate from the vertical center axis 259x of following conductive plugs 259, shown in Fig. 3 A and 3B.Perhaps, the vertical center axis 263x of phase-change material contact hole 263h can be identical with the vertical center axis 259x of following conductive plugs 259.
Last interlayer dielectric layer 267 is arranged on the substrate with phase-change material pattern 265.Hard mask pattern 266 can be arranged between phase-change material pattern 265 and the last interlayer dielectric layer 267.Hard mask pattern 266 can for with reference to figure 2A and described hard mask pattern 41a of 2B and 41b identical materials layer.The phase-change material pattern 265 of part directly contacts with conductive layer pattern by the printed line contact hole 267h that penetrates interlayer dielectric layer 267 and hard mask pattern 266.For example, phase-change material pattern 265 can directly contact with the last conductive plugs 271 that sees through last interlayer dielectric layer 267 and hard mask pattern 266, as shown in Figure 3A.Can be electrically connected to the printed line 273 that is arranged on the interlayer dielectric layer 267 with going up conductive plugs 271.Last conductive plugs 271 can for with reference to described conductive plugs 49a and the 49b identical materials layer gone up of figure 2A and 2B.
In other one exemplary embodiment of the present invention, phase-change material pattern 265 can directly contact with the conductive layer pattern on being arranged at interlayer dielectric layer 267.In other words, phase-change material pattern 265 can directly contact with the printed line 273 ' on being arranged at interlayer dielectric layer 267, shown in Fig. 3 B.In this situation, printed line 273 ' extension penetrates interlayer dielectric layer 267 and hard mask pattern 266.
The vertical center axis 267x of printed line contact hole 267h can separate from the vertical center axis 263x of phase-change material contact hole 263h.Perhaps, the vertical center axis 267x of printed line contact hole 267h can be identical with the vertical center axis 263x of phase-change material contact hole 263h.
Insulation contact separator 269 can additionally be arranged between the sidewall of the sidewall of conductive plugs 271 and printed line contact hole 267h.In this situation, further reduced the contact area between last conductive plugs 271 and the phase-change material pattern 265.Insulation contact separator 269 can be made of silicon nitride layer or silicon oxynitride layer.Similarly, insulation contact separator 269 can be arranged between the sidewall of printed line 273 ' and printed line contact hole 267h, shown in Fig. 3 B.
The method that forms phase-change memory cell according to one exemplary embodiment of the present invention now will be described.
Fig. 4 is the vertical cross-section view that illustrates according to the formation method of the phase-change memory cell shown in Figure 2 of one exemplary embodiment of the present invention to Fig. 8.
With reference to figure 4, in the predetermined zone of Semiconductor substrate 21, form separator 23 and define source region 23a.On active area 23a, form gate dielectric 25, and on substrate, form grid conducting layer with gate dielectric 25.This grid conducting layer of composition forms the first grid electrode 27a and the second gate electrode 27b, and they are parallel to each other and be provided with and be crossed with source region 23a.The first and second gate electrode 27a and 27b can extend with respectively as first and second word lines.
Use word line 27a and 27b and separator 23 as the ion injecting mask, foreign ion is injected with among the 23a of source region, form the common source region 29s and first and second drain region 29d ' and the 29d thus ".Form common source region 29s among the active area 23a between the first and second word line 27a and 27b.In addition, form the first drain region 29d ' in active area 23a, its adjacent and relative common source region 29s with the first word line 27a is provided with.In addition, in active area 23a, form the first drain region 29d ", its adjacent and relative common source region 29s with the second word line 27b is provided with.The first word line 27a, common source region 29s and the first drain region 29d ' have constituted first switching device, i.e. the first access MOS transistor.Similarly, the second word line 27b, common source region 29s and the second drain region 29d " constituted second switch device, the i.e. second access MOS transistor.In other one exemplary embodiment, can form the structure that first and second switching devices have bipolar transistor.On substrate, form first time interlayer dielectric layer 31 then with first and second switching devices.
With reference to figure 5, first time interlayer dielectric layer 31 of composition forms and exposes common source region 29s, the first drain region 29d ' and the second drain region 29d respectively " public source contact hole, first drain contact hole and second drain contact hole.Utilize conventional method in contact hole separately, form public source contact bolt 33s, first the drain electrode contact bolt 33d ' and second couple contact bolt 33d ".
Have contact bolt 33s, 33d ' and 33d " substrate on form conductive layer.This conductive layer of composition forms and covers public source contact bolt 33s, the first drain electrode contact bolt 33d ' and the second contact bolt 33d that drains respectively " bit line 35s, the first drain pad 35d ' and the second drain pad 35d ".Bit line 35s be can form and word line 27a and 27b are parallel to.Perhaps, can form bit line 35s across word line 27a and 27b.Have the bit line 35s and first and second drain pad 35d ' and the 35d " substrate on form second time interlayer dielectric layer 37.First and second times interlayer dielectric layers 31 and 37 have constituted time interlayer dielectric layer 38.
With reference to figure 6, second time interlayer dielectric layer 37 of composition forms and exposes first and second drain pad 35d ' and the 35d respectively " first and second storage node contact holes.In first and second storage node contact holes, form first time conductive plugs 39a and second time conductive plugs 39b respectively.On substrate, form phase-change material layers 41 then with following conductive plugs 39a and 39b.Phase-change material layers 41 can be formed by the material layer that comprises at least a chalcogen such as tellurium (Te) or selenium (Se).For example, phase-change material layers 41 can be formed by sulfurized layer, such as the GST layer.In this situation, following conductive plugs 39a directly contacts with phase-change material layers 41 with 39b.Therefore, following conductive plugs 39a and 39b can be by not forming with the electric conducting material of phase-change material pattern 41 reactions.For example, following conductive plugs 39a and 39b can be by including but not limited to that following material forms: tungsten (W) layer, titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, molybdenum nitride (MoN) layer, niobium nitride (NbN) layer, silicon titanium nitride (TiSiN) layer, aluminium titanium nitride (TiAlN) layer, boron titanium nitride (TiBN) layer, silicon zirconium nitride (ZrSiN) layer, tungsten silicon nitride (WSiN) layer, boron tungsten nitride (WBN) layer, aluminium zirconium nitride (ZrAlN) layer, silicon molybdenum nitride (MoSiN) layer, aluminium molybdenum nitride (MoAlN) layer, silicon tantalum nitride (TaSiN) layer, aluminium tantalum nitride (TaAlN) layer, titanium (Ti) layer, molybdenum (Mo) layer, tantalum (Ta) layer, titanium silicide (TiSi) layer, tantalum silicide (TaSi) layer, titanium tungsten (TiW) layer, oxynitriding titanium (TiON) layer, alumina titanium nitride (TiAlON) layer, oxynitriding tungsten (WON) layer, tantalum nitride oxide (TaON) layer or copper (Cu) layer.
On phase-change material layers 41, can be additionally formed hard mask layer.This hard mask layer can be formed by the insulating barrier that has etching selectivity with respect to phase-change material layers 41.For example, hard mask layer can be by comprising that at least a material layer that is selected from silicon oxide layer, silicon nitride layer and insulating metal oxide layer forms.Silicon oxide layer can be formed by tetraethyl orthosilicate (TEOS) layer, and metal oxide layer can be formed by alumina layer or titanium oxide layer.The composition hard mask layer comes respectively to form the first hard mask pattern 43a and the second hard mask pattern 43b above first and second times conductive plugs 39a and 39b.
With reference to figure 7, use hard mask pattern 43a and 43b to come etching phase-change material layers 41 as etching mask, form the first phase-change material pattern 41a and the second phase-change material pattern 41b thus, it directly contacts with 39b with first and second times conductive plugs 39a respectively.Perhaps, use photoetching process and do not use hard mask pattern 43a and 43b, can form phase- change material pattern 41a and 41b.
Forming interlayer dielectric layer 45 on the substrate with hard mask pattern 43a and 43b.Last interlayer dielectric layer 45 can be formed by silicon oxide layer.Interlayer dielectric layer 45 forms the first printed line contact hole 45a and the second printed line contact hole 45b that exposes the first and second phase- change material pattern 41a and 41b respectively with hard mask pattern 43a and 43b on the composition.Can form the first printed line contact hole 45a to have the vertical center axis that separates from the vertical center axis of first time conductive plugs 39a.Similarly, can form the second printed line contact hole 45b to have the vertical center axis that separates from the vertical center axis of second time conductive plugs 39a.
During the etch process that is used to form printed line contact hole 45a and 45b, may cause etch damage to the first and second phase-change material pattern 41a and 41b.When the etch damage that is caused is serious, can reduce the characteristic of phase-change material pattern 41a and 41b.Therefore, preferably use the etch recipe that can minimize the etch damage that is applied to phase- change material pattern 41a and 41b to carry out the etch process that forms printed line contact hole 45a and 45b.In order to minimize etch damage, the etch process performance that preferably forms printed line contact hole 45a and 45b is at least 5 high etch-selectivity.In other words, the etch-rate of preferably going up interlayer dielectric layer 45 and hard mask pattern 43a and 43b is 5 times of etch-rate of phase- change material pattern 41a and 41b.
In one exemplary embodiment of the present invention, as last interlayer dielectric layer 45 and hard mask pattern 43a with 43b is formed by silicon oxide layer and phase- change material pattern 41a and 41b when being formed by the GST layer, under 10 to 100mTorr pressure, use C xH yF zFirst main etching gas and the C of system vF wThe second main etching gas of system can be carried out the etch process that forms printed line contact hole 45a and 45b.In addition, can use 300 to 1000W plasma power to carry out etch process.In these one exemplary embodiment, the first main etching gas can be CHF 3Gas, CH 2F 2Gas or CH 3F gas, and the second main etching gas can be CF 4Gas, C 4F 6Gas, C 4F 8Gas or C 5F 8Gas.In addition, except the first and second main etching gas, can also adopt argon (Ar) gas, nitrogen (N 2) gas and oxygen (O 2) at least a etch process of carrying out of gas.In this case, the overall flow rate of the first and second main etching gas can be at least 10% of the overall flow rate of employed all gas in the etch process.
With reference to figure 8, on substrate, form conductive layer, and eat-back the top surface that conductive layer exposes interlayer dielectric layer 45 with printed line contact hole 45a and 45b.Therefore, in the first and second printed line contact hole 45a and 45b, form on first conductive plugs 49b on the conductive plugs 49a and second respectively.Form on first and second conductive plugs 49a and 49b directly to contact with 41b with the first and second phase-change material pattern 41a respectively.Therefore, last conductive plugs 49a and 49b also can be by not forming with the conductive layer of phase-change material pattern 41a and 41b reaction.For example, last conductive plugs 49a and 49b can be by including but not limited to that following material forms: tungsten (W) layer, titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, molybdenum nitride (MoN) layer, niobium nitride (NbN) layer, silicon titanium nitride (TiSiN) layer, aluminium titanium nitride (TiAlN) layer, boron titanium nitride (TiBN) layer, silicon zirconium nitride (ZrSiN) layer, tungsten silicon nitride (WSiN) layer, boron tungsten nitride (WBN) layer, aluminium zirconium nitride (ZrAlN) layer, silicon molybdenum nitride (MoSiN) layer, aluminium molybdenum nitride (MoAlN) layer, silicon tantalum nitride (TaSiN) layer, aluminium tantalum nitride (TaAlN) layer, titanium (Ti) layer, molybdenum (Mo) layer, tantalum (Ta) layer, titanium silicide (TiSi) layer, tantalum silicide (TaSi) layer, titanium tungsten (TiW) layer, oxynitriding titanium (TiON) layer, alumina titanium nitride (TiAlON) layer, oxynitriding tungsten (WON) layer, tantalum nitride oxide (TaON) layer or copper (Cu) layer.
In other one exemplary embodiment of the present invention, before the conductive layer of conductive plugs 49a and 49b in the deposition formation first and second, can on the sidewall of printed line contact hole 45a and 45b, form insulation and contacting separator 47.Insulation contact separator 47 can be formed by silicon nitride layer or silicon oxynitride layer.
Subsequently, on having, form flaggy on the substrate of conductive plugs 49a and 49b, and this flaggy of composition forms the printed line 51 that is electrically connected to conductive plugs 49a and 49b on first and second.
In another one exemplary embodiment, can omit and form the technology that goes up conductive plugs 49a and 49b.In this situation, form printed line 51 and directly contact with 41b with the first and second phase-change material pattern 41a with 45b by printed line contact hole 45a.
With reference to Fig. 3 A and 3B the method that one exemplary embodiment according to the present invention forms limited phase-change memory cell is described.
Refer again to Fig. 3 A and 3B, form switching device at Semiconductor substrate 251 places.Use and can form switching device with reference to figure 4 described similar modes.Have on the substrate of this switching device form under interlayer dielectric layer 253.Conductive plugs 259 is passed down interlayer dielectric layer 253 under forming.To descend conductive plugs 259 to be electrically connected to this switching device.Forming bottom electrode 261 on the interlayer dielectric layer 253 down.Form bottom electrode 261 to contact with following conductive plugs 259.On substrate, form shape layer 263 with bottom electrode 261.Shape layer 263 can be formed by insulating barrier, such as silicon oxide layer.
Composition shape layer 263 forms the phase-change material contact hole 263h of the bottom electrode 261 of expose portion.Can form phase-change material contact hole 263h to have the vertical center axis 263x that separates from the vertical center axis 259x of following conductive plugs 259.On shape layer 263, form phase-change material pattern 265 to fill phase-change material contact hole 263h.In addition, on phase-change material pattern 265, can also form hard mask pattern 266.Can be to form hard mask pattern 266 and phase-change material pattern 265 with 7 above-mentioned identical modes with reference to figure 6.And, forming interlayer dielectric layer 267 on the substrate with hard mask pattern 266.
Interlayer dielectric layer 267 and hard mask pattern 265 form the printed line contact hole 267h of the phase-change material pattern 265 of expose portion on the composition.Use can be carried out the etch process that forms printed line contact hole 267h with reference to figure 7 described etch recipe.Can form printed line contact hole 267h to have the vertical center axis 267x that separates from the vertical center axis 263x of phase-change material contact hole 263h.On the sidewall of printed line contact hole 267h, can form insulation contact separator 269.Insulation contact separator 269 can be formed by insulating barrier, forms such as silicon oxide layer and silicon oxynitride layer.Formation is gone up conductive plugs 271 and is filled printed line contact hole 267h then.Use the method for conductive plugs 49a and 49b in the formation shown in Figure 8, can form conductive plugs 271.Therefore, form phase-change material pattern 265 directly to contact with the last conductive plugs 271 of passing interlayer dielectric layer 267 and hard mask pattern 266.On last interlayer dielectric layer 267, form printed line 273 then.Can form printed line 273 and cover conductive plugs 271.
In other one exemplary embodiment of the present invention, can omit and form the technology that goes up conductive plugs 271.In this situation, on last interlayer dielectric layer 267, form the printed line 273 ' that directly contacts with phase-change material pattern 265, shown in Fig. 3 B.
[example]
Fig. 9 illustrates conventional phase-change memory cell and according to the curve chart of the switching characteristic of the phase-change memory cell of one exemplary embodiment of the present invention.In Fig. 9, transverse axis indication is applied to writes voltage Vw between the last conductive plugs of each data storage elements and the following conductive plugs, and the longitudinal axis is indicated the resistance R of each data storage elements.And, in Fig. 9, by the data of reference marker 101 indication programming characteristic corresponding to the routine data memory element, and by the data of the reference marker 103 indications programming characteristic corresponding to the data storage elements of one exemplary embodiment of the present invention.
Use the process conditions manufacturing described in the following table I to present the data storage elements of the measurement result of Fig. 9.
For above-mentioned routine data memory element, form top electrode to have the width (diameter) identical with the phase-change material pattern.That is, with top electrode and the autoregistration of phase-change material pattern.In this situation, conductive plugs contacts top electrode in the formation.
But for the data storage elements according to one exemplary embodiment of the present invention, hard mask pattern is formed by silica (SiO) layer, and with hard mask pattern and the autoregistration of phase-change material pattern.That is, form hard mask pattern to have the width (diameter) identical with the phase-change material pattern.In this situation, conductive plugs penetrates hard mask pattern in the formation.In other words, conductive plugs directly contacts with the phase-change material pattern in the formation.
Table I
Routine techniques The present invention
Following conductive plugs Material The TiN layer The TiN layer
Diameter 55nm 55nm
The phase-change material pattern Material The GST layer The GST layer
Diameter 680nm 680nm
Thickness 100nm 100nm
Top electrode The TiN layer -
Hard mask pattern The SiO layer The SiO layer
Last interlayer dielectric layer The SiO layer The SiO layer
Last conductive plugs Material The W layer The W layer
Diameter 240nm 240nm
In addition, in manufacturing according to the data storage elements of one exemplary embodiment of the present invention, thereby by using interlayer dielectric layer and hard mask pattern on the continuous composition of oxide etching process to form the printed line contact hole of the phase-change material pattern of expose portion.Under the plasma power of the pressure of 10mTorr and 500W, use magnetic intensified response ion(ic) etching (MERIE) equipment to carry out oxide etching process.In this situation, use CHF 3Gas and CF 4Gas is as main etching gas, and CHF 3Gas and CF 4The flow velocity of gas is respectively 40sccm and 10sccm.
In Fig. 9, the voltage Vw that writes at each data point place is applied to data storage elements and continues 500ns (nanosecond).
With reference to figure 9, conventional data storage elements continues to present about 1 * 10 after the 500ns at the voltage Vw that writes that applies about 0.5V 4Ohm resistance is set, and conventional data storage elements apply about 1.2V write the lasting 500ns of voltage Vw after present about 1 * 10 6The replacement resistance of ohm.
Simultaneously, the data storage elements of one exemplary embodiment of the present invention continues to present about 1 * 10 after the 500ns at the low voltage Vw that writes that applies about 0.3V 4Ohm resistance is set, and data storage elements of the present invention lowly presents about 4 * 10 after writing the lasting 500ns of voltage Vw what apply about 1.1V 6The height replacement resistance of ohm.
In a word, compare, present low relatively setting/reset voltage and relative high replacement resistance according to the data storage elements of one exemplary embodiment of the present invention with the routine data memory element.
According to aforesaid one exemplary embodiment of the present invention, the phase-change material pattern is directly contacted with printed line with the last conductive plugs that penetrates the interlayer dielectric layer, and do not insert top electrode.Therefore, increase the write current density of body region of the phase-change material pattern of the phase-change memory cell that flows through one exemplary embodiment, also improved the efficient of writing of phase-change memory cell thus.
Though described one exemplary embodiment of the present invention, yet can notice under situation about not breaking away from and to make various modifications here by the spirit and scope of the present invention that scope defined of claim.
The application requires in the rights and interests of the korean patent application No.10-2004-0101999 of submission on December 6th, 2004, and its full content is incorporated in this as a reference.

Claims (43)

1, a kind of phase-change memory cell comprises:
Following interlayer dielectric layer is formed on the Semiconductor substrate;
Following conductive plugs is passed described interlayer dielectric layer down;
The phase-change material pattern is arranged on the described interlayer dielectric layer down to contact described conductive plugs down;
Last interlayer dielectric layer covers described phase-change material pattern and following interlayer dielectric layer; With
Conductive layer pattern is provided with by passing the described printed line contact hole of going up the interlayer dielectric layer directly to contact with described phase-change material pattern.
2, phase change memory device according to claim 1, wherein, the width of described conductive plugs down is less than the width of described phase-change material pattern.
3, phase change memory device according to claim 1 also comprises the insulation contact separator that is arranged between described conductive layer pattern and the described printed line contact hole.
4, phase change memory device according to claim 1 also comprises the hard mask pattern between the top surface that is arranged at described upward interlayer dielectric layer and described phase-change material pattern,
Wherein, described conductive layer pattern penetrates described interlayer dielectric layer and the described hard mask pattern gone up.
5, phase change memory device according to claim 4, wherein, described hard mask pattern comprises and is selected from least a in silicon oxide layer, silicon nitride layer and the insulating metal oxide layer.
6, phase change memory device according to claim 1, wherein, the vertical center axis that the vertical center axis that described conductive plugs down has the conductive layer pattern from described printed line contact hole separates.
7, a kind of phase-change memory cell comprises:
Separator is formed in the presumptive area of Semiconductor substrate and defines the source region;
Switching device is formed in the described active area;
Following interlayer dielectric layer is formed on the substrate with described switching device;
Following conductive plugs penetrates described interlayer dielectric layer down, and described conductive plugs down is electrically connected to described switching device;
The phase-change material pattern is arranged on the described interlayer dielectric layer down, contacts with described conductive plugs down;
Last interlayer dielectric layer covers described phase-change material pattern and described interlayer dielectric layer down; And
Printed line is arranged at described going up on the interlayer dielectric layer, directly contacts with described phase-change material pattern by passing the described printed line contact hole of going up the interlayer dielectric layer.
8, phase change memory device according to claim 7 also comprises the insulation contact separator between the sidewall of the printed line that is arranged in the described printed line contact hole and described printed line contact hole.
9, phase change memory device according to claim 7 also comprises the hard mask pattern between the top surface that is arranged at described upward interlayer dielectric layer and described phase-change material pattern,
Wherein, described printed line penetrates described interlayer dielectric layer and the described hard mask pattern gone up.
10, phase change memory device according to claim 9, wherein, described hard mask pattern comprises and is selected from least a in silicon oxide layer, silicon nitride layer and the insulating metal oxide layer.
11, phase change memory device according to claim 7 also comprises:
Last conductive plugs, filling penetrate the described printed line contact hole of described upward interlayer dielectric layer and directly contact with described phase-change material pattern.
12, phase change memory device according to claim 11 also comprises the insulation contact separator between the sidewall that is arranged at described printed line contact hole and the described sidewall of going up conductive plugs.
13, phase change memory device according to claim 11 also comprises the hard mask pattern between the top surface that is arranged at described upward interlayer dielectric layer and described phase-change material pattern,
Wherein, the described conductive plugs that goes up penetrates described interlayer dielectric layer and the described hard mask pattern gone up.
14, phase change memory device according to claim 11, wherein, the described conductive plugs that goes up is by being selected from tungsten layer, titanium nitride layer, tantalum nitride layer, tungsten nitride layer, the nitrogenize molybdenum layer, niobium nitride layer, the silicon titanium nitride layer, the aluminium titanium nitride layer, the boron titanium nitride layer, the silicon zirconium nitride layer, the tungsten silicon nitride layer, the boron tungsten nitride layer, the aluminium zirconium nitride layer, silicon nitrogenize molybdenum layer, aluminium nitrogenize molybdenum layer, the silicon tantalum nitride layer, the aluminium tantalum nitride layer, titanium layer, molybdenum layer, tantalum layer, titanium silicide layer, the silication tantalum layer, titanium tungsten layer, the oxynitriding titanium layer, the alumina titanium nitride layer, the oxynitriding tungsten layer, a kind of formation of oxynitriding tantalum layer or copper layer.
15, a kind of phase-change memory cell comprises:
Following interlayer dielectric layer is formed on the Semiconductor substrate;
Following conductive plugs is passed described interlayer dielectric layer down;
Bottom electrode is arranged on the described interlayer dielectric layer down, contacts with described conductive plugs down;
Shape layer covers described bottom electrode and described interlayer dielectric layer down;
The phase-change material pattern is formed on the described shape layer, and described phase-change material pattern contacts with described bottom electrode by the phase-change material contact hole that passes described shape layer;
Last interlayer dielectric layer is formed on the substrate with described phase-change material pattern; And
Conductive layer pattern directly contacts with described phase-change material pattern by passing the described printed line contact hole of going up the interlayer dielectric layer.
16, phase change memory device according to claim 15 also comprises the sidewall and the contact of the insulation between the conductive layer pattern in the described printed line contact hole separator that are arranged at described printed line contact hole.
17, phase change memory device according to claim 15 also comprises being arranged at described phase-change material pattern and the described hard mask pattern of going up between the interlayer dielectric layer,
Wherein, described conductive layer pattern penetrates described interlayer dielectric layer and the described hard mask pattern gone up.
18, a kind of phase-change memory cell comprises:
Separator is formed in the presumptive area of Semiconductor substrate and defines the source region;
Switching device is formed in the described active area;
Following interlayer dielectric layer is formed on the substrate with described switching device;
Following conductive plugs penetrates described interlayer dielectric layer down, and described conductive plugs down is electrically connected to described switching device;
Bottom electrode is arranged on the described interlayer dielectric layer down, contacts with described conductive plugs down;
Shape layer covers described bottom electrode and following interlayer dielectric layer;
The phase-change material pattern is formed on the described shape layer, and described phase-change material pattern contacts with described bottom electrode by the phase-change material contact hole that penetrates described shape layer;
Last interlayer dielectric layer is formed on the substrate with described phase-change material pattern;
Printed line is arranged at described going up on the interlayer dielectric layer, directly contacts with described phase-change material pattern by penetrating the described printed line contact hole of going up the interlayer dielectric layer.
19, phase change memory device according to claim 18 also comprises the insulation contact separator between the sidewall of the printed line that is arranged at described printed line contact hole and described printed line contact hole.
20, phase change memory device according to claim 18 also comprises being arranged at described phase-change material pattern and the described hard mask pattern of going up between the interlayer dielectric layer,
Wherein, described printed line penetrates described interlayer dielectric layer and the described hard mask pattern gone up.
21, phase change memory device according to claim 18 also comprises:
Last conductive plugs, filling penetrate the described printed line contact hole of described upward interlayer dielectric layer and directly contact with described phase-change material pattern.
22, phase change memory device according to claim 21 also comprises the insulation contact separator between the sidewall that is arranged at described printed line contact hole and the described sidewall of going up conductive plugs.
23, phase change memory device according to claim 21 also comprises being arranged at described phase-change material pattern and the described hard mask pattern of going up between the interlayer dielectric layer,
Wherein, the described conductive plugs that goes up penetrates described interlayer dielectric layer and the described hard mask pattern gone up.
24, phase change memory device according to claim 21, wherein, the described conductive plugs that goes up is by being selected from tungsten layer, titanium nitride layer, tantalum nitride layer, tungsten nitride layer, the nitrogenize molybdenum layer, niobium nitride layer, the silicon titanium nitride layer, the aluminium titanium nitride layer, the boron titanium nitride layer, the silicon zirconium nitride layer, the tungsten silicon nitride layer, the boron tungsten nitride layer, the aluminium zirconium nitride layer, silicon nitrogenize molybdenum layer, aluminium nitrogenize molybdenum layer, the silicon tantalum nitride layer, the aluminium tantalum nitride layer, titanium layer, molybdenum layer, tantalum layer, titanium silicide layer, the silication tantalum layer, titanium tungsten layer, the oxynitriding titanium layer, the alumina titanium nitride layer, the oxynitriding tungsten layer, a kind of formation of oxynitriding tantalum layer or copper layer.
25, a kind of method that forms phase-change memory cell, described method comprises:
Interlayer dielectric layer under forming on the Semiconductor substrate;
The described following conductive plugs of interlayer dielectric layer is down passed in formation;
Form the phase-change material pattern on described interlayer dielectric layer down, described phase-change material pattern contacts with described conductive plugs down;
The interlayer dielectric layer covers described phase-change material pattern and described interlayer dielectric layer down in the formation;
The described upward interlayer dielectric layer of composition forms the printed line contact hole of the described phase-change material pattern of expose portion; And
Forming conductive layer pattern comes directly to contact with the exposed portions of described phase-change material pattern by described printed line contact hole.
26, method according to claim 25 also comprises:
In the predetermined zone of described Semiconductor substrate, form separator and define the source region, before forming described interlayer dielectric layer down, form described separator; And
On described active area, form switching device,
Wherein, described conductive plugs down is electrically connected to described switching device.
27, method according to claim 25 also is included in and forms described going up before the interlayer dielectric layer, on described phase-change material pattern, forms and the self aligned hard mask pattern of described phase-change material pattern,
Wherein, form described printed line contact hole and penetrate described interlayer dielectric layer and the described hard mask pattern gone up.
28, method according to claim 25 also is included in and forms insulation contact separator on the sidewall of described printed line contact hole.
29, method according to claim 25 wherein, forms described conductive layer pattern and comprises:
Form flaggy, described flaggy is filled described printed line contact hole and is covered the described interlayer dielectric layer of going up; And
The described flaggy of composition forms the printed line that covers described printed line contact hole.
30, method according to claim 25 wherein, forms described conductive layer pattern and comprises:
Conductive plugs in the formation, described upward conductive plugs is filled described printed line contact hole and is directly contacted with the exposed portions of described phase-change material pattern;
Form flaggy and cover described conductive plugs and the described interlayer dielectric layer of going up gone up; And
The described flaggy of composition forms and is electrically connected to the described printed line of going up conductive plugs.
31, method according to claim 30, wherein, the described conductive plugs that goes up is by being selected from tungsten layer, titanium nitride layer, tantalum nitride layer, tungsten nitride layer, the nitrogenize molybdenum layer, niobium nitride layer, the silicon titanium nitride layer, the aluminium titanium nitride layer, the boron titanium nitride layer, the silicon zirconium nitride layer, the tungsten silicon nitride layer, the boron tungsten nitride layer, the aluminium zirconium nitride layer, silicon nitrogenize molybdenum layer, aluminium nitrogenize molybdenum layer, the silicon tantalum nitride layer, the aluminium tantalum nitride layer, titanium layer, molybdenum layer, tantalum layer, titanium silicide layer, the silication tantalum layer, titanium tungsten layer, the oxynitriding titanium layer, the alumina titanium nitride layer, the oxynitriding tungsten layer, a kind of formation of oxynitriding tantalum layer or copper layer.
32, method according to claim 25, wherein, when the described interlayer dielectric layer of going up is formed by silicon oxide layer, by using C xH yF zFirst main etching gas and the C of system vF wThe second main etching gas of system comes the described interlayer dielectric layer of going up of etching to form described printed line contact hole as main etching gas.
33, method according to claim 25 wherein, forms described printed line contact hole to have the vertical center axis that separates from the described vertical center axis of conductive plugs down.
34, a kind of method that forms phase-change memory cell, described method comprises:
Interlayer dielectric layer under forming on the Semiconductor substrate;
The described following conductive plugs of interlayer dielectric layer is down passed in formation;
Form bottom electrode on the interlayer dielectric layer down described, described bottom electrode contacts with described conductive plugs down;
Form shape layer and cover described bottom electrode and following interlayer dielectric layer;
The described shape layer of composition forms the phase-change material contact hole that exposes described bottom electrode;
On described shape layer, form the phase-change material pattern, form described phase-change material pattern and contact with described bottom electrode by described phase-change material contact hole;
Forming the interlayer dielectric layer on the substrate with described phase-change material pattern;
The described interlayer dielectric layer of going up of composition forms the printed line contact hole that exposes described phase-change material pattern;
Form conductive layer pattern, described conductive layer pattern directly contacts with described phase-change material pattern by described printed line contact hole.
35, method according to claim 34 also is included in and forms described going up before the interlayer dielectric layer, forms hard mask pattern on described phase-change material pattern, described hard mask pattern and the autoregistration of described phase-change material pattern,
Wherein, form described printed line contact hole and penetrate described interlayer dielectric layer and the described hard mask pattern gone up.
36, method according to claim 34 also is included in and forms insulation contact separator on the sidewall of described printed line contact hole.
37, method according to claim 36, wherein, described insulation contact separator is formed by silicon nitride layer or silicon oxynitride layer.
38, method according to claim 34 wherein, forms described conductive layer pattern and comprises:
Form flaggy, described flaggy is filled described printed line contact hole and is covered the described interlayer dielectric layer of going up; And
The described flaggy of composition forms the printed line that covers described printed line contact hole.
39, method according to claim 34 wherein, forms described conductive layer pattern and comprises:
Conductive plugs in the formation, described upward conductive plugs is filled described printed line contact hole and is directly contacted with the exposed portions of described phase-change material pattern;
Form flaggy and cover described conductive plugs and the described interlayer dielectric layer of going up gone up; And
The described flaggy of composition forms and is electrically connected to the described printed line of going up conductive plugs.
40, according to the described method of claim 39, wherein, the described conductive plugs that goes up is by being selected from tungsten layer, titanium nitride layer, tantalum nitride layer, tungsten nitride layer, the nitrogenize molybdenum layer, niobium nitride layer, the silicon titanium nitride layer, the aluminium titanium nitride layer, the boron titanium nitride layer, the silicon zirconium nitride layer, the tungsten silicon nitride layer, the boron tungsten nitride layer, the aluminium zirconium nitride layer, silicon nitrogenize molybdenum layer, aluminium nitrogenize molybdenum layer, the silicon tantalum nitride layer, the aluminium tantalum nitride layer, titanium layer, molybdenum layer, tantalum layer, titanium silicide layer, the silication tantalum layer, titanium tungsten layer, the oxynitriding titanium layer, the alumina titanium nitride layer, the oxynitriding tungsten layer, a kind of formation of oxynitriding tantalum layer or copper layer.
41, method according to claim 34, wherein, when the described interlayer dielectric layer of going up is formed by silicon oxide layer, by using C xH yF zFirst main etching gas and the C of system vF wThe second main etching gas of system comes the described interlayer dielectric layer of going up of etching to form described printed line contact hole as main etching gas.
42, method according to claim 34 wherein, forms described phase-change material contact hole to have the vertical center axis that separates from the described vertical center axis of conductive plugs down.
43, method according to claim 34 wherein, forms described printed line contact hole to have the vertical center axis that separates from the vertical center axis of described phase-change material contact hole.
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