CN1790550B - Shift register method - Google Patents
Shift register method Download PDFInfo
- Publication number
- CN1790550B CN1790550B CN 200410077649 CN200410077649A CN1790550B CN 1790550 B CN1790550 B CN 1790550B CN 200410077649 CN200410077649 CN 200410077649 CN 200410077649 A CN200410077649 A CN 200410077649A CN 1790550 B CN1790550 B CN 1790550B
- Authority
- CN
- China
- Prior art keywords
- shift register
- pulse
- counter
- output
- produces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a shift register system, method and display device of driving circuit, which comprises the following parts: shift register, counter and several switch elements, wherein the shift register contains initial pulse end to receive the exterior signal, several output ends and control end; the counter contains signal receiving end in connection with the register control end, pulse output end and several output ends in connection with the initial pulse end; several switch elements contain several input ends in connection with the output ends, several output ends in connection with the exterior and switch end in connection with one of the counter output ends.
Description
[technical field]
The invention relates to a kind of shift register system.
[background technology]
Shift register generally is applied in the driving circuit of display device, shift register in the gate driver circuit of display device passes through sweep trace output scanning signal line by line, shift register in the source electrode drive circuit of display device is used for picture signal write signal line, by the display pixel display image signals.
Please refer to Fig. 1, is a kind of display device drive circuit synoptic diagram of prior art.(Thin Film Transistor TFT) drives pixel electrode 103 as switch to its applied film transistor, and the opposite that reverse side electrode 105 is positioned at pixel electrode 103 forms a common conductive layer, and fixed voltage Vc links to each other with reverse side electrode 105; Gate drivers (IntegratedCircuits, integrated circuit) 300 and source electrode driver 200 drive n line scanning electrode and m column signal electrode respectively; Source electrode driver 200 by shift register 210 sampled image signals after sampling controller 220 and output buffer 230 provide it to signal electrode 102, gate drivers 300 is successively by shift register (Shift Register) 310, level translator (Level Shifter) 320 and output buffer (Output Buffer) 330 output scanning pulses are to scan electrode 101, and controller 400 controls offer time signal and other signal of gate drivers 300 and source electrode driver 200.
Shift register 310 in this gate drivers 300 has 256 output terminals, and then these shift register 310 inside need 256 registers to form.Because of the shift register 310 inner registers that need numerous quantity, therefore can occupy bigger chip area, and make production cost higher.
[summary of the invention]
The shift register inner structure occupies the big problem of chip area in the prior art in order to overcome, and the invention provides a kind of shift register method.
Shift register method of the present invention, by having the shift register of one first predetermined quantity n (n 〉=1) output terminal, one counter and one second predetermined quantity m (m 〉=1)) on-off element comes realization data output with the shift register system of reaching n * m output terminal, this method comprises: counter receives outside initial pulse, the starting end of this counter transmits a pulse and to the initial pulse end of this shift register it is triggered and be opening then, the output terminal of this counter transmits a pulse and to first on-off element its triggering is opening, and remaining on-off element is a closed condition; This shift register receives that pulse that this counter transmits begins to produce the displacement output signal and n output terminal by this shift register offers this first on-off element, and is exported by this first on-off element; (1≤i≤n) is after the individual clock period for i when first on-off element is in opening, this shift register produces a pulse to this counter, this counter produces a pulse to the second on-off element its triggering is opening, remaining on-off element is a closed condition, this counter also produces a pulse to this shift register makes the signal of its n output terminal output offer this second on-off element, and is exported by this second on-off element; And the like, after i the clock period when m on-off element is in opening, this shift register produces a pulse to this counter, this counter produces a pulse to this shift register and makes this shift register output signal again, or no longer produces this shift register of trigger action.
Compared to prior art, shift register method of the present invention adopts on-off element to be connected with the output terminal of register, thereby produce displacement output by many groups switch and can solve the more and inner big problem of chip space that occupies of the required register of shift register, therefore can reduce production costs.
[description of drawings]
Fig. 1 is a prior art display device drive circuit synoptic diagram.
Fig. 2 is a shift register system synoptic diagram of the present invention.
Fig. 3 is a drive waveforms synoptic diagram of the present invention.
Fig. 4 is the driving circuit synoptic diagram of display device of the present invention.
[embodiment]
Please refer to Fig. 2, is shift register system synoptic diagram of the present invention.This shift register system 31 comprises shift register 311, counter 316, first on-off element 312, second switch element 313, the 3rd on-off element 314 and the 4th on-off element 315.These shift register 311 inside comprise 64 output terminals being made up of 64 registers (figure does not show), and one is used for the initial pulse end STV1 and a control end STV2 of received signal.This counter 316 comprises a signal receiving end STV, a pulse output end a and four open and close signal output part b1, b2, b3, b4.This signal receiving end STV is connected with the control end STV2 of this shift register, and this pulse output end a is connected with the initial pulse end STV1 of this shift register.These four groups of on-off element inside comprise respectively corresponding to pairing 64 input ends of shift register 311 output terminals, 64 output terminals and an open and close end on/off; In these four groups of on-off elements, the open and close end on/off of first on-off element 312 is connected with the open and close signal output part b1 of this counter 316, the open and close end on/off of second switch element 313 is connected with the open and close signal output part b2 of this counter 316, the open and close end on/off of the 3rd on-off element 314 is connected with the open and close signal output part b3 of this counter 316, and the open and close end on/off of the 4th on-off element 315 is connected with the open and close signal output part b4 of this counter 316.The input end of these four groups of on-off elements is connected with the output terminal of this shift register 311 by the data bus with 64, and the output terminal of these four groups of on-off elements did not link to each other with outside (figure shows), in order to output signal.
Please refer to Fig. 3, is shift register method drive waveforms synoptic diagram of the present invention.Below be that example is introduced shift register method of the present invention with 256 shift pulse signals of shift register system of the present invention 31 outputs.256 shift pulse signals that shift register system 31 is received are by its first on-off element 312, second switch element 313, the 3rd on-off element 314 and 315 outputs of the 4th on-off element.At first, the counter 316 of shift register system 31 inside receives outside initial pulse, the starting end a of this counter 316 transmits the initial pulse end STV1 of a pulse to shift register 311 then, and output terminal b1 transmits the open and close end on/off of pulse to the first on-off element 312.The pulse that the control end STV1 of this shift register 311 receives this counter 316 starting end a transmission begins to produce displacement output.The trigger action that this first on-off element 312 is transmitted by this counter 316 output terminal b1 is opening and receives the displacement output signal that this shift register 311 produces.Second switch element 313, the 3rd on-off element 314 and the 4th on-off element 315 promptly are not in closed condition owing to be triggered at this moment, therefore 64 output terminals of this shift register 311 are exported to first on-off element 312 by bus with its 1-64 pulse signal, this moment by 64 output terminals of first on-off element 312 to outside transmission signals, i.e. waveform shown in S1.1～S1.64 among the figure.
After 63 clock period, one control end STV2 of this shift register 311 end is sent the control end STV end that a pulse is back to this counter 316. this counter 316 receives after the pulse it once again and sends a pulse and receive the pulse that this counter 316 starting end a transmit to a control end STV1 of this shift register 311 with the control end STV1 that triggers these shift register 311. these shift registers 311 and begin to produce displacement output to trigger second switch element 313 and to send a pulse by its starting end a synchronously. the trigger action that this second switch element 313 is transmitted by this counter 316 output terminal b2 is opening and receives the displacement output signal that this shift register 311 produces. this moment first on-off element 312, the 3rd on-off element 314 and the 4th on-off element 315 promptly are not in closed condition owing to be triggered, therefore 64 output terminals of this shift register 311 are exported to second switch element 313 by bus with its 65-128 pulse signal, this moment by 64 output terminals of second switch element 313 to outside transmission signals, i.e. waveform shown in S2.1～S2.64 among the figure.
Through after 63 clock period, a control end STV2 of this shift register 311 end is sent the control end STV end that a pulse is back to this counter 316 again.This counter 316 receive once again after the pulse its send a pulse with trigger the 3rd on-off element 314 and synchronously by its starting end a send a pulse to a control end STV1 of this shift register 311 to trigger this shift register 311.The trigger action that the 3rd on-off element 314 is transmitted by this counter 316 output terminal b3 is opening and receives the displacement output signal that this shift register 311 produces.First on-off element 312, second switch element 313 and the 4th on-off element 315 promptly are not in closed condition owing to be triggered at this moment, therefore 64 output terminals of this shift register 311 are exported to the 3rd on-off element 314 by bus with its 129-192 pulse signal, this moment by 64 output terminals of the 3rd on-off element 314 to outside transmission signals, i.e. waveform shown in S3.1～S3.64 among the figure.
Through after 63 clock period, a control end STV2 of this shift register 311 end is sent the control end STV end that a pulse is back to this counter 316 again.This counter 316 receive once again after the pulse its send a pulse with trigger the 4th on-off element 315 and synchronously by its starting end a send a pulse to a control end STV1 of this shift register 311 to trigger this shift register 311.The trigger action that the 4th on-off element 315 is transmitted by this counter 316 output terminal b4 is opening and receives the displacement output signal that this shift register 311 produces.First on-off element 312, second switch element 313 and the 3rd on-off element 314 promptly are not in closed condition owing to be triggered at this moment, therefore 64 output terminals of this shift register 311 are exported to the 4th on-off element 315 by bus with its 193-256 pulse signal, this moment by 64 output terminals of the 4th on-off element 315 to outside transmission signals, i.e. waveform shown in S4.1～S4.64 among the figure.
Through after 63 clock period, a control end STV2 of this shift register 311 end is sent the control end STV end that a pulse is back to this counter 316 again.Behind the 5th received pulse of this counter 316, if it is when this transmits this shift register 311 of trigger action, this shift register 311 produces displacement output again in the manner described above, and these four groups of on-off elements are output signal in order; If it no longer transmits this shift register 311 of a trigger action, then it transmits signal to other circuit (figure does not show), and this shift register 311 no longer produces displacement output.Then one has the shift register 311 of 64 registers and 256 pulse signals of shift register system 31 realization outputs of four groups of on-off elements.
In addition, the output terminal of the shift register 311 of shift register system of the present invention 31 inside is not limited to 64, can enlarge or dwindle the quantity of its output terminal as required,, then only need two groups of on-off elements to realize equally with input and output terminal of respective numbers if it is 128 output terminals.Be not limited to after through 63 clock period, the control end STV2 end of this shift register 311 is sent the control end STV end that a pulse is back to this counter 316, also can be after through 62 clock period, perhaps a certain moment in 64 clock period, the control end STV2 end of this shift register 311 is sent the control end STV end that a pulse is back to this counter 316.
Please refer to Fig. 4, be display device drive circuit synoptic diagram of the present invention. the glass substrate of this display device 1 did not comprise on (figure shows): a plurality of pixels 10, gate drivers 20, source electrode driver 30 and controller 40. these a plurality of pixels 10 formation 50. gate drivers, 20 inside, one viewing area comprise shift register system as shown in Figure 2. and the internal circuit of source electrode driver 30 is identical with tradition. and controller 40 is used for the initial pulse signal and the clock signal of control gate driver 20 and source electrode driver 30. and gate drivers 20 drives the capable gate line of n, source electrode driver 30 drives the m column data line. and thin film transistor (TFT) (figure does not show) drives a plurality of pixels 10 as switch, it is positioned at the infall of capable gate line of n and m column data line, and the opposite that reverse side electrode (figure does not show) is positioned at these a plurality of pixels 10 forms a common conductive layer. and this thin film transistor (TFT) is made up of polysilicon.
Because shift register system of the present invention, shift register method are connected with a plurality of on-off elements with shift register in the display device drive circuit, compared with prior art, the picture signal of exporting identical figure place adopts the register of lesser amt, thereby can save the shift register volume inside, reduce chip area, thereby reduce production costs.
In addition, shift register system of the present invention is not limited to be applied in the gate drivers of display device drive circuit, also can be applicable in the source electrode driver.
Claims (4)
1. shift register method, come the output of realization data by shift register, a counter and one second predetermined quantity m on-off element with the shift register system of reaching n * m output terminal with one first predetermined quantity n output terminal, wherein n 〉=1, m 〉=1, this method comprises:
Counter receives outside initial pulse, the starting end of this counter transmits a pulse and to the initial pulse end of this shift register it is triggered and be opening then, the output terminal of this counter transmits a pulse and to first on-off element its triggering is opening, and remaining on-off element is a closed condition;
This shift register receives that pulse that this counter transmits begins to produce the displacement output signal and n output terminal by this shift register offers this first on-off element, and is exported by this first on-off element;
I when first on-off element is in opening is after the clock period, this shift register produces a pulse to this counter, this counter produces a pulse to the second on-off element its triggering is opening, remaining on-off element is a closed condition, this counter also produces a pulse to this shift register makes the signal of its n output terminal output offer this second on-off element, and exported 1≤i≤n wherein by this second on-off element;
And the like, after i the clock period when m on-off element is in opening, this shift register produces a pulse to this counter, this counter produces a pulse to this shift register and makes this shift register output signal again, or no longer produces this shift register of trigger action.
2. shift register method as claimed in claim 1 is characterized in that: this n value is 64.
3. shift register method as claimed in claim 1 is characterized in that: this m value is 4.
4. shift register method as claimed in claim 1 is characterized in that: this i value is 63.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410077649 CN1790550B (en) | 2004-12-18 | 2004-12-18 | Shift register method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410077649 CN1790550B (en) | 2004-12-18 | 2004-12-18 | Shift register method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1790550A CN1790550A (en) | 2006-06-21 |
| CN1790550B true CN1790550B (en) | 2010-05-12 |
Family
ID=36788314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410077649 Expired - Fee Related CN1790550B (en) | 2004-12-18 | 2004-12-18 | Shift register method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1790550B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123391B (en) * | 2017-07-07 | 2020-02-28 | 京东方科技集团股份有限公司 | Gate driving unit and driving method thereof, gate driving circuit and display device |
| CN107331358B (en) * | 2017-07-19 | 2019-11-15 | 深圳市华星光电半导体显示技术有限公司 | A kind of display panel and display panel grid signal control method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577472A (en) * | 2003-07-17 | 2005-02-09 | 恩益禧电子股份有限公司 | Scan electrode driving circuit and display apparatus |
| CN2763945Y (en) * | 2004-11-26 | 2006-03-08 | 鸿富锦精密工业（深圳）有限公司 | Shift register system and display device driving circuit |
-
2004
- 2004-12-18 CN CN 200410077649 patent/CN1790550B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577472A (en) * | 2003-07-17 | 2005-02-09 | 恩益禧电子股份有限公司 | Scan electrode driving circuit and display apparatus |
| CN2763945Y (en) * | 2004-11-26 | 2006-03-08 | 鸿富锦精密工业（深圳）有限公司 | Shift register system and display device driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1790550A (en) | 2006-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100255835B1 (en) | Shift register and image display apparatus | |
| CN1953007B (en) | Flat panel display and operation method thereof | |
| CN100541592C (en) | Shift register | |
| CN1835063B (en) | Shift register circuit and drive control apparatus | |
| KR100549157B1 (en) | Liquid crystal display device | |
| US8068577B2 (en) | Pull-down control circuit and shift register of using same | |
| EP3333843A1 (en) | Shift register, gate driving circuit, display panel driving method, and display device | |
| US20060050043A1 (en) | Liquid crystal display device and driving method thereof | |
| US6963327B2 (en) | Shift register circuit including first shift register having plurality of stages connected in cascade and second shift register having more stages | |
| US20080101529A1 (en) | Shift register and image display apparatus containing the same | |
| CN102013244B (en) | Liquid crystal display driving circuit and related driving method | |
| US20060071892A1 (en) | Display element drive unit, display device including the same, and display element drive method | |
| US20170221439A1 (en) | Gate Driver Unit, Gate Driver Circuit and Driving Method Thereof, and Display Device | |
| US20020167504A1 (en) | Driving circuit and display including the driving circuit | |
| JP2005222688A (en) | Shift register and display device provided with the same | |
| CN101978428A (en) | Shift register and active matrix device | |
| CN102831861A (en) | Shifting register, drive method thereof, gate driver and display device | |
| JP2005196158A (en) | Drive circuit for liquid crystal display | |
| TW200915284A (en) | A liquid crystal display and the driving method thereof | |
| CN101510398A (en) | Source electrode drive circuit | |
| KR101227342B1 (en) | Semiconductor integrated circuit device and liquid crystal display driving semiconductor integrated circuit device | |
| US6765980B2 (en) | Shift register | |
| CN113554970B (en) | GOA driving circuit, display panel and display device | |
| CN100342271C (en) | Display device | |
| CN1790550B (en) | Shift register method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100512 Termination date: 20151218 |
|
| EXPY | Termination of patent right or utility model |