CN102831861A - Shifting register, drive method thereof, gate driver and display device - Google Patents
Shifting register, drive method thereof, gate driver and display device Download PDFInfo
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- CN102831861A CN102831861A CN2012103267034A CN201210326703A CN102831861A CN 102831861 A CN102831861 A CN 102831861A CN 2012103267034 A CN2012103267034 A CN 2012103267034A CN 201210326703 A CN201210326703 A CN 201210326703A CN 102831861 A CN102831861 A CN 102831861A
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Abstract
The invention relates to the technical field of the display, and provides a shifting register, a drive method thereof, a gate driver and a display device. The shifting register comprises an input module, a resetting control module, a resetting module and an output module, wherein the input module transmits an input signal to a pull-up module according to a signal inputted by an signal input end and a signal inputted by a first clock signal end; the resetting control module transmits a control signal to the resetting module according to a first level signal, a second level signal, the signal inputted by the first clock signal end, a signal inputted by a second clock signal end and the input signal; the resetting module is used for resetting an output end according to the control signal transmitted by the resetting control module and the first level signal; and the output module transmits an output signal to the output end according to the signal transmitted by the input module and the second level signal. The shifting register is simple and compact in structure, stable in performance and capable of realizing horizontal drive through small area.
Description
Technical field
The present invention relates to the display device technical field, a kind of shift register and driving method thereof, gate drivers and display device are provided.
Background technology
(Organic Light-Emitting Diode OLED) as a kind of light source with advantages such as high brightness, wide visual angle, response speed are fast, is applied to during high-performance shows Organic Light Emitting Diode more and more.The Traditional passive matrix/organic light emitting shows that (Passive Matrix OLED PMOLED) along with the increase of display size, needs the driving time of shorter single pixel, thereby needs to increase transient current, causes power consumption to increase.The application of big electric current simultaneously can cause on the ITO line pressure drop excessive, and makes the OLED WV too high, reduces its work efficiency.And active matrix organic light-emitting shows that (Active Matrix OLED AMOLED) through the switching tube input OLED electric current of lining by line scan, can address these problems well.
Compare with AMLCD, the AMOLED gray-scale displayed is directly proportional with the drive current of driving OLED device, and in order to realize the demonstration of higher gray scale, AMOLED needs bigger drive current, so AMOLED adopts the higher polysilicon technology of mobility to realize more.In order to compensate the problem of the threshold voltage shift that multi-crystal TFT exists; The image element circuit of AMOLED often needs the corresponding compensation structure; So the image element circuit structure of AMOLED is more complicated; Also need take bigger layout (layout) area accordingly, be unfavorable for the miniaturization and ultra-thinization of display device.
Summary of the invention
The technical matters that (one) will solve
To above-mentioned shortcoming, the AMOLED circuit takies the problem of layout area greatly in the prior art in order to solve in the present invention, and a kind of shift register and driving method thereof, gate drivers and display device are provided.
(2) technical scheme
For addressing the above problem, at first, the invention provides a kind of shift register, said shift register comprises: load module, send input signal according to the signal of the signal of signal input part input and the input of first clock signal terminal drawing-die piece that makes progress; Control module resets; Link to each other with said load module and reseting module, transmit control signal to reseting module according to the signal of first level signal, second level signal, the input of first clock signal terminal, the signal and the said input signal of second clock signal end input; Reseting module links to each other with said control module and the output terminal of resetting, and according to the said control signal and first level signal said output terminal is resetted; Output module links to each other with said load module and output terminal, sends the output signal according to signal and said second level signal that said load module sends to said output terminal.
Preferably, said output module comprises the transistor seconds and first electric capacity, and the source electrode of transistor seconds connects the second clock signal end, and drain electrode connects output terminal at the corresponding levels, and grid connects the first level node; A pole plate of first electric capacity connects the first level node, and another pole plate connects the drain electrode of transistor seconds.
Preferably, said reseting module comprises the first transistor and second electric capacity, and the source electrode of the first transistor connects first level signal, and drain electrode connects the output terminal of shift register at the corresponding levels, and grid connects the second level node; A pole plate of second electric capacity connects the second level node, and another pole plate connects first level signal.
Preferably, said load module comprises the 3rd transistor, and the 3rd transistorized source electrode connects input end, and drain electrode connects the first level node, and grid connects first clock signal terminal.
Preferably, the said control module that resets comprises the 4th, the 5th, the 6th and the 7th transistor, and the 4th transistor drain connects second level signal, and grid connects first clock signal terminal, and source electrode connects the 6th transistor drain; Perhaps, the 4th transistor drain is connected second level signal simultaneously with grid, and source electrode connects the 6th transistor drain; The 5th transistorized source electrode connects first level signal, and grid connects the first level node, and drain electrode connects the 7th transistorized source electrode; The 6th transistorized source electrode connects the second level node, and drain electrode connects the 4th transistorized source electrode, and grid connects first clock signal terminal; The 7th transistorized source electrode connects the 5th transistor drain, and drain electrode connects the second level node, and grid connects the second clock signal end.
Preferably, said first to the 7th transistor all is the P transistor npn npn or all is the N transistor npn npn.
Preferably, when all being the P transistor npn npn, first level signal is a high level signal, and second level signal is a low level signal; When all being the N transistor npn npn, first level signal is a low level signal, and second level signal is a high level signal.
Preferably, said first to the 7th transistor is TFT.
Preferably, the TFT that each pixel cell is corresponding on said first to the 7th transistorized TFT and the array base palte adopts identical technology to form simultaneously.
On the other hand; The present invention also provides a kind of gate drivers simultaneously; Said gate drivers comprises the aforesaid shift register of a plurality of cascades; First clock signal terminal of each grade shift register and second clock signal end connect the clock signal of two anti-phases respectively, and the connection of two clock signal terminals of adjacent level is opposite simultaneously; The input end of each grade connects the output terminal of upper level, with the output of the upper level input as the corresponding levels; The input termination initial input signal of the first order, the output of each grade is as the control signal of corresponding row grid.
On the other hand, the present invention also provides a kind of display device simultaneously, and said display device comprises: aforesaid gate drivers.
At last, the present invention also provides a kind of driving method of shift register, is applied to above-mentioned shift register; The method comprising the steps of: the signal in the input end input is in the low level cycle; The signal of first clock signal terminal input is a low level, and the signal of second clock signal end input is a high level, and the control module that resets is sent drive signal to reseting module; Reseting module resets to output terminal, output terminal output high level signal; In the next clock period; The signal of the signal of input end input and the input of first clock signal terminal is high level; The signal of second clock signal end input is a low level; Output module sends the output signal to output terminal, and the control module that resets is sent cut-off signals to reseting module, output terminal output low level signal; In next clock period again; The signal of input end input is a high level; The signal of first clock signal terminal input is a low level, and the signal of second clock signal end input is a high level, and the control module that resets is sent drive signal to reseting module; Reseting module resets to output terminal, output terminal output high level signal.
(3) beneficial effect
Adopt 7 transistors and 2 electric capacity promptly to form shift register among the present invention, be used for, realized the row of AMOLED is driven with minimum area to each capable shift register structure compact, stable performance that drives; Thereby integrated gate drive circuitry on array base palte effectively; And need not connect extra drive IC at substrate edges, and reduced the layout area of circuit as far as possible, realized that the height of driving circuit is integrated; Simplified the complexity of peripheral drive circuit among the present invention; Having saved material and preparation technology simultaneously, obviously reduced process time and production cost, is the optimal selection that realizes that high resolution A MOLED shows.
Description of drawings
Fig. 1 is the structured flowchart according to the shift register of one embodiment of the present invention;
Fig. 2 is the circuit structure diagram of shift register in the embodiment of the invention 1;
Fig. 3 is the level signal logic timing figure of the shift register of the embodiment of the invention 1;
Fig. 4 is the circuit structure diagram of shift register in the embodiment of the invention 2;
Fig. 5 is the level signal logic timing figure of the shift register of the embodiment of the invention 2;
Fig. 6 is the circuit structure diagram of shift register in the embodiment of the invention 3;
Fig. 7 is the gate driver circuit structural drawing of a plurality of shift register cascades among the present invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, the every other embodiment that those of ordinary skills are obtained under the prerequisite of not making creative work belongs to the scope that the present invention protects.
As shown in Figure 1, the shift register of accordinging to one embodiment of the present invention comprises: load module, the control module that resets, reseting module and output module.Wherein, load module sends input signal according to the signal of the signal of signal input part input and the input of first clock signal terminal drawing-die piece that makes progress; The control module that resets links to each other with said load module and reseting module, transmits control signal to reseting module according to the signal of first level signal, second level signal, the input of first clock signal terminal, the signal and the said input signal of second clock signal end input; Reseting module links to each other with said controll block and the output terminal of resetting, and according to the said control signal and first level signal said output terminal is resetted; Output module links to each other with said load module and output terminal, sends the output signal according to signal and said second level signal that said load module sends to said output terminal.
The driving method of above-mentioned shift register comprises step:
Signal in the input end input is in the low level cycle; The signal of first clock signal terminal input is a low level; The signal of second clock signal end input is a high level; The control module that resets is sent drive signal to reseting module, and reseting module resets to output terminal, output terminal output high level signal;
In the next clock period; The signal of the signal of input end input and the input of first clock signal terminal is high level; The signal of second clock signal end input is a low level; Output module sends the output signal to output terminal, and the control module that resets is sent cut-off signals to reseting module, output terminal output low level signal;
In next clock period again; The signal of input end input is a high level; The signal of first clock signal terminal input is a low level, and the signal of second clock signal end input is a high level, and the control module that resets is sent drive signal to reseting module; Reseting module resets to output terminal, output terminal output high level signal.
Further specify technical scheme of the present invention through concrete embodiment below.
In order to reduce the layout area of circuit as far as possible, adopt GOA (Gate on Array, integrated gate driving is claimed in the capable driving of array base palte again) mode to realize that the height of driving circuit is integrated among the present invention.Particularly; Be used among the present invention each row the shift register structure compact, the stable performance that drive, realized the row of AMOLED is driven with minimum area, thus integrated gate drive circuitry on array base palte effectively; And need not connect extra drive IC at substrate edges; Having simplified the complexity of peripheral drive circuit, reduced the layout area of GOA circuit, is the optimal selection that realizes that high resolution A MOLED shows.
Further; As shown in Figure 2; In the embodiments of the invention 1; Shift register receives the control of the clock signal (the signal CLK of first clock signal terminal input and the signal CLKB of second clock signal input part input) of two complementations (promptly inversion signal) each other, receives the input signal (INPUT) of the output G [n-1] of upper level circuit as the corresponding levels.
Be that example describes with P transistor npn npn (PMOS) at first among Fig. 2, in this shift register: output module comprises the transistor seconds and first electric capacity, and reseting module comprises the first transistor and second electric capacity; Load module comprises the 3rd transistor; The control module that resets comprises the 4th, the 5th, the 6th and the 7th transistor, and wherein, the source electrode of the first transistor T1 connects first level signal; Drain electrode connects output terminal G [n] at the corresponding levels, and grid connects the second level node N2; The source electrode of transistor seconds T2 connects second clock signal end CLKB, and drain electrode connects output terminal G [n] at the corresponding levels, and grid connects the first level node N1; The source electrode of the 3rd transistor T 3 connects input end INPUT (the output G [n-1] by upper level provides input signal), and drain electrode connects the first level node N1, and grid connects the first clock signal terminal CLK; The drain electrode of the 4th transistor T 4 connects second level signal, and grid connects the first clock signal terminal CLK, and source electrode connects the drain electrode of the 6th transistor T 6; The 5th transistor T 5 source electrodes connect first level signal, and grid connects the first level node N1, and drain electrode connects the source electrode of the 7th transistor T 7; The source electrode of the 6th transistor T 6 connects the second level node N2, and drain electrode connects the source electrode of the 4th transistor T 4, and grid connects the first clock signal terminal CLK; The source electrode of the 7th transistor T 7 connects the drain electrode of the 5th transistor T 5, and drain electrode connects the second level node N2, and grid connects second clock signal end CLKB; A pole plate of first capacitor C 1 connects the first level node N1, and another pole plate connects the drain electrode of transistor seconds T2; A pole plate of second capacitor C 2 connects the second level node N2, and another pole plate connects first level signal.Among Fig. 1, when adopting the P transistor npn npn, first level signal is high level signal VGH, and second level signal is low level signal VGL.
Further with reference to the level signal synoptic diagram of figure 3, following below to the course of work introduction of the shift register of P transistor npn npn formation in the embodiments of the invention 1:
This shift register is by the clock signal clk and the CLKB control of two complementations, and the output G [n-1] of upper level shift-register circuit is as input signal at the corresponding levels.The course of work of this shift-register circuit is divided into input sample, exports signal, three phases resets.
In the t1 stage, G [n-1] is a low imput, and control signal CLK is a low level, and transistor T 3 conductings are so the level that this moment, N1 was ordered is pulled down to VGL+|Vthp| accordingly.At this moment, transistor T 4 and T6 conducting, the N2 point is a low level, so transistor T 1 conducting, output G [n] is high level VGH.And this moment, the CLKB signal also was a high level, thereby had guaranteed that output G [n] is a high level.This moment, C1 was recharged, and input signal G [n-1]=VGL is sampled, and the voltage difference at C1 two ends is VGH-VGL-∣ Vthp ∣.
In the t2 stage, input signal G [n-1] and CLK signal are high, and transistor T 3 is closed, and the level that N1 is ordered is kept by C1, for VGL+ ∣ Vthp ∣, is low level, so transistor T 2 conductings, CLKB is a low level simultaneously, import G [n] this moment and are low level.Simultaneously CLKB is a low level, and N1 point also be a low level, thus transistor T 5 and T7 conducting, and CLK to be high level guaranteed that transistor T 6 is closed has guaranteed that the N2 point is a high level, transistor T 1 is closed, and can not exert an influence to exporting G [n].
In the t3 stage, CLK is a low level, transistor T 3 conductings, and G [n-1] is a high level; The level that corresponding N is 1 will be drawn high and be high level, and then transistor T 2 is closed, and CLK is low simultaneously, transistor T 4 and T6 conducting; And CLKB is high, and transistor T 7 is closed, and has guaranteed the low level that N2 is ordered; Transistor T 1 is opened, and input G [n] is drawn high once more is high level VGH, realizes resetting of output.
The speed that the on off state influence output G [n] of transistor T 4 resets adopts the CLK signal that transistor T 4 is controlled.Guaranteed at t1, t2, this gate line of t3 outside the period non-selects the stage, and it is steady relatively that the level of input G [n] keeps, and it is less to fluctuate.Capacitor C 2 has been guaranteed and should have been closed by period transistor T 1 at the level that the t2 period has kept N2 to order simultaneously, guarantees to import the low level stability of G [n].
Embodiments of the invention 2 are as shown in Figure 4, and wherein, shift register receives the control of the clock signal (CLK and CLKB) of two complementations (promptly inversion signal) each other equally, receive the input signal (INPUT) of the output of upper level circuit as the corresponding levels.The embodiment 2 among Fig. 4 and the key distinction of the embodiment 1 among Fig. 2 are, adopt N transistor npn npn (NMOS) to constitute shift register among the embodiment 2.
Shift register among the embodiment 2 comprises equally: first to the 7th transistor and first, second electric capacity, and wherein, the source electrode of the first transistor T1 connects first level signal, and drain electrode connects output terminal G [n] at the corresponding levels, and grid connects the second level node N2; The source electrode of transistor seconds T2 connects second clock signal end CLKB, and drain electrode connects output terminal G [n] at the corresponding levels, and grid connects the first level node N1; The source electrode of the 3rd transistor T 3 connects input end INPUT (the output G [n-1] by upper level provides input signal), and drain electrode connects the first level node N1, and grid connects the first clock signal terminal CLK; The drain electrode of the 4th transistor T 4 connects second level signal, and grid connects the first clock signal terminal CLK, and source electrode connects the drain electrode of the 6th transistor T 6; The 5th transistor T 5 source electrodes connect first level signal, and grid connects the first level node N1, and drain electrode connects the source electrode of the 7th transistor T 7; The source electrode of the 6th transistor T 6 connects the second level node N2, and drain electrode connects the source electrode of the 4th transistor T 4, and grid connects the first clock signal terminal CLK; The source electrode of the 7th transistor T 7 connects the drain electrode of the 5th transistor T 5, and drain electrode connects the second level node N2, and grid connects second clock signal end CLKB; A pole plate of first capacitor C 1 connects the first level node N1, and another pole plate connects the drain electrode of transistor seconds T2; A pole plate of second capacitor C 2 connects the second level node N2, and another pole plate connects first level signal.Can find out from the contrast of Fig. 3 and Fig. 1; The connected mode of each transistor AND gate electric capacity and embodiment 1 are basic identical among the embodiment 2; Be with the difference of embodiment 1 among Fig. 1, among the embodiment 2, when adopting the N transistor npn npn; First level signal is low level signal VGL, and second level signal is high level signal VGH.
Again with reference to the level signal synoptic diagram of figure 5, following below to the course of work introduction of the shift register of N transistor npn npn formation in the embodiments of the invention 2:
By the clock signal clk and the CLKB control of two complementations, the output G [n-1] of upper level shift-register circuit is as input signal at the corresponding levels equally for this shift register among the embodiment 2.The course of work of this shift-register circuit also is divided into input sample, exports signal, three phases resets.
In the t1 stage, G [n-1] is the high level input signal, and control signal CLK is a high level, and transistor T 3 conductings are so the level that this moment, N1 was ordered is dragged down accordingly.At this moment, transistor T 4 and T6 conducting, the N2 point is a high level, so transistor T 1 conducting, output G [n] is low level VGL.And this moment, the CLKB signal also was a low level, thereby had guaranteed that output G [n] is low level.This moment, C1 was recharged, and input signal G [n-1] is sampled.
In the t2 stage, input signal G [n-1] and CLK signal are low, and transistor T 3 is closed, and the level that N1 is ordered remains high level by C1, so transistor T 2 conductings, CLKB is a high level simultaneously, and import G [n] this moment is high level.Simultaneously CLKB is a high level, and N1 point also be a high level, thus transistor T 5 and T7 conducting, and CLK to be low level guaranteed that transistor T 6 is closed has guaranteed that the N2 point is a low level, transistor T 1 is closed, and can not exert an influence to exporting G [n].
In the t3 stage, CLK is a high level, transistor T 3 conductings, and G [n-1] is a low level; The level that corresponding N is 1 will drag down and be low level, and then transistor T 2 is closed, and CLK is high simultaneously, transistor T 4 and T6 conducting; And CLKB is low, and transistor T 7 is closed, and has guaranteed the high level that N2 is ordered; Transistor T 1 is opened, and input G [n] is dragged down once more is low level VGL, realizes resetting of output.
The speed that the on off state influence output G [n] of transistor T 4 resets adopts the CLK signal that transistor T 4 is controlled.Guaranteed at t1, t2, this gate line of t3 outside the period non-selects the stage, and it is steady relatively that the level of input G [n] keeps, and it is less to fluctuate.Capacitor C 2 has been guaranteed and should have been closed by period transistor T 1 at the level that the t2 period has kept N2 to order simultaneously, guarantees to import the stability of G [n] high level.
Embodiment 3
Embodiments of the invention 3 are as shown in Figure 6, and through finding out that with the contrast of the embodiment 1 of Fig. 2 in this embodiment 3, the basic circuit structure of shift register is similar, just the connected mode of the drain and gate of the 4th transistor T 4 is slightly had any different.In embodiment 3, the drain and gate of the 4th crystal transistor T 4 connects second level signal (PMOS is low level signal VGL during pipe) simultaneously.In this way, the 4th transistor T 4 is operated in state of saturation, and it is in conducting state all the time, thereby when realizing, can utilize less device size to realize the corresponding stronger ability that drags down.
In the course of work of embodiment 3, except transistor T 4 is in the conducting state all the time, all the other processes and embodiment 1 are basic identical, repeat no more at this.In addition, this embodiment is equally applicable in the circuit of embodiment 2, and just second level signal is high level signal VGH under the NMOS pattern.
More preferably; Each transistor in the shift register in the various embodiments of the present invention and each cell can adopt TFT (Thin Film Transistor; Thin film transistor (TFT)) constitutes; In the time of on being integrated in array base palte, can adopt identical technology to form simultaneously with the TFT that each pixel cell is corresponding on the array base palte.That is, the corresponding array base palte that adopts P type TFT of the shift register that P type TFT constitutes, the corresponding array base palte that adopts N type TFT of the shift register that N type TFT constitutes can further reduce whole device preparing process like this.
Referring to Fig. 7, in the present invention, a plurality of above-mentioned shift register cascades constitute the gate drivers of liquid crystal panel again.Particularly; The cascade structure that is cascaded into gate drivers by N shift register is: each grade shift register (STAGE_1; STAGE_2; ...., STAGE_N-1, first clock signal terminal CLKIN STAGE_N) and second clock signal end CLKBIN connect the clock signal (first clock signal clk and second clock signal CLKB) of two anti-phases respectively; The connection of two clock signal terminals of adjacent level simultaneously opposite (if promptly the CLKIN of odd level connects first clock signal clk, then the CLKIN of even level meets second clock signal CLKB); The input end IN of each grade connects the output terminal G [n] of upper level, with the output of the upper level input as the corresponding levels; The input termination initial input signal INPUT of the first order, the output of each grade is as the control signal G_1 of corresponding row grid, G_2 ...., G_N-1, G_N.Through the gate drivers of this cascade, liquid crystal panel is opened the controlling grid scan line (abbreviation grid line) of each row successively and is closed the controlling grid scan line of other row under the driving of each signal, realizes lining by line scan thereby only drive the corresponding TFT of this row pixel cell.
Preferably, above-mentioned gate drivers is integrated in and forms the GOA unit on the array base palte.The present invention also provides a kind of display device, and this display device comprises as above said gate drivers.Said display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, LCD, DPF, mobile phone, panel computer.
Among the present invention, be used for, realized the row of AMOLED is driven with minimum area to each capable shift register structure compact, stable performance that drives; Thereby integrated gate drive circuitry on array base palte effectively; And need not connect extra drive IC at substrate edges, and reduced the layout area of circuit as far as possible, realized that the height of driving circuit is integrated; Simplified the complexity of peripheral drive circuit among the present invention; Having saved material and preparation technology simultaneously, obviously reduced process time and production cost, is the optimal selection that realizes that high resolution A MOLED shows.
Shift register of the present invention and driving method, gate drivers not only go for also going among the TFT-LCD as gate driving on the AMOLED display.
Above embodiment only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (12)
1. a shift register is characterized in that, said shift register comprises:
Load module sends input signal according to the signal of the signal of signal input part input and the input of first clock signal terminal drawing-die piece that makes progress;
Control module resets; Link to each other with said load module and reseting module, transmit control signal to reseting module according to the signal of first level signal, second level signal, the input of first clock signal terminal, the signal and the said input signal of second clock signal end input;
Reseting module links to each other with said control module and the output terminal of resetting, and according to the said control signal and first level signal said output terminal is resetted;
Output module links to each other with said load module and output terminal, sends the output signal according to signal and said second level signal that said load module sends to said output terminal.
2. shift register as claimed in claim 1 is characterized in that, said output module comprises the transistor seconds and first electric capacity, and the source electrode of transistor seconds connects the second clock signal end, and drain electrode connects output terminal at the corresponding levels, and grid connects the first level node; A pole plate of first electric capacity connects the first level node, and another pole plate connects the drain electrode of transistor seconds.
3. shift register as claimed in claim 2; It is characterized in that said reseting module comprises the first transistor and second electric capacity, the source electrode of the first transistor connects first level signal; Drain electrode connects the output terminal of shift register at the corresponding levels, and grid connects the second level node; A pole plate of second electric capacity connects the second level node, and another pole plate connects first level signal.
4. shift register as claimed in claim 3 is characterized in that said load module comprises the 3rd transistor, and the 3rd transistorized source electrode connects input end, and drain electrode connects the first level node, and grid connects first clock signal terminal.
5. shift register as claimed in claim 4; It is characterized in that the said control module that resets comprises the 4th, the 5th, the 6th and the 7th transistor, the 4th transistor drain connects second level signal; Grid connects first clock signal terminal, and source electrode connects the 6th transistor drain; Perhaps, the 4th transistor drain is connected second level signal simultaneously with grid, and source electrode connects the 6th transistor drain; The 5th transistorized source electrode connects first level signal, and grid connects the first level node, and drain electrode connects the 7th transistorized source electrode; The 6th transistorized source electrode connects the second level node, and drain electrode connects the 4th transistorized source electrode, and grid connects first clock signal terminal; The 7th transistorized source electrode connects the 5th transistor drain, and drain electrode connects the second level node, and grid connects the second clock signal end.
6. shift register according to claim 5 is characterized in that, said first to the 7th transistor all is the P transistor npn npn or all is the N transistor npn npn.
7. shift register according to claim 6 is characterized in that, when all being the P transistor npn npn, first level signal is a high level signal, and second level signal is a low level signal; When all being the N transistor npn npn, first level signal is a low level signal, and second level signal is a high level signal.
8. shift register according to claim 5 is characterized in that, said first to the 7th transistor is TFT.
9. shift register according to claim 8 is characterized in that, the TFT that each pixel cell is corresponding on said first to the 7th transistorized TFT and the array base palte adopts identical technology to form simultaneously.
10. gate drivers; It is characterized in that; Said gate drivers comprise a plurality of cascades like each described shift register among the claim 1-9; First clock signal terminal of each grade shift register and second clock signal end connect the clock signal of two anti-phases respectively, and the connection of two clock signal terminals of adjacent level is opposite simultaneously; The input end of each grade connects the output terminal of upper level, with the output of the upper level input as the corresponding levels; The input termination initial input signal of the first order, the output of each grade is as the control signal of corresponding row grid.
11. a display device is characterized in that, said display device comprises: gate drivers as claimed in claim 10.
12. the driving method of a shift register is applied to the described shift register of arbitrary claim among the claim 1-9, it is characterized in that the method comprising the steps of:
Signal in the input end input is in the low level cycle; The signal of first clock signal terminal input is a low level; The signal of second clock signal end input is a high level; The control module that resets is sent drive signal to reseting module, and reseting module resets to output terminal, output terminal output high level signal;
In the next clock period; The signal of the signal of input end input and the input of first clock signal terminal is high level; The signal of second clock signal end input is a low level; Output module sends the output signal to output terminal, and the control module that resets is sent cut-off signals to reseting module, output terminal output low level signal;
In next clock period again; The signal of input end input is a high level; The signal of first clock signal terminal input is a low level, and the signal of second clock signal end input is a high level, and the control module that resets is sent drive signal to reseting module; Reseting module resets to output terminal, output terminal output high level signal.
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| CN (1) | CN102831861B (en) |
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| CN103761938A (en) * | 2013-02-01 | 2014-04-30 | 京东方科技集团股份有限公司 | Shifting register units, shifting register, array substrate and display device |
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| CN105304021A (en) * | 2015-11-25 | 2016-02-03 | 上海天马有机发光显示技术有限公司 | Shift register circuit, gate driving circuit, and display panel |
| CN106023901A (en) * | 2016-08-03 | 2016-10-12 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| WO2017219763A1 (en) * | 2016-06-23 | 2017-12-28 | 京东方科技集团股份有限公司 | Goa signal determining circuit and determining method, gate driving circuit, and display device |
| CN107945742A (en) * | 2016-10-12 | 2018-04-20 | 上海和辉光电有限公司 | Scan drive cell, scan drive circuit and display panel |
| CN108039150A (en) * | 2017-11-16 | 2018-05-15 | 武汉华星光电半导体显示技术有限公司 | Shift register circuit and shifting deposit unit |
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| CN105989797B (en) * | 2015-02-06 | 2018-10-02 | 上海和辉光电有限公司 | Scan control line drive module and display device |
| CN108630163A (en) * | 2018-05-10 | 2018-10-09 | 武汉华星光电半导体显示技术有限公司 | A kind of driving circuit |
| CN110767177A (en) * | 2019-10-29 | 2020-02-07 | 昆山国显光电有限公司 | Scanning circuit, driving method thereof, display panel and display device |
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| WO2020199284A1 (en) * | 2019-04-04 | 2020-10-08 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
| CN112150971A (en) * | 2019-06-26 | 2020-12-29 | 陕西坤同半导体科技有限公司 | Shift register circuit of active matrix organic light emitting display and display thereof |
| CN113658562A (en) * | 2021-08-23 | 2021-11-16 | 杭州领挚科技有限公司 | Shift register circuit |
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| CN103761938A (en) * | 2013-02-01 | 2014-04-30 | 京东方科技集团股份有限公司 | Shifting register units, shifting register, array substrate and display device |
| WO2014117433A1 (en) * | 2013-02-01 | 2014-08-07 | 京东方科技集团股份有限公司 | Shift register units, shift register, array substrate, and display device |
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| WO2015058553A1 (en) * | 2013-10-23 | 2015-04-30 | 京东方科技集团股份有限公司 | Shift register unit, goa circuit, array substrate and display device |
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| US9905192B2 (en) | 2015-01-20 | 2018-02-27 | Boe Technology Group Co., Ltd. | GOA unit and driving method, GOA circuit and display device |
| CN104537977A (en) * | 2015-01-20 | 2015-04-22 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) unit and driving method, GOA circuit and display device |
| WO2016115782A1 (en) * | 2015-01-20 | 2016-07-28 | 京东方科技集团股份有限公司 | Goa unit and driving method, goa circuit and display device |
| CN104575396A (en) * | 2015-02-05 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit and drive method thereof and grid scanning circuit |
| US9818339B2 (en) | 2015-02-05 | 2017-11-14 | Boe Technology Group Co., Ltd. | Shift register unit and method of driving the same, gate scanning circuit |
| CN105989797B (en) * | 2015-02-06 | 2018-10-02 | 上海和辉光电有限公司 | Scan control line drive module and display device |
| CN104616617B (en) * | 2015-03-09 | 2017-03-22 | 京东方科技集团股份有限公司 | Shifting register and drive method thereof as well as grid drive circuit and display device |
| CN104616617A (en) * | 2015-03-09 | 2015-05-13 | 京东方科技集团股份有限公司 | Shifting register and drive method thereof as well as grid drive circuit and display device |
| CN105096823A (en) * | 2015-07-16 | 2015-11-25 | 上海和辉光电有限公司 | Organic light-emitting display device and scanning drive circuit thereof |
| CN105304021A (en) * | 2015-11-25 | 2016-02-03 | 上海天马有机发光显示技术有限公司 | Shift register circuit, gate driving circuit, and display panel |
| WO2017219763A1 (en) * | 2016-06-23 | 2017-12-28 | 京东方科技集团股份有限公司 | Goa signal determining circuit and determining method, gate driving circuit, and display device |
| US10235919B2 (en) | 2016-06-23 | 2019-03-19 | Boe Technology Group Co., Ltd. | GOA signal determining circuit, determining method, gate driver circuit and display device |
| CN106023901B (en) * | 2016-08-03 | 2018-07-17 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
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| US10777149B2 (en) | 2018-05-10 | 2020-09-15 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Driving circuit |
| CN108630163A (en) * | 2018-05-10 | 2018-10-09 | 武汉华星光电半导体显示技术有限公司 | A kind of driving circuit |
| WO2020199284A1 (en) * | 2019-04-04 | 2020-10-08 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
| CN112150971A (en) * | 2019-06-26 | 2020-12-29 | 陕西坤同半导体科技有限公司 | Shift register circuit of active matrix organic light emitting display and display thereof |
| CN110767177A (en) * | 2019-10-29 | 2020-02-07 | 昆山国显光电有限公司 | Scanning circuit, driving method thereof, display panel and display device |
| CN110767177B (en) * | 2019-10-29 | 2021-08-20 | 昆山国显光电有限公司 | Scanning circuit, driving method thereof, display panel and display device |
| CN113658562A (en) * | 2021-08-23 | 2021-11-16 | 杭州领挚科技有限公司 | Shift register circuit |
| CN113658562B (en) * | 2021-08-23 | 2023-02-17 | 杭州领挚科技有限公司 | Shift register circuit |
| CN115035871A (en) * | 2022-06-28 | 2022-09-09 | 上海中航光电子有限公司 | Display panel and display device |
| CN115035871B (en) * | 2022-06-28 | 2024-04-05 | 上海中航光电子有限公司 | Display panel and display device |
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