CN1783044A - On-chip system - Google Patents
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- CN1783044A CN1783044A CN 200410096178 CN200410096178A CN1783044A CN 1783044 A CN1783044 A CN 1783044A CN 200410096178 CN200410096178 CN 200410096178 CN 200410096178 A CN200410096178 A CN 200410096178A CN 1783044 A CN1783044 A CN 1783044A
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Abstract
The on-chip system includes several functional modules connected with internal bus including two independent transmission channels, including one control/state channel for transmitting control/state information and one data channel for transmitting other data except control/state information. Each of the control/state channel and the data channel has separate data bus, address bus and control bus. The kernel of the present invention is to design on-chip system bus in the strategy of separate control/state channel and data channel, which have different topologic structures and communication protocols. The present invention has greatly simplified interface design of functional modules inside the system and increased total system communication bandwidth, and is especially suitable for on-chip system design with compact data interaction.
Description
Technical field
The present invention relates to the semi-conductor chip field, more particularly, relate to a kind of SOC (system on a chip).
Background technology
Along with semiconductor process technology further perfect to the development of deep-submicron and eda tool, chip internal can integrated more, more complicated functional module (being generally the IP module), form a complexity SOC (system on a chip) (System-on-a-chip, SoC).Generally speaking, need to exchange lot of data between each functional module, these exchanges data are finished by communication link, thereby communication link often just becomes the bottleneck of system performance.Whether the common share communication link can be divided into point-to-point mode and bus mode to communication link according to functional module.If each functional module of internal system utilizes the common share communication link to connect, the framework of this system just is based on bus mode.Each functional module based on bus connecting mode has identical bus interface, and the system architecture of composition is simple, is easy to expansion, is convenient to the design reuse of functional module.Exactly because bus-structured these advantages, present SOC (system on a chip) has adopted bus structure basically.
Existing bus-structured SOC (system on a chip) carries out adopting single pass mode usually when interconnected with bus, and promptly all functions module all uses identical bus resource (comprising control bus, address bus and data bus etc.) to transmit various types of data.
In fact, the data by the data bus transmission can be divided into two classes between inner each functional module of SOC (system on a chip): control status information and other data.The control here status information be meant and normally be stored in the control information data and the status information data of operation of those control function module and state in the control register and status register of functional module inside.Therefore, control the transmission of status information be register manipulation basically, its operating frequency is low, the address is discontinuous.Other data here are meant the data of transmitting except on the external data bus of control status information, and the transmission of other data is very frequent, mainly uses the sudden transmission mode, and the efficient of these data transmission directly influences the performance of system.
As previously mentioned, in adopting the bus-structured SOC (system on a chip) of single-channel mode, control status information and other data all transmit by same data bus, and use same control bus and address bus.The bandwidth of this data bus is exactly the maximum communication bandwidth of total system, if control status information and other data use same data bus to transmit, need swap data continually between each functional module of internal system, when the maximum communication bandwidth of total system requirement surpassed the bandwidth of this data bus, internal bus will become communication performance bottleneck.Particularly when a plurality of functional modules are competed same bus resource, central arbiter is each only can to allow a functional module to use this resource, other functional module must be waited for, the functional module that has need be waited for the long time in order to obtain the bus right to use, the insertion of a large amount of latent periods can prolong the working time of system, reduces the performance of system greatly.
Therefore, just need a kind of new SOC (system on a chip) internal bus, can be to data of different types with different transmission channels.
Summary of the invention
The objective of the invention is to overcome the shortcoming and defect of prior art and a kind of new SOC (system on a chip) is provided, data of different types is adopted different transmission channels.
SOC (system on a chip) provided by the invention comprises a plurality of functional modules, connects with internal bus between described a plurality of functional modules, and described internal bus comprises independently two transmission channels, for:
Be used to transmit the control/stator channel of control/status information; With
Be used to transmit the data channel of other data except that control/status information;
Described control/stator channel and data channel include data line, address wire and control line separately.
Control/the stator channel of described SOC (system on a chip) is the master-slave equipment structure, and one in a plurality of functional modules that described control/stator channel connected is main equipment, and the functional module outside the main equipment is as slave unit.The data line of described control/stator channel comprises: between write data line that all slave units are shared and slave unit and the main equipment read data line.The address wire of described control/stator channel is shared by all slave units.The control line of described control/stator channel comprises: by each slave unit to the interrupt request singal line of main equipment, by gating signal line and all the slave unit shared command signal line of main equipment to each slave unit.
The data channel of described SOC (system on a chip) is the master-slave equipment structure, and a plurality of functional modules that described data channel connected comprise at least one main equipment and at least one slave unit; Described address wire and described control line are connected to described slave unit from described main equipment; Described data line comprises the write data line and the read data line of separation, and the write data line is connected to described slave unit from described main equipment, described read data line and be connected to described main equipment from described slave unit.
Described data channel comprises a plurality of main equipments, also comprise first MUX and the moderator related in the described data channel with slave unit, described moderator is arbitrated computing according to address and control signal that described a plurality of main equipments send, and the bus right to use of distributing described a plurality of main equipments according to arbitration result, described moderator also is connected with described first MUX and controls described first MUX signal from described a plurality of main equipments is selected.
Described data channel comprises a plurality of slave units, also comprises second MUX related with main equipment in the described data channel, and described second MUX is selected the signal from described a plurality of slave units.Described second MUX is connected with described moderator, and controls described second MUX by described moderator the signal from described a plurality of slave units is selected.Described moderator is for adopting the moderator of robin scheduling algorithm.
The present invention has following beneficial effect:
1. core of the present invention is that the strategy that adopts control/stator channel and data channel to separate designs the SOC (system on a chip) bus, two passages according to the design of internal system two class data different characteristics have different topological structures and communication protocol, the Interface design of inner each functional module of simplified system greatly, the communication bandwidth that the increase system is total is fit to the design of the intensive on-chip system chip of data interaction very much.
2. control/stator channel of the present invention separates with data channel, and two passages use different address space and data line, can simplify the address decoding circuitry design, avoids because the compromise that two class different pieces of information host-host protocol differences are done.
3, control/stator channel of the present invention and data channel all adopt master and slave equipment handshake method to come swap data.Because control status register is positioned at different address spaces with other data, can distinguish encoding and decoding, is convenient to simplify the design of each module interface logic.
4. data channel of the present invention is used the related moderator of distributed slave unit, only the slave unit end of sharing at a plurality of main equipments just need design corresponding moderator, internal system allows a plurality of main equipment-slave units to communicating simultaneously, and design can greatly improve internal system data communication bandwidth like this.
5. data channel of the present invention uses simple Handshake Protocol to finish data transmission, allows the slow functional module of response speed to insert latent period in the process of data transmission.This method for designing helps the design reuse of functional module, is convenient to the functional module that performance is different and is integrated in the System on Chip/SoC.
Description of drawings
Fig. 1 is the one-piece construction synoptic diagram of SOC (system on a chip) of the present invention;
Fig. 2 is the structural representation of control/stator channel in the SOC (system on a chip) of the present invention;
Fig. 3 is the read operation sequential chart of control/stator channel in the SOC (system on a chip) of the present invention;
Fig. 4 is the write operation sequential chart of control/stator channel in the SOC (system on a chip) of the present invention;
Fig. 5 is the structural representation of data channel in the SOC (system on a chip) of the present invention;
Fig. 6 is the read operation sequential chart of data channel in the SOC (system on a chip) of the present invention;
Fig. 7 is the write operation sequential chart of data channel in the SOC (system on a chip) of the present invention;
Fig. 8 is the structural representation of moderator in the data channel in the SOC (system on a chip) of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Generally included a plurality of functional modules in the SOC (system on a chip), each functional module all has bus interface, utilizes the internal bus of SOC (system on a chip) to couple together.In the present invention embodiment as shown in Figure 1, SOC (system on a chip) comprises functional module 0～5 (can expand) and control desk.Control desk is a special functional module of SOC (system on a chip), often serves as by an Embedded RISC CPU or with the functional module that RISC CPU has identical or a similar functions.In other possible embodiment, control desk also can be integrated in other functional module.Can know that from following description this control desk will be as the main equipment in control/stator channel of the present invention.
As shown in Figure 1, in the present invention, the internal bus of SOC (system on a chip) comprises independently two passages: control/stator channel 10 and data channel 20.Functional module 0～5 and control desk utilization control/stator channel 10 and data channel 20 couple together.Control/stator channel 10 be used for transmitting SOC (system on a chip) control status information data, and data channel 20 be used for transmitting SOC (system on a chip) except that control other data the status information data.Because control desk only is used for control/stator channel 10, therefore be not connected on the data channel 20.For control/stator channel 10 and data channel 20, each passage all includes data line, address wire and the control line that is used to transmit corresponding data, and this will describe in detail respectively hereinafter.
Control/stator channel
Fig. 2 shows the structure of control/stator channel among the present invention, comprising the data line that control/stator channel is arranged, address wire and control line.
As shown in Figure 2, control/stator channel adopts the master-slave equipment structure, promptly adopts the master-slave equipment handshake method to come swap data between the functional module.On control/stator channel, have only a main equipment in a plurality of functional modules, other functional module is slave unit.This main equipment is exactly the control desk among Fig. 1 and Fig. 2, and slave unit is a functional module 0～5.
In Fig. 2, the address wire of control/stator channel illustrates with CAddr, is connected between control desk and each functional module 0～5 as slave unit, and is shared by each functional module 0～5 as slave unit.Because the data that control/stator channel transmitted are control/status information, its Action Target is the status register and the control register of each functional module 0～5 inside, does not therefore need too wide address wire.In one embodiment of the invention, the address wire CAddr width of control/stator channel is 5, register that can 32 different addresses of addressing.Narrower address wire width can be simplified the difficulty of decoding scheme design, accelerates circuit response time.But the width that should be appreciated that address wire CAddr also can be done other variation according to user's actual needs.
In Fig. 2, the control line of control/stator channel comprises: command signal line is read and write enable signal line CR/Wn, gating signal line CSel, interrupt request singal line IRQ in other words.
The direction of interrupt request singal line IRQ is served as reasons each functional module 0～5 as slave unit to control desk, is used to transmit the interrupt request singal that slave unit sends to control desk.In one embodiment, the interrupt request singal high level is effective, when a certain functional module 0～5 need be carried out data interaction with control desk, utilizes this signalisation control desk.In Fig. 2, be used in and add underscore and the numeral number identical after the IRQ and distinguish interrupt request singal line between different slave units and the control desk, as IRQ_0～IRQ_5 with functional module.
The direction of gating signal line CSel be by control desk to each functional module 0～5 as slave unit, be used to transmit the gating signal that control desk sends to slave unit.In one embodiment, gating signal line CSel is that high level is effective.IRQ is similar with the interrupt request singal line, distinguishes the gating signal line of different slave units in Fig. 2 with CSel_0～CSel_5.
It is shared by each slave unit that command signal line is read and write enable signal line CR/Wn in other words, is used to transmit the read-write operation order that control desk sends to each slave unit.In one embodiment, the high level of read-write enable signal line CR/Wn is represented the read operation order, and low level is represented the write operation order.When this signal was high level (logical one), control desk was read the internal register through the functional module of gating signal line CSel gating; When this signal was low level (logical zero), control desk was to through the internal register write data of the functional module of gating signal line CSel gating.
As shown in Figure 2, similar to the data line of SOC (system on a chip) in the prior art, the data line of control/stator channel also is made up of the write data line CDadaOut and the read data line CDataIn that separate.In Fig. 2, write data line CDadaOut is shared by each slave unit, and its direction is to the functional module 0～5 as slave unit by control desk.The direction of read data line CDataIn is served as reasons each functional module 0～5 as slave unit to control desk; Each functional module 0～5 as slave unit all has read data line CDataIn to be connected with control desk as main equipment respectively, in Fig. 2, be used in and add the read data line that underscore and the numeral number identical with functional module are distinguished different slave units and control desk after the CDataIn, as CDataIn_0～CDataIn_5.Because control/stator channel only is used for transmitting the control/status information of each functional module, does not need too wide data line.In one embodiment of the invention, the data line width of control/stator channel is 32, but should be appreciated that the width of data line also can do other variation according to user's actual needs.
According to aforementioned to control/stator channel description and Fig. 2 as can be known, for the slave unit in each control/stator channel, the functional module among Fig. 2 0～5 for example, all be connected with data line, address wire and control line in the control/stator channel in a like fashion, therefore each slave unit all can have identical bus interface, and this is that the functional module that is convenient to very much SOC (system on a chip) is expanded.For example in Fig. 2, SOC (system on a chip) can expand to functional module N-1 and the functional module N (not shown) that has as slave unit, and N can be any slave unit number that meets user's request.And, functional module N-1 has identical bus interface with functional module N with functional module 0～5, this bus interface except with control/stator channel in shared read-write enable signal line CR/Wn, the address wire CAddr of slave unit with write data line CDadaOut is connected, also be connected with control desk by gating signal line CSel_ (N-1), CSel_N and interrupt request singal line IRQ_ (N-1), IRQ_N respectively, this is all consistent with functional module 0～5.
Usually having only two kinds of operations of reading and writing on the control/stator channel, all is to be responsible for initiation by control desk.Control desk is when the slave unit of selecting to want to operate, utilize gating signal line CSel to notify this functional module, send read-write operation order CR/Wn then, obtain the data that need from the read data line CDataIn of control/stator channel, perhaps data are delivered on the write data line CDadaOut of control/stator channel.
Fig. 3 shows the read operation sequential chart of control/stator channel.As shown in Figure 3, in the clock period 2 of clock signal C lk, control desk by on draw the level of gating signal line CSel to select to want the slave unit of reading of data, draw the level of read-write enable signal line CR/Wn to send the read operation order then, send by the address Addr0 of read register by address wire CAddr simultaneously.In the clock period 3 of clock signal C lk, read data line CDataIn in the control/stator channel of the slave unit that is addressed driving oneself delivers to the data Data0 on the Addr0 of address on the read data line CDataIn of control/stator channel.When continuous read operation, can also send the address Addr1 of reading of data next time simultaneously at clock period 3 control desk, slave unit is delivered to the data Data1 on the Addr1 of this address on the read data bus of control/stator channel in the clock period 4.The rest may be inferred for the sequential of a plurality of read data operations, comprises address Addr2 and data Data2, comprised three data read cycles among Fig. 3 altogether.
Fig. 4 shows the write operation sequential chart of control/stator channel.As shown in Figure 4, in the clock period 2 of clock signal C lk, control desk by on draw the level of gating signal line CSel to select to want the module of reading of data, the level of drop-down read-write enable signal line CR/Wn sends the read operation order, and send the address Addr0 that is write register by address wire CAddr, the write data line CDadaOut of drive controlling/stator channel simultaneously.Data write operation was finished in a clock period.The rest may be inferred for the sequential of a plurality of data writing operation, comprises address Addr1 and Addr2 and corresponding and data Data1 and Data2, comprised three data write cycles again among Fig. 4 altogether.
Data channel
In the present invention, on-chip system chip inner utilization data channel exchanges other data.In order to improve the performance of system, must improve the bandwidth of data communication as far as possible, reduce time delay of data transmission simultaneously.In the present invention, data channel also adopts the master-slave equipment structure, promptly adopts the master-slave equipment handshake method to come swap data between the functional module, and can support a plurality of bus masters.When SOC (system on a chip) inside comprises a plurality of main equipment, adopt distributed arbitration program mechanism, moderator is related with slave unit.Wherein, address wire, control line signal that main equipment comes enter moderator, and moderator is according to the entitlement of the algorithm assigns bus of user's selection.Moderator produces the control signal of the MUX related with this slave unit and control signals of the related MUX of relevant main equipment (operating the main equipment of this slave unit) with all.Similar to the data line of SOC (system on a chip) in the prior art, the data line of data channel also is made up of the write data line and the read data line that separate, and wherein the direction of write data line is from the main equipment to the slave unit, and the direction of read data line is from the slave unit to the main equipment.
The datapath structure of a SOC (system on a chip) has been shown in the embodiment of Fig. 5, in this embodiment, SOC (system on a chip) inside comprises two bus masters and two bus slaves, be respectively main equipment 0 and main equipment 1 and slave unit 0 and slave unit 1, two main equipments 0 and main equipment 1 all can be operated two slave units 0 and slave unit 1, wherein, main equipment among Fig. 5 and slave unit can be the arbitrary functional modules (comprising control desk) among Fig. 1.
In Fig. 5, main equipment 0 is connected with its address wire 501, control line 502 and write data line 503, and main equipment 1 is connected with its address wire 501, control line 502 and write data line 503.Two slave units 0 and 1 all are associated with a MUX and a moderator respectively, and the first MUX S0 is related with moderator 0 and slave unit 0, and the first MUX S1 is related with moderator 1 and slave unit 1.In addition, for the data of selecting to return from a plurality of slave units, two main equipment ends also are associated with a MUX respectively, and wherein, the second MUX M0 is related with main equipment 0, and the second MUX M1 is related with main equipment 1.
As shown in Figure 5, the address wire in the data channel 501 and 511, control line 502 and 512 and write data line 503 and 513 all be connected to slave unit 0 and 1 from main equipment 0 and 1.From address wire 501, control line 502 and write data line 503 signals of main equipment 0 and after address wire 511, control line 512 and write data line 513 signal demands of main equipment 1 are selected through the first MUX S0 wherein lead up to address wire 51, control line 52 and write data line 53 are sent into slave unit 0; Same, send into slave unit 1 from address wire 501, control line 502 and write data line 503 signals of main equipment 0 and from will wherein leading up to address wire 51 ', control line 52 ' and write data line 53 ' after address wire 511, control line 512 and write data line 513 signal demands of main equipment 1 are selected through the first MUX S1.
As shown in Figure 5, the first MUX S0 and S1 select the signal of time institute's foundation to come from moderator 0 and moderator 1 respectively, wherein, moderator 0 is connected with main equipment to the first MUX S0 and selects signal wire 505, and moderator 1 is connected with main equipment to the first MUX S1 and selects signal wire 515.With first MUX S0 and the moderator 0 related with slave unit 0 is example, enter moderator 0 from address wire 501 and 511, control line 502 and 512 signals of two main equipments 0 and 1, moderator 0 is according to the entitlement of the arbitration algorithm distribution bus of user's selection; Moderator 0 produces a main equipment and selects signal and select signal wire 505 to be sent to the first MUX S0 by main equipment, and the first MUX S0 selects signal that address wire, control line and the write data line signal of main equipment 0 or main equipment 1 are sent into slave unit 0 according to its main equipment that receives.Identical with moderator 0 with the first MUX S0 with the working method of related first MUX S1 of slave unit 1 and moderator 1, wherein moderator 1 produces a main equipment and selects signal and select signal wire 515 to be sent to the first MUX S1 by main equipment.
Read data line 504 in the data channel and 514 is connected to main equipment 0 and main equipment 1 from slave unit 0 and slave unit 1.Wherein, the read data line 504 of slave unit 0 and the read data line 514 of slave unit 1 all be connected to the second MUX M0 related with main equipment 0 and and the second related MUX M1 of main equipment 1, will wherein lead up to read data line 54 and read data line 54 ' after selecting by the second MUX M0 and M1 to be sent to main equipment 0 and main equipment 1.
Slave unit in the data channel transfers to main equipment by acknowledge signal line from slave unit to the answer signal of main equipment.Wherein, the answer signal of slave unit 0 transfers to second MUX M0 and the M1 respectively by its acknowledge signal line 500, and the answer signal of slave unit 1 transfers to second MUX M0 and the M1 respectively by its acknowledge signal line 510.The second MUX M0 transfers to main equipment 0, the second MUX M1 to after selecting from the answer signal of slave unit 0 and slave unit 1 road answer signal wherein being transferred to main equipment 1 by acknowledge signal line 50 ' to one road answer signal of inciting somebody to action after selecting from the answer signal of slave unit 0 and slave unit 1 wherein by acknowledge signal line 50.
As shown in Figure 5, moderator 0 and moderator 1 also will send bus use allowance signal Gnt to the second MUX M0 and the second MUX M1 after arbitration.Therefore, moderator 0 connects respectively between the second MUX M0 and the second MUX M1 by the bus use permits signal wire 508 and 509, and moderator 1 connects respectively between the second MUX M0 and the second MUX M1 by the bus use permits signal wire 518 and 519.The second MUX M0 selects bus to use to permit the bus of leading up in the signal wire 508 and 518 to use and permit signal wire 58 and send to main equipment 0, the second MUX M1 and select bus to use to permit the bus of leading up in the signal wire 509 and 519 to use and permit signal wire 59 and send to main equipment 1.
As previously shown, the second MUX M0 and the second MUX M1 need use the signal of permitting on the signal wire 508 and 518 and 509 and 519 to select to read data line 504 and 514, acknowledge signal line 500 and 510, bus, so that road signal wherein is transferred to main equipment 0 and main equipment 1.The second MUX M0 and the second MUX M1 select the signal of time institute's foundation also to come from moderator 0 and moderator 1 respectively.As shown in Figure 5, moderator 0 is connected with slave unit selection signal wire 506 and 507 to the first MUX M0 and the second MUX M1 respectively, so that send slave unit selection signal by moderator 0 to the first MUX M0 and the second MUX M1; Moderator 1 is connected with slave unit selection signal wire 516 and 517 to the first MUX M0 and the second MUX M1 respectively, so that send slave unit selection signal by moderator 1 to the first MUX M0 and the second MUX M1.The first MUX M0 selects signal to carry out selection operation according to the slave unit that moderator 0 selects signal wire 506 and moderator 1 to select signal wire 516 to send by slave unit by slave unit, and the slave unit that the second MUX M1 selects signal wire 507 and moderator 1 to select signal wire 517 to send by slave unit according to moderator 0 by slave unit selects signal to carry out selection operation.
In data channel,, therefore need the address wire and the data line of broad because the data that it transmitted are more than control/stator channel.In one embodiment of the invention, the address wire 501 of data channel and 511 width are 32, different address spaces that can addressing 4GByte, the width of the data line of data channel (comprising read data line 504,514 and write data line 503,513) is 128.But the width that should be appreciated that data channel address wire and data line also can be done other variation according to user's actual needs.
In Fig. 5, the control line 501 of data channel and 511 direction are slave unit operated from the main equipment to the main equipment, and the signal that it transmitted comprises: bus uses request signal Req, bus cycles marking signal Frame, address effective marker signal AValid, sudden transmission length BSize, command signal to read and write in other words that byte enable sign DataBE, last write data marking signal WLast, main equipment can receive read data sign RReady on enable signal R/Wn, write data effective marker signal WValid, the data bus.Wherein,
Bus is used request signal Req to be used to transmit main equipment and is used request to the bus that slave unit sends.In one embodiment, bus uses request Req effective as high level, when a certain main equipment need use bus transfer data, utilizes this signalisation slave unit.
Bus cycles marking signal Frame is used for transmission primaries bus cycles sign.In one embodiment, bus cycles marking signal Frame is that high level is effective.
Address effective marker signal AValid is used for the address effective marker of transmission primaries bus operation request.In one embodiment, address effective marker signal AValid is that high level is effective.
Sudden transmission length BSize is used for the sudden transmission length of transmission primaries bus operation.In one embodiment, sudden transmission length BSize uses 8 highway widths, and one time data read-write operation can transmit 256 data at most.
Command signal line is read and write enable signal line R/Wn in other words and is used to transmit the read-write operation order that main equipment sends to each slave unit.In one embodiment, the high level of read-write enable signal line R/Wn is represented the read operation order, and low level is represented the write operation order.
Write data effective marker signal WValid is used for the data effective marker on the total line write transactions write data bus of transmission primaries.In one embodiment, write data effective marker signal WValid is that high level is effective.
Byte enable sign DataBE is used for respective byte effective marker on transmission primaries bus operation write data line and the read data line on the data bus.In one embodiment, byte enable sign DataBE uses 16 highway widths, represents respectively whether each byte data is effective in the data transfer.In one embodiment, byte enable sign DataBE is that high level is effective, DataBE[0] represent that byte 0 is effective, DataBE[1 for high level] represent that byte 1 is effective for high level, by that analogy.
Last write data marking signal WLast is used for the sign of total last data writing operation of line write transactions of transmission primaries.In one embodiment, last write data marking signal WLast is that high level is effective.
Main equipment can receive read data sign RReady and be used for the ready sign of transmission primaries bus read operation main equipment reception read data.In one embodiment, can to receive read data sign RReady be that high level is effective to main equipment.
In data channel, the answer signal of acknowledge signal line 500 and 510 transmission comprises: bus operation answer signal Ack, slave unit can receive Data Labels WReady, read data effective marker RValid, last read data sign RLast.Wherein,
Bus operation answer signal Ack is used for transmission primaries bus cycles answer logo, when a slave unit can respond the request of its main equipment of addressing, utilizes this signalisation main equipment.In one embodiment, bus operation answer signal Ack is that high level is effective.
Slave unit can receive Data Labels WReady and be used for the total line write transactions ready flag of transmission primaries, when a slave unit can receive data on the write bus, utilizes this signalisation main equipment.In one embodiment, can to receive Data Labels WReady be that high level is effective to slave unit.
Read data effective marker RValid is used for transmission primaries bus read operation data effective marker, when a slave unit is delivered to valid data on the read data bus, utilizes this signalisation main equipment.In one embodiment, read data effective marker RValid is that high level is effective.
Last read data sign RLast is used for last Data Labels of transmission primaries bus read operation, when a slave unit is delivered to last data on the read data bus, utilizes this signalisation main equipment.In one embodiment, last read data sign RLast is that high level is effective.
According to aforementioned to the data passage description and Fig. 5 as can be known, for main equipment in the data channel and slave unit, all be connected with data line, address wire and control line in the data channel in a like fashion, therefore each main equipment or slave unit all can have identical bus interface, and this is that the functional module that is convenient to very much SOC (system on a chip) is expanded.
Usually having only two kinds of operations of reading and writing on the data channel, all is to be responsible for initiation by main equipment.When main equipment need use bus, utilize bus to use request signal Req to initiate bus and use request, the bus use that the slave unit utilization moderator related with it sends is permitted signal Gnt and is replied.Main equipment utilizes bus cycles marking signal Frame to represent bus operation one time, send address Addr, address valid signal AValid and command signal R/Wn simultaneously, slave unit determines whether to respond this operation by decoding, utilizes bus operation answer signal Ack notice main equipment.If respond this bus operation, slave unit is perhaps delivered to valid data on the read data line according to the data on the command signal R/Wn reception write data line.
Fig. 6 shows the read operation sequential chart of data channel.As shown in Figure 6, on clock period 1 main equipment, draw the Req signal to send the data channel operation requests.On clock period 2 moderator, draw the Gnt signal to agree that this main equipment uses data channel.On clock period 3 main equipment, draw the Frame signal indication to begin a data channel operation, on draw the R/Wn signal to send the data channel read command, send the lowest address of this read operation, on draw AValid signal indication address effective, send the length BSize of this sudden transmission simultaneously.On clock period 4 main equipment, draw the RReady signal indication to enter the ready (RDY) state, can receive the read data of slave unit.Main equipment is determined those invalid data bytes of shielding by the suitable position that is provided with among the DataBE.At clock period 5 slave unit by this read operation of address decoding decision response, on draw the Ack signal to carry out bus acknowledge.Because internal data also is not ready for, therefore continuing to keep RValid is zero, inserts latent period.Clock period 6 and 7 is the latent period that slave unit inserts.Drawing the RValid signal to begin to transmit data on the read data line Rdata of data channel on clock period 8 slave unit, effectively the cycle is a data transfer cycle simultaneously for RReady and RValid.Have 8 data transfer cycles (BSize=8) in the accompanying drawing 6.Clock period 15 is last data transfer cycle, main equipment by on draw RLast to represent that this cycle is last read data cycle.Finish in this read operation of the drop-down Frame marker of clock period 16 main equipment, simultaneously drop-down AValid, RReady and RLast signal.Drop-down Ack of slave unit and RValid signal return to idle condition.
Fig. 7 shows the write operation sequential chart of data channel.As shown in Figure 7, on clock period 1 main equipment, draw the Req signal to send the data channel operation requests.On clock period 2 moderator, draw the Gnt signal to agree that this main equipment uses data channel.On clock period 3 main equipment, draw the Frame signal indication to begin a data channel operation, drop-down R/Wn signal sends the data channel write order, send the lowest address of this write operation, on draw AValid signal indication address effective, send the length BSize of this sudden transmission simultaneously.Different with the data channel read operation, main equipment is sent first data that will transmit, and on draw the WValid signal.Can mask some bytes by the suitable position that is provided with among the DataBE.At clock period 5 slave unit by this read operation of address decoding decision response, on draw the Ack signal to carry out bus acknowledge.Because the slave unit inner space has been ready, can receive the data on the write data line Wdata, on draw the WReady signal.The simultaneously effective cycle of WReady and WValid is a data transfer cycle, and the cycle 5,6,7,8 is data transfer cycle in the accompanying drawing 7.Can not receive the data on the write data line again in clock period 9 slave unit inside, drop-down WReady signal inserts a latent period.Ready in clock period 10 slave unit inner space, can continue to receive the data on the write data line, on draw the WReady signal to begin new data transfer cycle.Clock period 15 is last data transfer cycle, main equipment by on draw WLast to represent that this cycle is for last data write cycle.Finish at this write operation of the drop-down Frame marker of clock period 16 main equipment, simultaneously drop-down AValid, WValid and RWast signal.Drop-down Ack of slave unit and WReady signal return to idle condition.
In order to improve internal system data communication bandwidth, data channel is used the related resolving strategy of slave unit.When if some slave units need respond the operation requests of a plurality of main equipments,, need to use the right to use that moderator distributes this slave unit for fear of the bus operation conflict.In one embodiment, moderator uses the robin scheduling algorithm to decide the operation requests that responds which main equipment.As shown in Figure 8, moderator receive from the Master device operation request of relevant main equipment, according to the priority orders of storing in the priority query in the moderator, request signal queueing logic by moderator inside is selected the highest request signal of current priority, and corresponding master device is made with output control signal formation logic by the arbitration in the moderator and to be replied (for example the bus among Fig. 5 is used and permitted signal 508 and 509), send selection control signal (for example the main equipment of moderator 0 selects signal 505 and slave unit to select signal 506 and 507 among Fig. 5) simultaneously to MUX.When a bus operation was finished, request signal was cancelled, and moderator is resequenced to the priority orders in its priority query, and the main equipment of recent minimum service comes limit priority, and the main equipment that has just obtained service comes lowest priority.Wherein, the N among Fig. 8 is the main equipment number of the same slave unit of operation.
Although be the structure that example illustrates data channel of the present invention only hereinbefore with two main equipments and two slave units, but those skilled in the art can obtain having the embodiment of the data channel of more main equipments and/or more slave units at an easy rate according to foregoing description, also is easy to obtain having still less main equipment and/or the still less embodiment of the data channel of slave unit.For example, clearly, when a main equipment is only arranged in the data channel of SOC (system on a chip), can save first MUX and the moderator of slave unit end; When a slave unit is only arranged in the data channel of SOC (system on a chip), can save second MUX of main equipment end.
In the present invention, can adopt hardware description language (Hardware Description Language HDL) to write, comprehensively, download in FPGA device or the special IC after the emulation, debugging as each functional module of main equipment or slave unit, can realize required on-chip system chip.Perhaps, but each functional module also special IC (ASIC) realize,
The user according to oneself needs designs or select different functional modules for use, can construct high performance, as to be fit to different application special IC.
Claims (10)
1, a kind of SOC (system on a chip) comprises a plurality of functional modules, connects with internal bus between described a plurality of functional modules, it is characterized in that described internal bus comprises independently two transmission channels, for:
Be used to transmit the control/stator channel of control/status information; With
Be used to transmit the data channel of other data except that control/status information;
Described control/stator channel and data channel include data line, address wire and control line separately.
2, SOC (system on a chip) according to claim 1, it is characterized in that, control/the stator channel of described SOC (system on a chip) is the master-slave equipment structure, and one in a plurality of functional modules that described control/stator channel connected is main equipment, and the functional module outside the main equipment is as slave unit.
3, SOC (system on a chip) according to claim 2 is characterized in that, the data line of described control/stator channel comprises:
The write data line that all slave units are shared; With
Between slave unit and the main equipment read data line.
4, SOC (system on a chip) according to claim 1 and 2 is characterized in that, the address wire of described control/stator channel is shared by all slave units.
5, SOC (system on a chip) according to claim 2 is characterized in that, the control line of described control/stator channel comprises:
By the interrupt request singal line of each slave unit to main equipment;
By the gating signal line of main equipment to each slave unit; With
The command signal line that all slave units are shared.
6, SOC (system on a chip) according to claim 1 is characterized in that, the data channel of described SOC (system on a chip) is the master-slave equipment structure, and a plurality of functional modules that described data channel connected comprise at least one main equipment and at least one slave unit; Described address wire and described control line are connected to described slave unit from described main equipment; Described data line comprises the write data line and the read data line of separation, and the write data line is connected to described slave unit from described main equipment, described read data line and be connected to described main equipment from described slave unit.
7, SOC (system on a chip) according to claim 6, it is characterized in that, described data channel comprises a plurality of main equipments, also comprise first MUX and the moderator related in the described data channel with slave unit, described moderator is arbitrated computing according to address and control signal that described a plurality of main equipments send, and the bus right to use of distributing described a plurality of main equipments according to arbitration result, described moderator also is connected with described first MUX and controls described first MUX signal from described a plurality of main equipments is selected.
8, according to claim 6 or 7 described SOC (system on a chip), it is characterized in that, described data channel comprises a plurality of slave units, also comprises second MUX related with main equipment in the described data channel, and described second MUX is selected the signal from described a plurality of slave units.
9, SOC (system on a chip) according to claim 8 is characterized in that, described second MUX is connected with described moderator, and controls described second MUX by described moderator the signal from described a plurality of slave units is selected.
10, SOC (system on a chip) according to claim 7 is characterized in that, described moderator is for adopting the moderator of robin scheduling algorithm.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196819B (en) * | 2006-12-06 | 2010-05-26 | 安凯(广州)微电子技术有限公司 | Method for chip self-adapting start equipment of system on chip |
| CN102364908A (en) * | 2011-10-21 | 2012-02-29 | 深圳航天东方红海特卫星有限公司 | Information transmission system and method based on satellite-borne electronic equipment |
| CN103106113A (en) * | 2013-02-25 | 2013-05-15 | 广东威创视讯科技股份有限公司 | Interrupt event processing method and processing equipment |
| CN103383543A (en) * | 2012-05-02 | 2013-11-06 | 飞思卡尔半导体公司 | System on chip and control module thereof |
| CN105260331A (en) * | 2015-10-09 | 2016-01-20 | 天津国芯科技有限公司 | Dual-bus memory controller |
| CN108304333A (en) * | 2017-12-26 | 2018-07-20 | 中国科学院长春光学精密机械与物理研究所 | A kind of one master and multiple slaves formula bus |
| CN117971743A (en) * | 2024-03-28 | 2024-05-03 | 天津大学四川创新研究院 | Embedded platform synchronous communication system and method based on bus structure |
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2004
- 2004-11-30 CN CNB2004100961787A patent/CN100485648C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196819B (en) * | 2006-12-06 | 2010-05-26 | 安凯(广州)微电子技术有限公司 | Method for chip self-adapting start equipment of system on chip |
| CN102364908A (en) * | 2011-10-21 | 2012-02-29 | 深圳航天东方红海特卫星有限公司 | Information transmission system and method based on satellite-borne electronic equipment |
| CN103383543A (en) * | 2012-05-02 | 2013-11-06 | 飞思卡尔半导体公司 | System on chip and control module thereof |
| CN103106113A (en) * | 2013-02-25 | 2013-05-15 | 广东威创视讯科技股份有限公司 | Interrupt event processing method and processing equipment |
| CN105260331A (en) * | 2015-10-09 | 2016-01-20 | 天津国芯科技有限公司 | Dual-bus memory controller |
| CN105260331B (en) * | 2015-10-09 | 2018-08-28 | 天津国芯科技有限公司 | A kind of dual bus Memory Controller Hub |
| CN108304333A (en) * | 2017-12-26 | 2018-07-20 | 中国科学院长春光学精密机械与物理研究所 | A kind of one master and multiple slaves formula bus |
| CN117971743A (en) * | 2024-03-28 | 2024-05-03 | 天津大学四川创新研究院 | Embedded platform synchronous communication system and method based on bus structure |
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| CN100485648C (en) | 2009-05-06 |
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