CN1746773A - Pattern transferring method of conductive structure - Google Patents
Pattern transferring method of conductive structure Download PDFInfo
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- CN1746773A CN1746773A CN 200410054375 CN200410054375A CN1746773A CN 1746773 A CN1746773 A CN 1746773A CN 200410054375 CN200410054375 CN 200410054375 CN 200410054375 A CN200410054375 A CN 200410054375A CN 1746773 A CN1746773 A CN 1746773A
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Abstract
A method for transferring conductive structure pattern includes providing a semiconductor substrate, forming a conductive layer on it then forming hard mask layer on conductive layer as well as forming a photoetching glue layer (PGL) on hard mask layer, removing partial PGL by each direction link mode to form patterned PGL, using patterned PGL as mask to etch hard mask to form patterned hard mask layer, and using patterned hard mask layer as another mask to remove partial conductive layer for forming patterned conductive layer.
Description
Technical field
The present invention relates to a kind of design transfer method of conductive structure, particularly a kind of design transfer method of utilizing hard mask layer to share photoresist layer.
Background technology
Photoetching (Photolithography) is in the whole semiconductor technology, one of the most very important step, and the complexity of a common technology depends on the photoetching number of times of required process or required mask quantity.In addition, whether the element integrated level of whole semi-conductor industry can continue to depend on also toward littler live width whether the development of photoetching process is smooth.
The ultimate principle of photoetching process is the incident light that utilizes specific wavelength, with the design transfer that has on the mask photoresist to the semiconductor structure, through development with etching after, just can on semiconductor structure, obtain required element or structure.The quality of photoresist, except with the photoperceptivity of photoresist mutually outside the Pass, good photoresist should also possess good tack, etch resistance, and resolution.Basically, this some all with photoresist whether can be complete to carry out design transfer relevant, bad tack or not good etch resistance all will make film under the photoresist when carrying out selective etch, and the error even the failure of design transfer take place.Therefore, the yield rate of the quality of photoresist and technology and degree of accuracy have very confidential relation.
Usually the thickness of photoresist is thin more, and its resolution is good more, but if from the etch resistance of photoresist and the viewpoint of taking precautions against the impurity intrusion, it is thicker that its thickness should be wanted.For instance, general when carrying out the design transfer of polysilicon, need thicker photoresist, avoid the over etching (etch-out) of photoresist behind the etching polysilicon, but thus, just reduced resolution, be unfavorable for the formation and the development of the semiconductor element of reduced size.
Summary of the invention
In view of above-mentioned, in order to reduce the required thickness of photoresist, one of purpose of the present invention is to provide a kind of design transfer method of conductive structure, utilizes a hard mask layer to share the design transfer function of photoresist layer.
Secondly,, another object of the present invention is to provide a kind of design transfer method of grid, successively utilize photoresist layer and hard mask layer, reach the purpose of dwindling component size in order to form the littler conductor element of size.
For reaching above-described purpose, the invention provides a kind of design transfer method (patterning method) of conductive structure, a Semiconductor substrate at first is provided, on Semiconductor substrate, form a conductive layer.On conductive layer, form a hard mask layer (hard mask layer), and on hard mask layer, form a photoresist layer.The photoresist layer that removes part in the isotropic etching mode is to form the photoresist layer of patterning.Photoresist layer with patterning is a mask, and the etching hard mask layer is to form the hard mask layer of patterning.Hard mask layer with patterning is another mask, removes the partially conductive layer to form the conductive layer of patterning.Wherein because the photoresist layer of patterning is used when only be the etching hard mask layer, but the therefore thin photoresist layer of used thickness, the resolution when improving the use photoresist layer, and then reduce the size of the patterned conductive layer of follow-up formation.
Adopt this method can effectively reduce the thickness of photoresist layer, improve the resolution of photoresist layer, and then reduce the size of follow-up formation patterned conductive layer.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 and Fig. 3 are the diagrammatic cross-section of a semiconductor element being implemented according to the present invention.
Label declaration:
10 semiconductor structures
12 conductive layers
14 hard mask layers
16 photoresist layers
Embodiment
According to above-mentioned, the invention provides a kind of design transfer method of grid, a Semiconductor substrate is provided, on Semiconductor substrate, form a polysilicon layer.On polysilicon layer, form a hard mask layer.On hard mask layer, form a photoresist layer.In the isotropic etching mode, remove the photoresist layer of part to expose the part hard mask layer, to remove again the hard mask layer that is exposed out to expose the polysilicon layer of part.After removing the photoresist layer of patterning, remove the polysilicon layer that is exposed out again to form the polysilicon layer of patterning.Remove the hard mask layer of patterning at last.
Fig. 1 and Fig. 3 are the diagrammatic cross-section of a semiconductor element being implemented according to the present invention.With reference to Fig. 1, by semiconductor structure 10 beginnings, in one embodiment, semiconductor structure 10 comprises and does not show on some figure but the required structure of established general semiconductor element, for example N type in silicon substrate, the silicon substrate or P type or trap (well) that both all possess and isolated component oxygen district, field or the shallow trench isolated component as forming with regional oxidizing process.In addition, the present invention also can be applicable to other to have had in the above structure of ground floor, and therefore, semiconductor structure 10 itself also can have the multi-lager semiconductor component structure, and is not limited to shown in the present embodiment.Then, utilize general suitable mode commonly used, on semiconductor structure 10, form conductive layer 12.In the present embodiment, conductive layer 12 is a polysilicon layer, and preparation is used for the usefulness as grid, therefore has a gate oxide (not showing on the figure) between semiconductor structure 10 and conductive layer 12.Be noted that the present invention is not limited to the conductive layer 12 that material is a polysilicon layer, and do not limit usefulness, so long as need not break away from the scope of the invention through semiconductor element or structure that photoetching forms as grid.
One of feature of the present invention as shown in Figure 2, is to cover in regular turn a layer hard mask layer 14 (hardmask layer) and a photoresist layer 16 on conductive layer 12.In the present embodiment, hard mask layer 14 is a silicon oxynitride layer (oxynitridelayer), and its thickness is about 200 dusts.Be noted that, because follow-up use hard mask layer 14 is as the etch mask of etching conductive layer 12, therefore, so long as and the material of conductive layer 12 with good etching selection ratio, all can be used as hard mask layer 14 used in the present invention, and be not limited to silicon oxynitride layer.Afterwards, utilize wavelength for the light of 248nm as exposure light source, to photoresist layer 16 through general design transfer, exposure, isotropic etch back (isotropic etch back) after, form the photoresist layer 16 of patterning.One of feature of the present invention is 16 usefulness that are used for as the subsequent etching of hard mask layer 14 of photoresist layer, so the thickness of photoresist layer 16 do not need blocked up, thin photoresist layer 16, and preferable resolution can be provided.
Afterwards, as shown in Figure 3, be an etch mask with the photoresist layer 16 of patterning, remove the hard mask layer 14 of part, just remove the hard mask layer 14 that the photoresist layer 16 that is patterned of part exposes, again photoresist layer 16 is removed to form the hard mask layer 14 of patterning.Afterwards, then the hard mask layer 14 with patterning is an etch mask, just removes conductive layer 12 that the hard mask layer 14 that is patterned of part exposes to form the conductive layer 12 of patterning.One of feature of the present invention, be that the hard mask layer 14 with patterning is the etch mask of conductive layer 12, but not general be the etch mask of conductive layer 12 with photoresist layer 16, so can significantly reduce the thickness of photoresist layer 16, also can obtain the conductive layer 12 of the littler patterning of size; In the present invention, can form the grid of 100 submicron lengths.One of purpose of the present invention, be to utilize wavelength for the light of 248nm as exposure light source, can be easier to make the grid of 100 submicron lengths.In addition, one of feature of the present invention is when forming the conductive layer of patterning, owing to be to be mask with the hard mask layer, therefore when removing unnecessary conductive layer, can not form as the high molecular residue from photoresist layer is arranged traditionally in cleaning process.
Above-described embodiment is only in order to illustrate technological thought of the present invention and characteristics; its purpose makes those of ordinary skill in the art can understand content of the present invention and is implementing according to this; the scope of this patent also not only is confined to above-mentioned specific embodiment; be all equal variation or modifications of doing according to disclosed spirit, still be encompassed in protection scope of the present invention.
Claims (9)
1. the design transfer method of a conductive structure comprises: a Semiconductor substrate is provided;
On this Semiconductor substrate, form a conductive layer;
On this conductive layer, form a hard mask layer;
On this hard mask layer, form a photoresist layer;
This photoresist layer that removes part in the isotropic etching mode is to form this photoresist layer of patterning;
Photoresist layer with this patterning is first mask, and this hard mask layer of etching is to form this hard mask layer of patterning; And
Hard mask layer with this patterning is second mask, removes this conductive layer of part to form this conductive layer of patterning.
2. the design transfer method of conductive structure according to claim 1 is characterized in that: behind this hard mask layer that forms patterning, remove this conductive layer of part before, remove the photoresist layer of this patterning.
3. the design transfer method of conductive structure according to claim 1 is characterized in that: the photoresist layer and the hard mask layer that remove this patterning after removing this conductive layer of part.
4. the design transfer method of conductive structure according to claim 1 is characterized in that: forming an insulation course between this Semiconductor substrate and this conductive layer.
5. the design transfer method of conductive structure according to claim 1 is characterized in that: form this conductive layer and be polysilicon layer of deposition.
6. the design transfer method of conductive structure according to claim 5 is characterized in that: form this hard mask layer for forming a silicon oxynitride layer.
7. the design transfer method of a grid comprises: a Semiconductor substrate is provided;
On this Semiconductor substrate, form a polysilicon layer;
On this polysilicon layer, form a hard mask layer;
On this hard mask layer, form a photoresist layer;
With the isotropic etching mode, remove the part this photoresist layer with expose the part this hard mask layer;
Remove the hard mask layer that is exposed out to expose this polysilicon layer of part;
Remove the photoresist layer of patterning;
Remove the polysilicon layer that is exposed out to form this polysilicon layer of patterning; And
Remove the hard mask layer of patterning.
8. the design transfer method of grid according to claim 7 is characterized in that: form this hard mask layer for forming a silicon oxynitride layer.
9. the design transfer method of grid according to claim 7 is characterized in that: be the light of 248nm this photoresist layer that exposes with the wavelength.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410054375 CN1746773A (en) | 2004-09-08 | 2004-09-08 | Pattern transferring method of conductive structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410054375 CN1746773A (en) | 2004-09-08 | 2004-09-08 | Pattern transferring method of conductive structure |
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| Publication Number | Publication Date |
|---|---|
| CN1746773A true CN1746773A (en) | 2006-03-15 |
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| CN 200410054375 Pending CN1746773A (en) | 2004-09-08 | 2004-09-08 | Pattern transferring method of conductive structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011050623A1 (en) * | 2009-10-28 | 2011-05-05 | 中国科学院微电子研究所 | Patterning method |
| CN101441996B (en) * | 2007-11-21 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming and etching hard mask layer |
| CN104538433A (en) * | 2015-01-09 | 2015-04-22 | 昆山工研院新型平板显示技术中心有限公司 | Active-matrix organic light emission display substrate and manufacturing method thereof |
| CN106371294A (en) * | 2016-12-01 | 2017-02-01 | 京东方科技集团股份有限公司 | Manufacturing method of display substrate, display substrate and display device |
| CN112320752A (en) * | 2019-08-05 | 2021-02-05 | 上海新微技术研发中心有限公司 | Preparation method of negative photoresist patterned film layer |
-
2004
- 2004-09-08 CN CN 200410054375 patent/CN1746773A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441996B (en) * | 2007-11-21 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming and etching hard mask layer |
| WO2011050623A1 (en) * | 2009-10-28 | 2011-05-05 | 中国科学院微电子研究所 | Patterning method |
| US8338084B2 (en) | 2009-10-28 | 2012-12-25 | Institute of Microelectronics, Chinese Academy of Sciences | Patterning method |
| CN104538433A (en) * | 2015-01-09 | 2015-04-22 | 昆山工研院新型平板显示技术中心有限公司 | Active-matrix organic light emission display substrate and manufacturing method thereof |
| CN106371294A (en) * | 2016-12-01 | 2017-02-01 | 京东方科技集团股份有限公司 | Manufacturing method of display substrate, display substrate and display device |
| CN112320752A (en) * | 2019-08-05 | 2021-02-05 | 上海新微技术研发中心有限公司 | Preparation method of negative photoresist patterned film layer |
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