CN1737806A - Method for generating gate controlled clock unit according to standard cell base element directly - Google Patents
Method for generating gate controlled clock unit according to standard cell base element directly Download PDFInfo
- Publication number
- CN1737806A CN1737806A CN 200510029299 CN200510029299A CN1737806A CN 1737806 A CN1737806 A CN 1737806A CN 200510029299 CN200510029299 CN 200510029299 CN 200510029299 A CN200510029299 A CN 200510029299A CN 1737806 A CN1737806 A CN 1737806A
- Authority
- CN
- China
- Prior art keywords
- clock unit
- gate controlled
- controlled clock
- pin
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
This invention relates to integration circuit technique field direct standard unit database parts clock units generating method, which comprises the following steps: unit structure defining, structure building, layout distributing, RC parameter extracting, time series database files; physical files generating and testing module, wherein, the layout and lead leg is set on the adjacent metal layer channel to make the output direction on level and crossed layers to realize the lead leg use and to prevent shielding layer on the door controlled clock unit.
Description
Technical field
What the present invention relates to is a kind of method of technical field of integrated circuits, particularly a kind of method that directly generates gate controlled clock unit according to standard cell base element.
Background technology
Gate controlled clock unit is the comparatively popular low power consumption design method in present SOC field, promptly when some heavy die block is in off position, and closing module clock internal signal, thus reduce the dynamic power consumption of inside modules, realize the low power dissipation design of chip.Use to gated clock in the now common integrated circuit flow process generally is divided into following several: foundry services manufacturer is by Design of Production Line or directly want to buy to the foundry vendor, promptly use real physical device to build and test, obtain relevant sequential and physical data thus.This method test result is comparatively accurate, and it is comparatively convenient that integrated circuit (IC) design department uses, but that shortcoming is cost is higher; Utilize the RTL language directly to build, the advantage of this method is that integrated circuit (IC) design department more easily realizes, the design of front end and testing authentication are also very convenient, but also there is certain defective in it: during the placement-and-routing of rear end if be made as autoplacement then between the device physical distance uncontrollable, the connection of device is very loose, real binding that can not implementation structure is easy to generate adverse influence on the sequential time slot; Implementation custom circuit design, but can't realize the dirigibility of chip design is in case occur that technology is changed or framework adjustment then need to reformulate circuit and size, restriction rule etc.
Find through literature search prior art, people such as Zhang Yongxin are at " microelectronics and computing machine ", the 21st the 1st phase of volume of January in 2004, " low power design technique of gated clock " delivered on the 23-26 page or leaf, this article provides a kind of method of utilizing layout tool to insert gate controlled clock unit automatically in the chip layout stage for the deviser, its principal character is exactly by specific function and the performance of instrument according to certain logical gate, and the device in the selection standard cell library forms gate controlled clock unit automatically.But this method is because can't be with the geographically thoroughly binding of composition device of door control unit, therefore its time delay to circuit integral body, area effect are all unfixing, owing to when Front-end Design, can't carry out exampleization, therefore can cause certain inconvenience simultaneously to the design verification of chip integral body to gate controlled clock unit.
This shows, traditional gated clock build or using method on economy and efficient, all restrictions have all been made by integrated circuit (IC) design department, therefore be necessary very much to find a kind of method that directly generates gated clock reasonably, easily by eda tool and standard cell lib.
Summary of the invention
The design that the present invention is intended to overcome above-mentioned gate controlled clock unit is given inconvenience that integrated circuit (IC) design department brings and difficult, a kind of method that directly generates gate controlled clock unit according to standard cell base element is provided, make it can generate gate controlled clock unit and associated documents thereof easily, thereby realize its easy generation and easy utilization.
The present invention is achieved by the following technical solutions, the present invention uses eda tool directly to generate gate controlled clock unit according to standard cell base element, and its step comprises: the generation of the building of the definition of cellular construction, structure, placement-and-routing, RC Parameter Extraction, timing sequence library file and physical library file and verification model make up.Below describe in detail:
1, the definition of cellular construction
Determining of gate controlled clock unit structure is the basis of realizing that relevant design and file generate.The version of gate controlled clock unit is more.From the employing of main device, can be divided into based on latch (latch) and register (flip-flop, ff) two classes, usually in order to prevent the generation of burr, use latch and register to build, in fact also have the clock gating cell that does not use latch or ff of eda tool support; From the type of service that produces clock, can be divided into rising edge effectively (posedege) and effective (negedge) two classes of negative edge; Under situation, also can produce the position and be divided into forward direction control (pre-control) and back to control (post-control) according to the final enable signal of gating with test pattern (test mode); As if sample enable signal being needed monitoring, then also can being divided into control point (obs) and no control point two classes are arranged.To the combination of above-mentioned each classificating requirement, the structure composition of clock gating cell and the basic law of naming rule have been constituted.When structure is determined, also need the purposes of pin (pin) to make specific definitions to gate controlled clock unit.Since the structure of gate controlled clock unit by strict regulations as above-mentioned several types within, so the purposes of its all signals all can be by strict difinition, the corresponding attribute of signal (attribute) definition that Here it is.
With the most frequently used latch_posdege_precontrol and latch_posdege_postcontrol is example for two types, and its signal mainly is divided into following a few class:
1.clock_gate_enable_pin: module clock enable signal en;
2.clock_gate_clock_pin: input clock signal clk;
3.clock_gate_test_pin: test pattern enable signal se;
4.clock_gate_out_pin: clock signal gclk.
For the clock_gating_cell that as latch_posedge_precontrol_obs, has the control point signal, also have:
Clock_gate_obs_pin: enable control point signal obs_pin.
It is pointed out that clock_gating_cell only limits to above-mentioned five kinds to the definition of pin pin signal, the pin pin signal that the DC instrument of synopsys can be good according to the automatic removal search respective specified of the type of architecture of clock_gating_cell.Do not meet the pin pin signal that clock_gating_cell requires if added some therein, then can be defaulted as a useless pin pin by instrument.For example wish in design that still this reset signal is to find corresponding definition in the pin of clock_gating_cell pin signal type by using the reset signal with the signal zero clearing on latch or the flip-flop.
2, structure builds
After structure is determined to finish, can total be built by the standard block library file of corresponding technology, promptly determine particular device and mutual annexation thereof.Generally speaking, should directly adopt the net table but not use the RTL behavioral description language to build this kind structure.Use synthesis tool (as SynopsysDesign Compiler) that the gate controlled clock unit structure is carried out comprehensively wherein needing emphasis that the port signal of this structure is made certain constraint after finishing:
Signal input and output time delay;
The input signal driving force;
Output signal load size;
The fan-out restriction;
Obtain the physical location unbound document by this process, submit to placement-and-routing's instrument to use.
3, placement-and-routing
Placement-and-routing's instrument (as Synopsys Astro) is by reading matter reason position constraint file and standard cell lib, the employed device of gate controlled clock unit structure chosen carry out putting of ad-hoc location, and generate relevant input and output and be connected signal wire, to meet the requirement of unbound document.It should be noted that, being provided with of the pin placing direction of input/output signal, must design (Hardmacro) with stone distinguishes to some extent, be the input and output direction of pin must be convenient to can both realize pin on horizontal and vertical level utilization, but not single direction commonly used is derived pin mode during the stone design.In the present invention, the extraction location of pin is set on the path (via) between adjacent transverse and the longitudinal metal layer, like this when chip design, the unit pin laterally with vertically on can both utilized easily.In addition, also should prevent from around gate controlled clock unit, to stamp screen layer (blockage), thereby save the wiring space of chip integral body.Why adopting this method, is in order to realize the equivalence substantially in the use of gate controlled clock unit and standard cell lib.
4, RC Parameter Extraction
Finish and to utilize after the placement-and-routing instrument to extract RC parameter information on the inner and port of gate controlled clock unit.
5, the generation of timing sequence library file and physical library file
The RC parameter is imported in the library file extracting tool (as Synopsys Primetime), generate timing sequence library file (.lib file).The library file that obtain this moment can not be as the basic timing sequence library file of gate controlled clock unit, and this is because the corresponding clock output port by the rear end inspection of tools time, can't be thought clock output to be arranged.In order to overcome above-mentioned difficulties, solution proposed by the invention is exactly the change that being defined as of corresponding input/output port pin is met gate controlled clock unit library file form.With latch_posedge_precontrol type gated clock is example:
(1) in the cell attribute, adds the clock_gating_integrated_cell statement;
(2) on input clock signal, add the clock_gate_clock_pin statement, and delete original clock statement;
(3) on corresponding module enable signal, add the clock_gate_enable_pin statement;
(4) on corresponding test enable signal, add the clock_gate_test_pin statement;
(5) on clock signal, add the clock_gate_out_pin statement;
(6) must add the relation of intermediate variable and output clock and intermediate variable in case of necessity.
By above-mentioned manual modification, can obtain the lib file that synthesis tool (Synopsys Design Compiler) can identify the clock_gating_cell type, thereby generate the db file.Simultaneously, utilization placement-and-routing instrument generates the lef file, the tech file that uses this file and foundries to provide according to the domain (Synopsys Astro) of unit, generate physics library file (plib and pdb), thereby realize whole the finishing of gate controlled clock unit related libraries file.
6, verification model makes up
After these files form,, also should set up the behavioral scaling realistic model (Behavior Model) of gate controlled clock unit according to the gate controlled clock unit temporal characteristics in order to realize the rationality of simulating, verifying.Can use the behavior description of RTL to set up model generally speaking, but in order to realize the post-simulation reality, should use gate leve language or self-defined primitive (primitive as far as possible, be truth table) the generation behavior model, add the sequential specify information of related port simultaneously so that the information of RC parameter can be in the emulation of rear end by reactionary slogan, anti-communist poster to the port of aperture of door clock unit.So far, the gate controlled clock unit of complete use has been realized all directly generating in integrated circuit (IC) design department.
From foregoing description; as long as can guarantee the accuracy of the standard cell lib that obtains; according to the flow process that the present invention introduced; just can utilize common eda tool directly to generate gate controlled clock unit and relevant library file thereof in integrated circuit (IC) design department easily, for low power dissipation design provides sizable facility.Compared with prior art, the present invention can generate gate controlled clock unit and associated documents thereof easily, thereby realizes its easy generation and easy utilization.
Description of drawings
Fig. 1 the inventive method process flow diagram
Embodiment
As shown in Figure 1, the invention will be further described below in conjunction with embodiment, but the present invention never is confined to these embodiment.
Need rear end control rising edge gate controlled clock unit (latch_posedge_postcontrol) based on latch of design, the concrete steps that need to carry out are:
1. determine to use the gate controlled clock unit structure of latch_posedge_postcontrol, determine relevant pin function;
Clock_gate_enable_pin: module clock enable signal module_clk_en;
Clock_gate_clock_pin: input clock signal clkin;
Clock_gate_test_pin: test pattern enable signal test_clk_en;
Clock_gate_out_pin: clock signal clkout;
2. building of structure:
According to selected clock_gating_cell structure, directly adopt the gate leve structure to write rtl code (code slightly).Code has formed the clock_gating_cell of a latch_poedge_precontrol.At this literary style, can promptly not be optimized to the device set_dont_touch of exampleization in the comprehensive script of DC.For this reason, need do following consideration to choosing of corresponding devices:
Driver
Load
fanout
Because the clock signal that generates by clock_gating_cell may drive considerable trigger or receive on the buffer, the restriction of fanout and load must be rationally.By the comprehensive script of clock_gating_cell, in order to generate the sdc file.In the DC script, need call the constraints file, respectively clock, input/output signal delay, drive, load, fanout done corresponding restriction:
3. placement-and-routing
Utilize placement-and-routing's instrument (Astro) that standard block is built structure into gate controlled clock unit, and finish the logic line between the unit, and satisfy the sequential requirement.Definite then pin is drawn direction, pin is arranged on the path (via) of ground floor metal level and second layer metal layer, thereby the domain of finishing gate controlled clock unit is made.
4.RC Parameter Extraction
Utilize the Starrcxt instrument to extract its parasitic parameter information (.spef), prepare for generating the timing sequence library file from the domain of gate controlled clock unit
5. the generation of timing sequence library file and physical library file
Set up the command file, utilize, import the extraction of carrying out library file among the Primetime from the spef and the net meter file (netlist) that generate.The instruction of an outbalance is extract_model when extracting library file, and its concrete form can be with reference to the User Manual of Primetime.
The lib file that above-mentioned extract_model forms not is to be to be similar to the clock_gating_cell library file that the eda tool of this class of DC can identify, and therefore need carry out manual modification to the lib file.
1) in the cell attribute, adds the clock_gating_integrated_cell statement.
2) on corresponding module enable signal, add the clock_gate_enable_pin statement.
3) on corresponding test enable signal, add the clock_gate_test_pin statement.
4) add intermediate variable syn_clk_en.
5) logical relation between interpolation intermediate variable syn_clk_en and input signal clkin, module_clk_en, the test_clk_en is used truth-table format usually.
6) on clock signal, add the clock_gate_out_pin statement, and indicate the relation of itself and syn_clk_en and clkin.
By above-mentioned manual modification, can obtain the lib file that the DC instrument can identify the clock_gating_cell type, thereby generate the db file.
Make plib and pdb, need the lef file, obtain after can doing conversion by the lef file that Astro derives.
6. the foundation of behavior model
Set up the function statement behavioral scaling model of a gate controlled clock unit, and on port, add reactionary slogan, anti-communist poster information (specify).
The general design that the present invention overcomes gate controlled clock unit is given inconvenience that integrated circuit (IC) design department brings and difficult, can generate gate controlled clock unit and associated documents thereof easily, thereby realize its easy generation and easy utilization.
Claims (7)
1, a kind of method that directly generates gate controlled clock unit according to standard cell base element is characterized in that, the utilization eda tool directly generates gate controlled clock unit according to standard cell base element, and its step comprises:
(1) definition of cellular construction: according to the structure type of gate controlled clock unit, combination to each classificating requirement, the structure that has constituted clock gating cell is formed and the basic law of naming rule, when structure is definite, the pin pin purposes of gate controlled clock unit is defined;
(2) building of structure: after finishing the determining of structure, directly adopt the net table to build total by the standard block library file, and use synthesis tool to realize comprehensive to the gate controlled clock unit structure, wherein need emphasis that the port signal of this structure is made constraint, obtain the physical location unbound document by this process, submit to placement-and-routing's instrument to use;
(3) placement-and-routing: placement-and-routing's instrument is by reading matter reason position constraint file and standard cell lib, the employed device of gate controlled clock unit structure chosen carry out putting of ad-hoc location, and generate relevant input and output and be connected signal wire, to meet the requirement of unbound document;
(4) RC Parameter Extraction: finish and utilize after the placement-and-routing instrument to extract RC parameter information on the inner and port of gate controlled clock unit;
(5) generation of timing sequence library file and physical library file: the RC parameter is imported in the library file extracting tool, generate the timing sequence library file;
(6) verification model makes up: after timing sequence library file and the formation of physical library file, according to the gate controlled clock unit temporal characteristics, set up the behavioral scaling realistic model of gate controlled clock unit.
2, the method that directly generates gate controlled clock unit according to standard cell base element according to claim 1 is characterized in that, in the step (1), and the structure type of described gate controlled clock unit, specific as follows:
From the employing of main device, be divided into based on latch and register two classes; From the type of service that produces clock, be divided into effective and effective two classes of negative edge of rising edge; Have under the situation of test pattern, produce the position according to the final enable signal of gating and be divided into forward direction control and back to control; As if sample enable signal being needed monitoring, then also be divided into to have control point and no control point two classes.
3, the method that directly generates gate controlled clock unit according to standard cell base element according to claim 1 is characterized in that in the step (1), the pin pin purposes of described gate controlled clock unit defines, and is specific as follows:
Clock_gate_enable_pin: module clock enable signal en;
Clock_gate_clock_pin: input clock signal clk;
Clock_gate_test_pin: test pattern enable signal se;
Clock_gate_out_pin: clock signal gclk;
Clock_gate_obs_pin: enable control point signal obs_pin.
4, the method that directly generates gate controlled clock unit according to standard cell base element according to claim 1 is characterized in that in the step (2), the described emphasis that needs is made constraint to the port signal of this structure, specifically comprises:
Signal input and output time delay;
The input signal driving force;
Output signal load size;
The fan-out restriction.
5, the method that directly generates gate controlled clock unit according to claim 1 according to standard cell base element, it is characterized in that, in the described step (3), the described employed device of gate controlled clock unit structure is chosen carried out putting of ad-hoc location, wherein, pin is set on the path of adjacent metal, so that the input and output direction is convenient to can both realize the utilization of pin on horizontal and vertical level, and prevents to stamp screen layer around gate controlled clock unit.
6, the method that directly generates gate controlled clock unit according to claim 1 according to standard cell base element, it is characterized in that, in the step (5), when generating the sequential file, must do the definition of corresponding input/output port pin and meet the manual of gate controlled clock unit library file form and change, so that identify gate controlled clock unit during system synthesis.
7, the method that directly generates gate controlled clock unit according to claim 1 according to standard cell base element, it is characterized in that, in the step (6), after finishing gate controlled clock unit related libraries file comprehensively, temporal characteristics according to gate controlled clock unit, set up the behavioral scaling realistic model of gate controlled clock unit, this model is a kind of behavior model that uses gate leve language or self-defined language generation, adds the sequential specify information of related port simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510029299 CN1737806A (en) | 2005-09-01 | 2005-09-01 | Method for generating gate controlled clock unit according to standard cell base element directly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510029299 CN1737806A (en) | 2005-09-01 | 2005-09-01 | Method for generating gate controlled clock unit according to standard cell base element directly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1737806A true CN1737806A (en) | 2006-02-22 |
Family
ID=36080599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510029299 Pending CN1737806A (en) | 2005-09-01 | 2005-09-01 | Method for generating gate controlled clock unit according to standard cell base element directly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1737806A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101968826A (en) * | 2010-11-23 | 2011-02-09 | 长沙景嘉微电子有限公司 | Tool for automatically establishing time sequence base |
| CN102831273A (en) * | 2012-08-30 | 2012-12-19 | 锐迪科科技有限公司 | Design method of digital integrated circuit comprising double-edge trigger |
| CN102982207A (en) * | 2012-11-29 | 2013-03-20 | 上海华力微电子有限公司 | Method for generating critical dimension bar pattern |
| CN109948226A (en) * | 2019-03-13 | 2019-06-28 | 上海安路信息科技有限公司 | The processing method and processing system of activation bit |
| CN110619166A (en) * | 2019-09-09 | 2019-12-27 | 中国人民解放军国防科技大学 | Design method of low-power-consumption clock tree |
| CN112364579A (en) * | 2020-09-28 | 2021-02-12 | 中国船舶重工集团公司第七0九研究所 | Gated clock conversion method based on recursive multi-branch tree |
| CN117634379A (en) * | 2022-08-24 | 2024-03-01 | 上海合见工业软件集团有限公司 | Optimization method and system for IC design |
-
2005
- 2005-09-01 CN CN 200510029299 patent/CN1737806A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101968826A (en) * | 2010-11-23 | 2011-02-09 | 长沙景嘉微电子有限公司 | Tool for automatically establishing time sequence base |
| CN101968826B (en) * | 2010-11-23 | 2013-03-06 | 长沙景嘉微电子股份有限公司 | Tool for automatically establishing time sequence base |
| CN102831273A (en) * | 2012-08-30 | 2012-12-19 | 锐迪科科技有限公司 | Design method of digital integrated circuit comprising double-edge trigger |
| CN102982207A (en) * | 2012-11-29 | 2013-03-20 | 上海华力微电子有限公司 | Method for generating critical dimension bar pattern |
| CN102982207B (en) * | 2012-11-29 | 2015-06-17 | 上海华力微电子有限公司 | Method for generating critical dimension bar pattern |
| CN109948226A (en) * | 2019-03-13 | 2019-06-28 | 上海安路信息科技有限公司 | The processing method and processing system of activation bit |
| CN109948226B (en) * | 2019-03-13 | 2020-12-25 | 上海安路信息科技有限公司 | Method and system for processing drive information |
| CN110619166A (en) * | 2019-09-09 | 2019-12-27 | 中国人民解放军国防科技大学 | Design method of low-power-consumption clock tree |
| CN110619166B (en) * | 2019-09-09 | 2023-02-10 | 中国人民解放军国防科技大学 | Design method of low-power-consumption clock tree |
| CN112364579A (en) * | 2020-09-28 | 2021-02-12 | 中国船舶重工集团公司第七0九研究所 | Gated clock conversion method based on recursive multi-branch tree |
| CN112364579B (en) * | 2020-09-28 | 2022-11-15 | 武汉凌久微电子有限公司 | Gated clock conversion method based on recursive multi-branch tree |
| CN117634379A (en) * | 2022-08-24 | 2024-03-01 | 上海合见工业软件集团有限公司 | Optimization method and system for IC design |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7788625B1 (en) | Method and apparatus for precharacterizing systems for use in system level design of integrated circuits | |
| US7603643B2 (en) | Method and system for conducting design explorations of an integrated circuit | |
| CN1737806A (en) | Method for generating gate controlled clock unit according to standard cell base element directly | |
| CN102831273B (en) | Design method of digital integrated circuit comprising double-edge trigger | |
| CN107256303B (en) | Method for rapidly acquiring simulation state of internal node of digital gate-level circuit | |
| CN101539958B (en) | Method and device for designing standard cell library and integrated circuit | |
| WO2005119441A2 (en) | Methods and systems for structured asic eletronic design automation | |
| Qamar et al. | LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow | |
| CN115470747B (en) | Clock tree synthesis method for realizing rapid convergence of time sequence | |
| US20070044058A1 (en) | Enabling efficient design reuse in platform ASICs | |
| US7003753B2 (en) | Method of generating a physical netlist for a hierarchical integrated circuit design | |
| US10657210B2 (en) | Slack time recycling | |
| Madariaga et al. | Review of electronic design automation tools for high-level synthesis | |
| Khan et al. | GHAZI: An Open-Source ASIC Implementation of RISC-V based SoC | |
| Hiremath et al. | Rtl to gdsii implementation of advanced high-performance bus lite | |
| Srivastava et al. | Operation-dependent frequency scaling using desynchronization | |
| Xu et al. | Platform-based design and the first generation dilemma | |
| Verbauwhede et al. | Skiing the embedded systems mountain | |
| Kim et al. | Multimedia IP Design in SystemC Design Environment Adopting High-level Code Optimization | |
| CN114861577A (en) | Method and device for analyzing digital circuit, electronic device, and storage medium | |
| Zhang et al. | Challenges and opportunities of ESL design automation | |
| Meredith et al. | The Next IC Design Methodology Transition Is Long Overdue | |
| Sagdeo | Synthesis with Verilog | |
| Um et al. | A Systematic Transaction Level Modeling and Verification | |
| Gong et al. | A de-synchronous circuit design flow using hybrid cell library |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |