CN102831273A - Design method of digital integrated circuit comprising double-edge trigger - Google Patents
Design method of digital integrated circuit comprising double-edge trigger Download PDFInfo
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Abstract
The invention discloses a design method of a digital integrated circuit comprising a double-edge trigger, wherein the method updates steps such as design input, logic synthesis, gate-level and RTL (Resistor Transistor Logic) level formal verification, logic optimization, formal verification of the gate level after/before optimization, distributing, wiring, and the like, so that the double-edge trigger is really integrated to the design method of the digital integrated circuit. The method has an important significance for improving processing speed of the digital integrated circuit or reducing power consumption of the digital integrated circuit.
Description
Technical field
The application relates to a kind of digital integrated circuit design method,
Background technology
Fig. 1 is a rising edge d type flip flop, and its output signal Q only follows the tracks of input signal D at the rising edge of clock signal clk.
Fig. 2 is a negative edge d type flip flop, and it just with the clock input inversion of rising edge d type flip flop, only follows the tracks of input signal D at the negative edge of clock signal clk so that export signal Q.
Fig. 3 be one bilateral along d type flip flop, comprise a rising edge d type flip flop 10, a negative edge d type flip flop 20 and one two path multiplexer 30.At the rising edge of clock signal clk, two path multiplexers 30 with the output signal Q1 of rising edge d type flip flop 10 as bilateral output signal Q3 along d type flip flop.At the negative edge of clock signal clk, two path multiplexers 30 with the output signal Q2 of negative edge d type flip flop 20 as bilateral output signal Q3 along d type flip flop.Therefore, bilateral output signal Q3 along d type flip flop is both at the rising edge of clock signal clk, also follow the tracks of input signal D at the negative edge of clock signal clk.
Above-mentioned is that the dual-edge trigger of example broken can only be at a clock along the limitation that carry out data processing in the clock period with the d type flip flop, and rising edge in a clock period and negative edge all can carry out data processing.After adopting this dual-edge trigger, when input signal was still kept original frequency, the frequency of clock signal can be reduced to original half the, and still can handle under the original clock signal frequency with monolateral along the identical data volume of trigger.Obviously, reduce the purpose that half clock frequency can reach remarkable reduction power consumption, reduce to generate heat.If still keep original clock signal frequency, then the data processing amount of dual-edge trigger in the identical time period can reach original twice, thereby significantly promotes processing speed.
Current, digital integrated circuit adopts method for designing top down usually.See also Fig. 4, this is a kind of typical digital integrated circuit design method, comprises the steps:
(design entry) imported in the 1st step, design, promptly describes the behavior and/or the structure of circuit with text and/or graphics mode, forms the circuit description document of RTL level.Text mode for example adopts hardware description languages (HDL, hardware description language) such as Veri log, VHDL.Graphics mode for example adopts schematic diagram, constitutional diagram etc.The circuit behavior is meant the input of circuit and relation and the sequential relationship thereof between the output.Circuit structure is meant each functional block, module, unit, door and the annexation between them in the circuit.
The 2nd step, RTL (register transfer level, register transfer level) level functional simulation promptly carry out emulation to the rtl circuit description document, and whether test its function consistent with designing requirement.RTL level functional simulation is claimed preceding emulation (pre-layout simulation) again, does not have time sequence information usually, or to define time delay simply be the unit interval, like 1ns.
The 3rd step, logic synthesis (logic synthesis), the circuit description document that is about to the RTL level converts gate level netlist (netlist) file of being made up of concrete logical block into.The gate level netlist file can be EDIF file, VHDL file, Verilog file etc.Transfer process depends on constraint condition and cell library file.
Said constraint condition comprises area-constrained, temporal constraint etc.Said temporal constraint comprises frequency, dutycycle, the offset characteristic of requirement work clock, the input time delay of input signal, the output time-delay of output signal, the switching time of each signal etc.
Said cell library file is also claimed the technology library file, comprises some necessary time sequence informations (delayed data, driving force etc.) of various combinatorial logic unit (Sheffer stroke gate, multiplexer, totalizer etc.) and sequential logic unit (trigger, latch etc.) and these unit.
The 4th step, gate leve and the formal verification of RTL level promptly judge statically according to circuit structure whether the gate leve net meter file is consistent on function with the rtl circuit description document.Existing digital integrated circuit only adopts monolateral along trigger, thereby this step can omit.
The 5th step, comprehensive back gate leve functional simulation promptly carry out emulation to formed gate level netlist file after the logic synthesis, and whether test its function consistent with designing requirement.Whether can be chosen in and add time sequence information in the gate level netlist this moment, consistent with designing requirement to judge its sequential.
The 6th step, logic optimization (logic optimization); Promptly according to the Boolean equation equivalence principle; The unoptimizable boolean of in the gate level netlist file that logic synthesis generated some are described the boolean who converts optimization into describe, with the scale that reduces the logical block that circuit takies, simplify circuit structure.Gate level netlist file behind the logic optimization also will carry out functional simulation.
The 7th step, optimize before and after the gate leve formal verification, whether the gate level netlist file before the gate level netlist file after promptly decision logic is optimized statically according to circuit structure and the logic optimization consistent on function.
Whether the 8th step, optimize back gate leve functional simulation, promptly formed gate level netlist file behind the logic optimization is carried out emulation, it is consistent with designing requirement to test its function.Whether can be chosen in and add time sequence information in the gate level netlist this moment, consistent with designing requirement to judge its sequential.
The 9th step, placement-and-routing promptly carry out layout design according to the gate level netlist file.This process generally includes:
(1) pre-layout (floor planning), the i.e. shape of definite chip, size etc.
(2) layout (placement) is promptly arranged the piece (blocks) that net is shown on chip, confirm the position of unit (cells) in the piece.
(3) comprehensive (clock tree synthesis, CTS), this is that physical layout according to chip is passed to each register clock pin in the chip with clock signal by the clock source to clock trees.Clock trees is a kind of tree structure that is used for analytical line time-delay.For example, as tree root, each lock unit is as leaf with the clock source, and middle branch is exactly actual line.Under the ideal situation, each lock unit should receive clock signal simultaneously.Each paths length through analyzing clock trees can be optimized improvement to the delay deviation of receive clock signal.
(4) line is promptly confirmed in wiring (routing) in piece and unit or between them.
The 10th step, domain level functional simulation; Also claim post-simulation (post-layout simulation); Promptly to the net meter file after the placement-and-routing or to the extraction after the placement-and-routing net meter file of RC parameter (resistance capacitance parameter) carry out emulation, whether consistent to test its function with designing requirement with sequential.
The 11st step, layout verification comprise that net table output (NE), electricity rule inspection (ERC), the parasitic parameter of DRC (DRC), domain extracts (PE), circuit diagram domain contrast (LVS) etc.
The 12nd step, generation domain GDSII data.
Because popularizing of EDA (electronic design automation) instrument in each step of above-mentioned design cycle, all has eda tool to help to realize.In all the other steps except that the 1st step, be to rely on eda tool to realize automatically basically, errors excepted again by the manual amendment.
Existing digital integrated circuit design method all is based on monolateral along trigger.At present also have no idea to comprise the Design of Digital Integrated Circuit of dual-edge trigger; This is because the eda tools such as logic synthesis tool in the 3rd step are not supported dual-edge trigger, thereby can't automatically convert the circuit description document of RTL level into the gate level netlist file.These work then are unthinkable as all transferring to artificial treatment.
Summary of the invention
The application's technical matters to be solved is to make existing digital integrated circuit design method increase the support to dual-edge trigger.
For solving the problems of the technologies described above, the digital integrated circuit design method that the application comprises dual-edge trigger comprises the step that designs input, logic synthesis, gate leve and the formal verification of RTL level, logic optimization, the gate leve formal verification of optimization front and back, placement-and-routing; Wherein:
When the design input, only adopt monolateral in the rtl circuit description document along trigger;
After logic synthesis, monolateral in the comprehensive back first gate level netlist file that generates partly or entirely changed into dual-edge trigger along trigger, generate the comprehensive back second gate level netlist file; In gate leve cell library file, increase the door of dual-edge trigger simultaneously, in gate leve cell library description document, increase the description of dual-edge trigger;
When gate leve and the formal verification of RTL level, comprehensive back first gate level netlist file and rtl circuit description document are carried out formal verification;
When logic optimization, the comprehensive back second gate level netlist file is carried out logic optimization;
Before optimizing front and back gate leve formal verification; Description with the dual-edge trigger in the gate leve cell library description document earlier changes into monolateral consistent along trigger; Carry out formal verification to optimizing back gate leve net meter file with the comprehensive back second gate level netlist file again, the description with the dual-edge trigger in the gate leve cell library description document recovers former state again;
Before placement-and-routing, the domain cellular construction and the ROW (row) that in domain level cell library file, increase dual-edge trigger earlier describe, and carry out placement-and-routing again; When placement-and-routing, the clock trees that is generated has comprised wire delay and the delay of two path multiplexers within the domain cellular construction of dual-edge trigger.
The said method of the application has realized comprising the whole process of the Design of Digital Integrated Circuit of dual-edge trigger, makes dual-edge trigger really be dissolved among the design of digital integrated circuit.This for the processing speed that promotes digital integrated circuit, or reduce the power consumption aspect of digital integrated circuit, all be significant.
Description of drawings
Fig. 1 is the logical symbol of rising edge d type flip flop.
Fig. 2 is the logical symbol of negative edge d type flip flop.
Fig. 3 is bilateral circuit diagram along d type flip flop.
Fig. 4 is the process flow diagram of existing digital integrated circuit design method.
Fig. 5 is the process flow diagram of the application's digital integrated circuit design method.
Description of reference numerals among the figure:
10 is the rising edge d type flip flop; 20 is the negative edge d type flip flop; 30 is two path multiplexers.
Embodiment
The application comprises the digital integrated circuit design method of dual-edge trigger, also has design input, RTL level functional simulation, logic synthesis, gate leve and the formal verification of RTL level as shown in Figure 4, comprehensive back gate leve functional simulation, logic optimization, the gate leve formal verification of optimization front and back, optimizes back gate leve functional simulation, placement-and-routing, domain level functional simulation, layout verification, these 12 steps of generation domain GDSII data.Wherein part steps is revised, concrete modification thes contents are as follows:
One of which, in the 1st when input step design, all triggers in the rtl circuit description document all adopt traditional monolateral along trigger.
Its two, the gate level netlist file that generates after the logic synthesis in the 3rd step is called the comprehensive back first gate level netlist file, trigger wherein all is monolateral along trigger.Monolateral in then will the comprehensive back first gate level netlist file partly or entirely changes dual-edge trigger along trigger into according to designing requirement, is called the comprehensive back second gate level netlist file.This change can realize through script file.
Monolateral advantage along trigger is that chip area is little, the advantage of dual-edge trigger be keep with monolateral during along the same clock frequency of trigger processing speed can be double, keep and monolateral during along the same processing speed of trigger clock frequency can reduce by half.Thereby common designing requirement is only in needing the nucleus module of high speed processing, to adopt dual-edge trigger, in all the other modules, still adopts monolateral along trigger; All triggers are adopted the same clock frequency, so that the processing speed of nucleus module is double.
When forming the comprehensive back second gate level netlist file, in gate leve cell library file (.lib file), increase the door of dual-edge trigger; Also in gate leve cell library description document (.v or .vhd file), increase the description of dual-edge trigger, promptly dual-edge trigger is all worked in rising edge of clock signal and negative edge.Though the gate level netlist file is identical with gate leve cell library description document suffix name; But the former is used for describing circuit connecting relation, input/output relation, the sequential relationship between each logical block (combinatorial logic unit, sequential logic unit), and the latter is used for describing each logical block to response process of clock signal etc.
Its three, when the 4th step gate leve and the formal verification of RTL level, comprehensive first gate level netlist file afterwards and rtl circuit description document are carried out formal verification.
Its four, in the 5th step during the gate leve functional simulation of comprehensive back, the comprehensive back first gate level netlist file is carried out functional simulation, this step can be omitted.
Its five, in the 6th step during logic optimization, the comprehensive back second gate level netlist file is carried out logic optimization.
They are six years old; Before gate leve formal verification before and after the optimization of the 7th step; Description with the dual-edge trigger in the gate leve cell library description document (.v or .vhd file) earlier changes into monolateral consistent along trigger, and promptly dual-edge trigger is only in rising edge of clock signal or negative edge work.Carry out formal verification to optimizing back gate leve net meter file with the comprehensive back second gate level netlist file then.Last again with the description recovery former state of the dual-edge trigger in the gate leve cell library description document, promptly dual-edge trigger is all worked in rising edge of clock signal and negative edge.
Its seven, before the 9th step placement-and-routing, in domain level cell library file (techfile), increase earlier the domain cellular construction and ROW (row) description of dual-edge trigger, promptly write down it highly.Carry out placement-and-routing afterwards again.When placement-and-routing, the clock trees that is generated has comprised the wire delay within the domain cellular construction of dual-edge trigger, the deferred message of two path multiplexers.
Through existing digital integrated circuit design method is carried out above-mentioned change, make this method be able to compatible dual-edge trigger.
See also Fig. 5, this is a specific embodiment of the application's digital integrated circuit design method of comprising dual-edge trigger, comprise the steps: (in each step with background technology in the identical part of content repeat no more)
The 1st step, design input are not adopted dual-edge trigger this moment to form the rtl circuit description document.Run into the situation that needs to use trigger, all adopt monolateral along trigger.Common design input tool software has Verilog, VHDL etc., and the suffix name of the rtl circuit description document that they form is respectively .v .vhd.
In fact, these two kinds of hardware description languages of Verilog and VDHL can be used for describing dual-edge trigger, but because follow-up logic synthesis tool is not supported dual-edge trigger, thereby when the design input, there is no need to adopt dual-edge trigger.
The 2nd the step, the rtl circuit description document is carried out functional simulation.Common functional simulation instrument has VCS (verilog compiled simulator), NCVerilog etc., and they all support all functions emulation in the 2nd step, the 5th step, the 8th step, the 10th step.
In fact, the functional simulation instrument is to support dual-edge trigger.But owing to do not comprise dual-edge trigger in the rtl circuit description document before, thereby dual-edge trigger is not carried out functional test in the functional simulation in this step yet.
The 3rd step, the rtl circuit description document is carried out logic synthesis, form the gate level netlist file.
Common logic synthesis tool is DC (design compiler), and it does not support dual-edge trigger.If comprise dual-edge trigger in the rtl circuit description document, then DC can't be converted into the gate level netlist file.Therefore, the trigger in the formed rtl circuit description document of the application all is monolateral along trigger, facilitates the use DC and carries out logic synthesis.Do not have dual-edge trigger in the formed gate level netlist file in comprehensive back yet, be called the comprehensive back first gate level netlist file.
Monolateral in then will the comprehensive back first gate level netlist file partly or entirely changes dual-edge trigger along trigger into according to designing requirement, is called the comprehensive back second gate level netlist file.When forming the comprehensive back second gate level netlist file, in gate leve cell library file (.lib file), increase the door of dual-edge trigger; Also in gate leve cell library description document (.v or .vhd file), increase the description of dual-edge trigger.
The input of logic synthesis tool has three types, and the first kind is rtl circuit description document (.v or a .vhd file), and second type is gate leve cell library file (.lib file), and the 3rd type is unbound document (for example the clock unbound document is the .sdc file); The suffix name of the formed gate level netlist file of Verilog, VHDL of output still is respectively .v, and .vhd is consistent with the suffix name of rtl circuit description document.
If in order to promote the processing speed of dual-edge trigger place module, the clock frequency of dual-edge trigger will be consistent along trigger with monolateral so.In the used clock unbound document of logic synthesis (.sdc file), clock frequency that can dual-edge trigger is set to monolateral consistent along trigger.
If in order to reduce power consumption, the heat radiation of dual-edge trigger place module, and keep and adopt monolateral processing speed the same during along trigger, the clock frequency of dual-edge trigger will become monolateral half the along trigger so.Can make amendment this moment to clock unbound document (.sdc file), and the clock frequency of dual-edge trigger is set to the half the of monolateral clock frequency along trigger.
The 4th step, comprehensive back first gate level netlist file and rtl circuit description document are carried out formal verification.Common formal verification tool has conformal, formality etc., and they all support the form of ownership checking in the 4th step, the 7th step.
The 5th step, the comprehensive back first gate level netlist file is carried out functional simulation, this step can be omitted.
The 6th step, the comprehensive back second gate level netlist file is carried out logic optimization, the logic optimization instrument is exactly logic synthesis tool DC, and the suffix name of optimizing back gate leve net meter file still is .v or .vhd file, wherein comprises dual-edge trigger.
Though DC does not support the rtl circuit description document that will comprise dual-edge trigger to convert the gate level netlist file into, support the gate level netlist file that comprises dual-edge trigger is carried out logic optimization.
The 7th step, the description with the dual-edge trigger in the gate leve cell library description document (.v or .vhd file) earlier change into monolateral consistent along trigger, and promptly dual-edge trigger is only in rising edge of clock signal or negative edge work.Carry out formal verification to optimizing back gate leve net meter file with the comprehensive back second gate level netlist file then.Last again with the description recovery former state of the dual-edge trigger in the gate leve cell library description document, promptly dual-edge trigger is all worked in rising edge of clock signal and negative edge.
The 8th step, carry out functional simulation to optimizing back gate leve net meter file.
The 9th step, carry out placement-and-routing according to optimizing back gate leve net meter file.Common placement-and-routing's instrument has SoC Encounter, IC Compiler etc.Owing to there is not the domain cellular construction of dual-edge trigger in the existing domain level cell library file (techfile), the domain cellular construction that also need increase dual-edge trigger therein carries out afterwards placement-and-routing again.Comparison diagram 1～Fig. 3 can know; The area of dual-edge trigger, highly all roughly be monolateral twice along trigger; Thereby the ROW (row) that also need in domain level cell library file, increase dual-edge trigger describes, and promptly writes down its height, carries out placement-and-routing afterwards again.
Can generate clock trees in placement-and-routing's process.Only adopting monolaterally during along trigger, clock trees only need be considered monolateral along the deferred messages such as wire delay outside the domain cellular construction of trigger.After having adopted dual-edge trigger, clock trees also need be considered the wire delay within the domain cellular construction of dual-edge trigger, the deferred message of two path multiplexers.This is that dual-edge trigger can be considered two monolateral combinations along trigger and one two path multiplexer because as shown in Figure 3.
Placement-and-routing's instrument reads gate level netlist file (.v or .vhd file), gate leve cell library file (.lib file), various unbound document (clock unbound document .sdc file, power constraints file etc.), the domain level cell library file (.lef) after the optimization, carries out layout design then.
The 10th step, according to the net meter file after the placement-and-routing or to the extraction after the placement-and-routing net meter file of RC parameter (resistance capacitance parameter) carry out domain level functional simulation.
The 11st the step, the net meter file after the placement-and-routing is carried out layout verification (physical verification).Layout verification tool can adopt placement-and-routing's instrument, also can adopt third party's instrument, for example the Hercules groupware of the Calibre groupware of Mentor company or Synopsys company.
The 12nd step, generation domain GDSII data still adopt placement-and-routing's instrument.
The application's digital integrated circuit design method has been realized the complete compatibility to dual-edge trigger, help promoting digital integrated circuit processing speed, or reduce the power consumption and the heat radiation of digital integrated circuit.
More than be merely the application's preferred embodiment, and be not used in qualification the application.For a person skilled in the art, the application can have various changes and variation.All within the application's spirit and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the application's the protection domain.
Claims (4)
1. a digital integrated circuit design method that comprises dual-edge trigger comprises the step that designs input, logic synthesis, gate leve and the formal verification of RTL level, logic optimization, the gate leve formal verification of optimization front and back, placement-and-routing; It is characterized in that:
When the design input, only adopt monolateral in the rtl circuit description document along trigger;
After logic synthesis, monolateral in the comprehensive back first gate level netlist file that generates partly or entirely changed into dual-edge trigger along trigger, generate the comprehensive back second gate level netlist file; In gate leve cell library file, increase the door of dual-edge trigger simultaneously, in gate leve cell library description document, increase the description of dual-edge trigger;
When gate leve and the formal verification of RTL level, comprehensive back first gate level netlist file and rtl circuit description document are carried out formal verification;
When logic optimization, the comprehensive back second gate level netlist file is carried out logic optimization;
Before optimizing front and back gate leve formal verification; Description with the dual-edge trigger in the gate leve cell library description document earlier changes into monolateral consistent along trigger; Carry out formal verification to optimizing back gate leve net meter file with the comprehensive back second gate level netlist file again, the description with the dual-edge trigger in the gate leve cell library description document recovers former state again;
Before placement-and-routing, the domain cellular construction and the ROW (row) that in domain level cell library file, increase dual-edge trigger earlier describe, and carry out placement-and-routing again; When placement-and-routing, the clock trees that is generated has comprised wire delay and the delay of two path multiplexers within the domain cellular construction of dual-edge trigger.
2. the digital integrated circuit design method that comprises dual-edge trigger according to claim 1; The step that between the step of gate leve and the formal verification of RTL level, logic optimization, also comprises comprehensive back gate leve functional simulation; It is characterized in that; During the gate leve functional simulation, the comprehensive back first gate level netlist file is carried out functional simulation in comprehensive back.
3. the digital integrated circuit design method that comprises dual-edge trigger according to claim 1; It is characterized in that; Before logic synthesis; The clock frequency of dual-edge trigger is set to monolateral consistent along trigger in the clock unbound document, to obtain the double processing speed of dual-edge trigger place module.
4. the digital integrated circuit design method that comprises dual-edge trigger according to claim 1; It is characterized in that; Before logic synthesis; The clock frequency of dual-edge trigger is set to the half the of monolateral clock frequency along trigger in the clock unbound document, with reduce dual-edge trigger place module power consumption and heat radiation.
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| WO2022021091A1 (en) * | 2020-07-28 | 2022-02-03 | 华为技术有限公司 | Clock tree architecture, and clock signal transmission method and device |
| CN116108797A (en) * | 2023-04-06 | 2023-05-12 | 中国人民解放军国防科技大学 | Trigger replacement method and device based on trigger fanout number and storage medium |
| CN116595918A (en) * | 2023-07-18 | 2023-08-15 | 奇捷科技(深圳)有限公司 | Method, device, equipment and storage medium for verifying quick logical equivalence |
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