CN1731915A - Multi-layer circuit board device - Google Patents

Multi-layer circuit board device Download PDF

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Publication number
CN1731915A
CN1731915A CNA2004100558508A CN200410055850A CN1731915A CN 1731915 A CN1731915 A CN 1731915A CN A2004100558508 A CNA2004100558508 A CN A2004100558508A CN 200410055850 A CN200410055850 A CN 200410055850A CN 1731915 A CN1731915 A CN 1731915A
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CN
China
Prior art keywords
resin
high temperature
circuit board
board arrangement
temperature disperses
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Granted
Application number
CNA2004100558508A
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Chinese (zh)
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CN1731915B (en
Inventor
野口高
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to CN2004100558508A priority Critical patent/CN1731915B/en
Publication of CN1731915A publication Critical patent/CN1731915A/en
Priority to HK06108474.2A priority patent/HK1088494A1/en
Application granted granted Critical
Publication of CN1731915B publication Critical patent/CN1731915B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

This invention discloses a multilayer circuit board, which comprises a electron element located on or in the board, a conducting layer linked with the electron element, a high-temperature disfusing resin, adopting insulating material, and allocated to eliminate heat generated by the device, and a molding resin round the electron element, wherein, the heat generated by electron device of the circuit board, is conducted and eliminated by the resin material around about the device. The resion is an insulating material, so needs on consideration of short-circuit problem.

Description

The multilayer circuit panel assembly
Technical field
The present invention relates to a multilayer circuit panel assembly.In more detail, the present invention relates to a SIP (system in package) who wherein has electronic component.
Background technology
Recently, electronic component is installed on a kind of circuit board, so that improve characteristic electron, comprises integrated level, littler package dimension and lower noise effect.After electronic component is installed in a kind of circuit board, by a built-in method wiring layer (conductive layer) layering is put thereon, to form a multilayer circuit panel assembly.Electronic component and wiring layer are with resin moulded.
But according to the multilayer circuit board of a routine, the heat that generates from electronic component is difficult to come out from device radiation and dissipation.Therefore, thermal impedance increases, and power consumption has also increased.In addition, device may be owing to this undesired heat damages, and therefore, reliability of products has also reduced.
A target of the present invention provides a multilayer circuit panel assembly, wherein can dispel the heat effectively.
Another target of the present invention provides the method for a multilayer circuit panel assembly of a kind of making, wherein can dispel the heat effectively.
Other target, advantage and a novel characteristics part of the present invention will be illustrated in the following description, and a part will be conspicuous for the art technology practician after the following explanation of research, perhaps can recognize by realization the present invention.The means that target of the present invention and advantage particularly point out in can the claims by appendix and the method for combination realize and obtain.
Summary of the invention
According to an aspect of the present invention, a kind of circuit board arrangement comprise one be installed on the device or within electronic component; A conductive layer, it is electrically connected to electronic component; A kind of high temperature disperses resin, and it is configured to disperse the heat that generates in the device; And moulding resin around electronic component.
High temperature disperses resin and can form on conductive layer at least.High temperature disperses resin and can form with electronic component and contact.
A kind of circuit board arrangement can further comprise a through hole that is formed in the moulding resin, and wherein high temperature disperses resin and is filled in the through hole.
High temperature disperses resin should be configured to form a heat conduction via, and the heat that generates in the device can disperse well by it.High temperature disperses resin and can be made by a kind of sial system material, and this material has about 0.92 emissivity.
A kind of circuit board arrangement can further comprise a center substrate that forms on device, wherein high temperature disperses a resin-coated surface of covering at the center substrate.High temperature disperses two surfaces that resin can be formed on the center substrate.
A kind of circuit board arrangement can further comprise a conductive frame, and it is formed in the device, and extends device, to be electrically connected to an external plates.Conductive frame can be a copper.
According to the present invention, the heat that generates at a kind of electronic component place of circuit board arrangement is the high temperature disperse material conduction by spreading all over device and disperse.Therefore, can prevent the increase of thermal impedance and power consumption.In addition, device can not damage because of this heat, thereby reliability of products has uprised.
According to another aspect of the present invention, a kind of method that is used to make a multilayer circuit panel assembly may further comprise the steps: a center substrate is provided; A kind of high temperature disperse material of two surface coverage at the center substrate; Form a conductive layer; Electronic component is installed on the conductive layer; And use resin moulded electronic component.
Description of drawings
Fig. 1 is that a width of cloth is described the cross-sectional view according to a multilayer circuit panel assembly of one first first-selected execution mode of the present invention.
Fig. 2 A-2F is a cross-sectional view of describing the making step of a multilayer circuit panel assembly shown in Figure 1.
Fig. 3 is that a width of cloth is described the cross-sectional view according to a multilayer circuit panel assembly of one second first-selected execution mode of the present invention.
Fig. 4 A-4G is a cross-sectional view of describing the making step of a multilayer circuit panel assembly shown in Figure 3.
Embodiment
In following detailed description to first-selected execution mode, with reference to accompanying drawing, accompanying drawing forms a part herein, and has wherein shown by the mode of describing and can realize concrete first-selected execution mode of the present invention.With sufficient specification specified these first-selected execution modes so that the art technology practician realizes the present invention, and be appreciated that and use other first-selected execution modes, and can under the situation that does not deviate from the spirit and scope of the present invention, make the change of machinery and electronics.Therefore, below describe in detail and do not understand with regard to limited significance, scope of the present invention is only limited by claims of appendix.
Fig. 1 is that a width of cloth is described the cross-sectional view according to a multilayer circuit panel assembly 10 of one first first-selected execution mode of the present invention.Multilayer circuit panel assembly 10 comprise be installed on the device or within electronic component (14 and 16); Conductive layer (22), it is electrically connected to electronic component (14 and 16); High temperature disperses resin (26a, 26b and 26c), and these resins are configured to disperse the heat that generates in the device 10; And moulding resin 30 around electronic component (14 and 16).
Multilayer circuit panel assembly 10 further comprises a center substrate 12; Electrode 18: connecting terminal 20 and the through hole (through hole) 24 that is used to be electrically connected.Connecting terminal 20 can be solder sphere.
Electronic component comprises semiconductor chip 14 and passive device 16.Center substrate 12 is made by a kind of glass epoxide material.Moulding resin 30 is a kind of epoxy resin, for example prepreg.High temperature disperses resin 26a and covers on two surfaces of center substrate 12.High temperature disperses resin 26b and covers on the surface of intermediate conductive layer 22, and these intermediate conductive layers form in device 10.Another kind of high temperature disperses resin 26c and is filled in the through hole, is not used in electrical connection, but is used for heat conduction.
Semiconductor chip 14 is directly installed on high temperature and disperses on the resin 26a.The connecting terminal of semiconductor chip 14 is electrically connected to conductive layer 22.Passive device 16 is directly installed on high temperature and disperses on the resin 26b.
High temperature disperses resin 26a, 26b and 26c is designed and is configured to form a heat conduction via, and the heat that generates in the device 10 can conduct well and disperses by it.High temperature disperses resin 26a, 26b and 26c and can be about 0.92 sial system material by a kind of emissivity and make.It is a kind of insulating material that high temperature disperses resin, is nonconducting.
Usually, pottery is lower than the thermal conductivity of metal (for example copper); But the emissivity (0.92) of pottery is than (0.03) height of copper.According to the present invention, a kind of high temperature disperse material only conducts heat under the situation of not short circuit.The pottery of a liquid state can be used as high temperature disperse material (resin), " the Cerac-α " that it can be produced for the Ceramission Co., Ltd by the Tokyo.
Multilayer circuit panel assembly 10 is made with construction method in a kind of after electronic component 14 and 16 have been installed.
Fig. 2 A-2F is a cross-sectional view of describing the making step of multilayer circuit panel assembly 10 shown in Figure 1.At first, shown in Fig. 2 A, a kind of high temperature disperses resin and is sprayed and cover on two surfaces of center substrate 12.Next, shown in Fig. 2 B, the bottom surface of semiconductor chip 14 is directly mounted to high temperature and disperses on the resin.After this, resin is dispersed a layer 26a by thermmohardening with the high temperature that formation thickness is about 30 μ m to 200 μ m.
Then, semiconductor chip 14 is resin moulded by a kind of epoxy resin (for example prepreg), and resin by thermmohardening to form moulding resin 30, shown in Fig. 2 C.Moulding resin layer 30 has and extends to the hole that high temperature disperses layer 26a.These holes are filled with a kind of high temperature and disperse resin, and are heated with sclerosis.It is a heat passage that high temperature in the hole disperses resin 26c, so that will be in device, especially the heat in electronic component 14 and the generation of 16 places be transmitted to the outside.
Next, form conduction mode (conductive layer) 22 in a (cathode) sputtering process and an electroplating process, a kind of then high temperature disperses resin-coated the lid on conductive layer 22.After this, resin is heated with sclerosis, disperses a layer 26b to form high temperature, shown in Fig. 2 D.The electrode of semiconductor chip 14 is electrically connected to conductive layer 22.
Then, shown in Fig. 2 E, passive device 16 is installed to high temperature and is dispersed on layer 26b, and by resin moulded.Resin is by thermmohardening (heating and harden), and to form moulding resin layer 30, it has the hole (through hole) that extends to high temperature and disperse layer 26b.These holes are filled with a kind of high temperature and disperse resin, and resin is heated with sclerosis.High temperature in the hole disperses resin 26c and plays a heat passage, so that in will installing, especially the heat conduction of electronic component 14 and 16 places generation outwards.In moulding resin 30, form through hole 24 to be used for electrical connection.
Shown in Fig. 2 F, conductive layer 22 is formed on the upper space of device, and electronic component (14 and 16) is installed on the conductive layer 22.After this, as shown in Figure 1, be used for the outside electrode 18 that connects and be formed on the bottom surface of device, and on electrode 18, provide connecting terminal 20, for example solder sphere.The multilayer circuit panel assembly of producing like this 10 can be installed on the mainboard.
According to the above-mentioned first first-selected execution mode, the heat that generates at the electronic component place of device disperses resin 26a, 26b and 26c conduction and disperses center substrate 12 and connecting terminal 20 by high temperature, so that heat disperses on whole device.Therefore, can prevent the increase of thermal impedance and power consumption.In addition, device can not damage because of heat, thereby reliability of products has uprised.
In addition, be insulating material because high temperature disperses resin, therefore needn't consider the short circuit problem in the device.Talk about by sentence, the freedom of circuit design is not subjected to high temperature to disperse the interference of resin.
Fig. 3 is that a width of cloth is described the cross-sectional view according to a multilayer circuit panel assembly 100 of one second first-selected execution mode of the present invention.In Fig. 3, identical with Fig. 1 or corresponding element is represented by identical reference number, and will can not repeated identical explanation.Multilayer circuit panel assembly 100 comprise be installed on the device or within electronic component (14 and 16); Conductive layer (22), it is electrically connected to electronic component (14 and 16); High temperature disperses resin (26a, 26b and 26c), and these resins are configured to disperse the heat that generates in the device 100; And moulding resin 30 around electronic component (14 and 16).
Multilayer circuit panel assembly 100 further comprises a copper framework 112; Electrode 18: connecting terminal 20 and the through hole 24 that is used to be electrically connected.Connecting terminal 20 can be solder sphere.
Electronic component comprises semiconductor chip 14 and passive device 16.Moulding resin 30 is a kind of epoxy resin, for example prepreg.High temperature disperses resin 26b and covers on the surface of intermediate conductive layer 22, and these intermediate conductive layers form in device 100.A kind of high temperature disperses resin 26c and is filled in the through hole, is used for non-electric-connecting.
Semiconductor chip 14 is directly installed on the copper framework 112.The connecting terminal of semiconductor chip 14 is electrically connected to conductive layer 22.Some passive devices 16 are directly installed on high temperature and disperse on the resin 26b.
High temperature disperses resin 26b and 26c is designed and is configured to form a heat conduction via, and the heat that generates in the device 100 can disperse well by it.High temperature disperses resin 26b and 26c and can be about 0.92 sial system material by a kind of emissivity and make.It is a kind of insulating material that high temperature disperses resin, is nonconducting.Usually, pottery is lower than the thermal conductivity of metal (for example copper); But the emissivity (0.92) of pottery is than (0.03) height of copper.According to the present invention, a kind of high temperature disperse material only conducts heat under the situation of not short circuit.
Multilayer circuit panel assembly 100 is made with construction method in a kind of after electronic component 14 and 16 have been installed.
Copper framework 112 has terminal, and these terminals are used as the lead that is connected to a mainboard (not shown).According to the second first-selected execution mode, can apply a underlayer voltage (electromotive force) to the terminal of copper framework 112.
Fig. 4 A-4G is a cross-sectional view of describing the making step of multilayer circuit panel assembly 100 shown in Figure 3.At first, shown in Fig. 4 A, equip a copper (metal) framework 112.Next, shown in Fig. 4 B, the bottom surface of semiconductor chip 14 is directly installed or is bonded on two surfaces of copper framework 112.After this, shown in Fig. 4 C, semiconductor chip 14 is resin moulded by a kind of epoxy resin (for example prepreg), and resin by thermmohardening to form moulding resin 30.Moulding resin layer 30 has the hole that extends to copper framework 112.These holes are filled with a kind of high temperature and disperse resin, and are heated with sclerosis.High temperature in the hole disperses resin 26c and plays a heat passage, so that the heat that will generate in device conduction outwards.
Next, form conduction mode (conductive layer) 22 in a (cathode) sputtering process and an electroplating process, a kind of then high temperature disperses resin-coated the lid on conductive layer 22.After this, resin is heated with sclerosis, disperses a layer 26b to form high temperature, shown in Fig. 4 D.The electrode of semiconductor chip 14 is electrically connected to conductive layer 22.
Then, shown in Fig. 4 E, passive device 16 is installed to high temperature and is dispersed on layer 26b, and by resin moulded.Resin is by thermmohardening (heating and harden), and to form moulding resin layer 30, it has the hole (through hole) that extends to high temperature and disperse layer 26b.These holes are filled with a kind of high temperature and disperse resin, and resin is heated with sclerosis.High temperature in the hole disperses resin 26c and plays a heat passage, so that in will installing, especially the heat conduction of electronic component 14 and 16 places generation outwards.In moulding resin 30, form through hole 24 to be used for electrical connection.
Next, shown in Fig. 4 F, conductive layer 22 is formed on the upper space of device, and electronic component (14 and 16) is installed on the conductive layer 22.After this, shown in Fig. 4 G, be used for the outside electrode 18 that connects and be formed on the bottom surface of device, and on electrode 18, provide connecting terminal 20, for example solder sphere.
After this, as shown in Figure 3, with the terminal of a molding die or the crooked outward extending copper framework 112 of similar thing, so that crooked terminal is used as the lead that is connected to a mainboard.
According to the above-mentioned second first-selected execution mode, the heat that generates at the electronic component place of device disperses resin 26b and 26c conduction and disperses copper framework 112 and connecting terminal 20 by high temperature, so that heat disperses on whole device.Therefore, can prevent the increase of thermal impedance and power consumption.In addition, device can not damage because of heat, thereby reliability of products has uprised.
In addition, be insulating material because high temperature disperses resin, therefore needn't consider the short circuit problem in the device.Talk about by sentence, the freedom of circuit design is not subjected to high temperature to disperse the interference of resin.

Claims (26)

1. circuit board arrangement comprises:
One be installed on the described device or within electronic component;
A conductive layer, it is electrically connected to described electronic component;
A kind of high temperature disperses resin, and it is an insulating material, and is configured to disperse the heat that generates in the device; And
Moulding resin around described electronic component.
2. according to a kind of circuit board arrangement of claim 1, wherein
High temperature disperses resin and covers on the conductive layer at least.
3. according to a kind of circuit board arrangement of claim 1, wherein
High temperature disperses resin-shaped to be become with electronic component and contacts.
4. according to a kind of circuit board arrangement of claim 1, further comprise:
Be formed on a through hole in the moulding resin, wherein
High temperature disperses resin and is filled in the through hole.
5. according to a kind of circuit board arrangement of claim 1, wherein
High temperature disperses resin and covers on conductive layer and the electronic component.
6. according to a kind of circuit board arrangement of claim 5, further comprise
Be formed on a through hole in the moulding resin, wherein
High temperature disperses resin and is filled in the through hole.
7. according to a kind of circuit board arrangement of claim 6, wherein
High temperature disperses resin and is configured to form a heat conduction via, and the heat that generates in the described device can disperse well by it.
8. according to a kind of circuit board arrangement of claim 1, wherein
High temperature disperses resin and is about 0.92 sial system material by a kind of emissivity and makes.
9. according to a kind of circuit board arrangement of claim 1, further comprise:
Be formed on a center substrate in the device, wherein
High temperature disperses resin and covers on the surface of center substrate.
10. according to a kind of circuit board arrangement of claim 9, wherein
High temperature disperses resin and covers on two surfaces of center substrate.
11. according to a kind of circuit board arrangement of claim 9, wherein
High temperature disperses resin and covers on the conductive layer.
12. according to a kind of circuit board arrangement of claim 9, wherein
High temperature disperses resin and is formed with electronic component and contacts.
13. a kind of circuit board arrangement according to claim 9 further comprises:
Be formed on a through hole in the moulding resin, wherein
High temperature disperses resin and is filled in the through hole.
14. according to a kind of circuit board arrangement of claim 9, wherein
High temperature disperses resin and covers on conductive layer and the electronic component.
15. a kind of circuit board arrangement according to claim 14 further comprises:
Be formed on a through hole in the moulding resin, wherein
High temperature disperses resin and is filled in the through hole.
16. according to a kind of circuit board arrangement of claim 15, wherein
High temperature disperses resin and is configured to form a heat conduction via, and the heat that generates in the described device can disperse well by it.
17. according to a kind of circuit board arrangement of claim 9, wherein
High temperature disperses resin and is about 0.92 sial system material by a kind of emissivity and makes.
18. a kind of circuit board arrangement according to claim 1 further comprises:
A conductive frame, it is formed in the device, and extends device, to be electrically connected to an external plates.
19. according to a kind of circuit board arrangement of claim 18, wherein
Conductive frame is that copper becomes.
20. according to a kind of circuit board arrangement of claim 18, wherein
High temperature disperses resin and covers on the conductive layer.
21. according to a kind of circuit board arrangement of claim 18, wherein
High temperature disperses resin and is configured to contact with electronic component.
22. a kind of circuit board arrangement according to claim 18 further comprises:
Be formed on a through hole in the moulding resin, wherein
High temperature disperses resin and is filled in the through hole.
23. according to a kind of circuit board arrangement of claim 18, wherein
High temperature disperses resin and covers on conductive layer and the electronic component.
24. a kind of circuit board arrangement according to claim 23 further comprises:
Be formed on a through hole in the moulding resin, wherein
High temperature disperses resin and is filled in the through hole.
25. according to a kind of circuit board arrangement of claim 24, wherein
High temperature disperses resin and is configured to form a heat conduction via, and the heat that generates in the described device can disperse well by it.
26. according to a kind of circuit board arrangement of claim 18, wherein
High temperature disperses resin and is about 0.92 sial system material by a kind of emissivity and makes.
CN2004100558508A 2004-08-04 2004-08-04 Multi-layer circuit board device Expired - Fee Related CN1731915B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2004100558508A CN1731915B (en) 2004-08-04 2004-08-04 Multi-layer circuit board device
HK06108474.2A HK1088494A1 (en) 2004-08-04 2006-07-31 Multi-layered circuit board assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2004100558508A CN1731915B (en) 2004-08-04 2004-08-04 Multi-layer circuit board device

Publications (2)

Publication Number Publication Date
CN1731915A true CN1731915A (en) 2006-02-08
CN1731915B CN1731915B (en) 2010-11-10

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CN101958312A (en) * 2009-07-16 2011-01-26 株式会社电装 Electronic control unit
CN101640972B (en) * 2008-07-28 2011-09-07 欣兴电子股份有限公司 Circuit board structure
US8436254B2 (en) 2008-07-14 2013-05-07 Unimicron Technology Corp. Method of fabricating circuit board structure
CN105659375A (en) * 2014-09-26 2016-06-08 英特尔公司 Flexible packaging architecture
CN106163092A (en) * 2016-08-20 2016-11-23 成都云士达科技有限公司 A kind of board structure of circuit manufacture method carrying heat sinking function
CN109413836A (en) * 2017-08-15 2019-03-01 鹏鼎控股(深圳)股份有限公司 Circuit board and preparation method thereof

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Publication number Priority date Publication date Assignee Title
KR100371877B1 (en) * 1997-04-16 2003-02-11 가부시끼가이샤 도시바 Wiring board, wiring board fabrication method, and semiconductor package
WO1999042523A1 (en) * 1998-02-23 1999-08-26 Asahi Kasei Kogyo Kabushiki Kaisha Thermosetting polyphenylene ether resin composition, cured resin composition obtained therefrom, and laminated structure
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8436254B2 (en) 2008-07-14 2013-05-07 Unimicron Technology Corp. Method of fabricating circuit board structure
CN101640972B (en) * 2008-07-28 2011-09-07 欣兴电子股份有限公司 Circuit board structure
CN101958312A (en) * 2009-07-16 2011-01-26 株式会社电装 Electronic control unit
US8355254B2 (en) 2009-07-16 2013-01-15 Denso Corporation Electronic control unit
CN101958312B (en) * 2009-07-16 2013-08-28 株式会社电装 Electronic control unit
CN105659375A (en) * 2014-09-26 2016-06-08 英特尔公司 Flexible packaging architecture
US10396038B2 (en) 2014-09-26 2019-08-27 Intel Corporation Flexible packaging architecture
CN106163092A (en) * 2016-08-20 2016-11-23 成都云士达科技有限公司 A kind of board structure of circuit manufacture method carrying heat sinking function
CN106163092B (en) * 2016-08-20 2020-01-14 惠州市纬德电路有限公司 Manufacturing method of circuit board structure with heat dissipation function
CN109413836A (en) * 2017-08-15 2019-03-01 鹏鼎控股(深圳)股份有限公司 Circuit board and preparation method thereof
CN109413836B (en) * 2017-08-15 2021-04-20 鹏鼎控股(深圳)股份有限公司 Circuit board and preparation method thereof

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