CN1725181A

CN1725181A - Buffering method of SDH class logical simulation excitation data

Info

Publication number: CN1725181A
Application number: CN 200410054777
Authority: CN
Inventors: 程智辉; 李伟东; 潘武飞
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2004-07-20
Filing date: 2004-07-20
Publication date: 2006-01-25
Anticipated expiration: 2024-07-20
Also published as: CN1300686C

Abstract

This invention relates to a method for buffering SDH kind logic emulation excitation data including: A, a message generation module generates an initial message to be put into a FIFO device, B, a LAPS package module takes a certain volume of message from the FIFO device to package and put them into a second FIFO device, C, a VC4 virtual cascade image module gets the packaged message from the second FIFO device to carry out VC4 image to generate STM-1 frame to be put in a third FIFO device, D, a bus interface conversion module gets STM-1 frame data from a third FIFO device for the bus interface conversion to generate bus data to be put in a fourth FIFO device to be transmitted to a tested device.

Description

A kind of SDH logic of class emulation excited data caching method

Technical field

The present invention relates to communicate by letter or the emulation technology of electronic applications, refer to a kind of SDH logic of class emulation excited data caching method especially.

Background technology

At SDH (Synchronous Digital Hierarchy, SDH (Synchronous Digital Hierarchy)) in the logic of class emulation, it is the work of a complexity that excitation produces, because the agreement that SDH relates to is numerous, complex disposal process, middle meeting produces a large amount of ephemeral datas, and how reasonably managing and using these ephemeral datas is the difficult point that the emulation personnel face always.

At present in the emulation of the SDH logic of class, it is that each required module in the excitation production process is designed to one by one independently program (be presented as and contain the principal function that a name is called main) in C/C++ that excitation produces the method that adopts, each independently the ephemeral data that produces of program will write in the file, next then relevant stand-alone program obtains needed data and handles from this document, after disposing, write once more in the another one file and use, by that analogy for next relevant stand-alone program.Processing procedure is shown in Figure 1.

As mentioned above, can produce a large amount of ephemeral datas because the complicacy of SDH logic of class agreement makes in the processing procedure, prior art is that all ephemeral datas are deposited in the data file, and data file is to be kept on the hard disk, and its storage speed is slow.Because data are not one-time writes, so need the frequent visit hard disk, make simulation efficiency very low, simulation velocity is very slow.Because each module all is an independent executable program one by one, each other without any contact, make the excitation production process not control on the whole in addition, the automaticity of emulation is not high; And the parameter of each module all is the form configuration by file, and in a single day parameter configures the back and just be difficult to change once more, use to the user and bring very big inconvenience.

Summary of the invention

The invention provides a kind of SDH logic of class emulation excited data caching method, solve that SDH logic of class simulation velocity is slow, parameter configuration and revise the problem of inconvenience.

SDH logic of class emulation excited data caching method provided by the invention comprises the following steps:

A) a message generation module generates initial message, and initial message is put into a FIFO (first in first out) device;

B) a LAPS module obtains message and carries out LAPS encapsulation from a FIFO device, and the message after the encapsulation is put into the 2nd FIFO device;

C) message obtained from the 2nd FIFO device after the encapsulation of a VC4 Virtual Concatenation mapping block carries out the mapping of VC4 Virtual Concatenation, generates the STM-1 frame, puts into the 3rd FIFO device;

D) a bus interface modular converter is obtained the STM-1 frame data from the 3rd FIFO device, carries out the bus interface conversion, generates bus data, puts into the 4th FIFO device; Again the bus data that generates is sent to tested equipment.

According to said method of the present invention, described each module all is provided with corresponding graphical parameter configuration interface, realizes dynamic access and revises the parameter of each module.

According to said method of the present invention, described each module is in a described FIF0 device, the 2nd FIFO device, the 3rd FIFO device before the reading of data, to whether be that sky is checked to the FIFO device of being visited,, then end reading of data if described FIF0 device is empty.。

According to said method of the present invention, pass through PLI (language interface able to programme) interface Data transmission between described bus interface modular converter and the tested equipment.

According to said method of the present invention, the described first, second, third and the 4th FIFO device is a calculator memory.

Advantage of the present invention is as follows:

1, improves the efficient that excitation produces in the emulation of the SDH logic of class, accelerate simulation velocity;

2, excitation in the emulation of the SDH logic of class is produced the various protocols that relates to and be combined into an integral body, improve the automaticity of emulation;

3, the present invention no longer needs to be saved in the file to go to the ephemeral data of centre, and all is kept in the internal memory of computing machine in the mode of FIFO, can be fast the ephemeral data of centre be conducted interviews.

Description of drawings

Fig. 1 is a SDH logic of class emulation excited data production process synoptic diagram in the prior art.

Fig. 2 is a SDH logic of class emulation excited data production process synoptic diagram of the present invention.

Embodiment

Technical scheme provided by the invention is different from prior art scheme part and is: the one, consider all modules that SDH logic of class emulation excitation produces on the whole, and no longer be independent of each other between each module, but front and back are related; The 2nd, employing FIFO device (storage medium can be the internal memory of computing machine) is replaced the file (storage medium is the hard disk of computing machine) in original technical scheme, can accelerate to encourage the access speed of generating routine so greatly to middle data, and the parameter of all configurations leaves in the internal memory, can be by designing the value of the parameter that corresponding each module of graphic interface dynamic access relates to.

The course of work that SDH logic of class emulation excited data of the present invention produces is described below as shown in Figure 2:

1, generates the initial message that needs by a message generation module, initial message is put into FIFO A;

2, obtain a certain amount of message from the FIFO A of initial message and carry out LAPS (Link AccessProcedure-SDH, link access procedure SDH) encapsulation, the message after the encapsulation is put into FIFO B;

3, the data stream that obtains from FIFO B after the encapsulation process is carried out the mapping of VC4 Virtual Concatenation, generates the STM-1 frame, puts into FIFO C;

4, from FIFO C, obtain the STM-1 frame data, carry out the bus interface conversion and generate bus data, put into FIFO D; From FIFO D, obtain bus data at last, send to DUT by the PLI interface.

Each module that occurs in Fig. 2 all has corresponding patterned parameter configuration interface, can visit the parameter that (read and revise) this module relates to dynamically, and whether each module can be that sky is checked to accessed FIFO all, if FIFO is that empty situation is (in processing procedure, pass through the FIFO swap data between the module, be to put into FIFO after the good data of resume module of front to take for subordinate's module, when taking data among the FIFO, subordinate's module may get sky to the data among the FIFO, and the data among the possibility FIFO are not enough, also need to previous stage module request for data.), then to return, treatment scheme is ended.

FIFO is a kind of buffer storage of first in first out, shows as one section internal memory that computing machine distributes in computing machine.Can use various FIFO devices to realize.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.

Claims

1, a kind of SDH logic of class emulation excited data caching method is characterized in that, comprises the following steps:

B) a LAPS package module is obtained message and is carried out LAPS encapsulation from a FIFO device, and the message after the encapsulation is put into the 2nd FIFO device;

2, SDH logic of class emulation excited data caching method as claimed in claim 1 is characterized in that: described each module all is provided with corresponding graphical parameter configuration interface, realizes dynamic access and revises the parameter of each module.

3, SDH logic of class emulation excited data caching method as claimed in claim 1 or 2, it is characterized in that: described each module is in a described FIFO device, the 2nd FIFO device, the 3rd FIFO device before the reading of data, to whether be that sky is checked to the FIFO device of being visited, if described FIFO device is empty, then end reading of data.

4, SDH logic of class emulation excited data caching method as claimed in claim 1 or 2 is characterized in that: pass through PLI (language interface able to programme) interface Data transmission between described bus interface modular converter and the tested equipment.

5, SDH logic of class emulation excited data caching method as claimed in claim 4, it is characterized in that: the described first, second, third and the 4th FIFO device is a calculator memory.