CN114281412A

CN114281412A - Message processing method and device, electronic equipment and storage medium

Info

Publication number: CN114281412A
Application number: CN202111601371.1A
Authority: CN
Inventors: 岳明; 黄定江; 蒋红月; 陈刚; 崔江鹤; 张宇峰; 李忠
Original assignee: China Telecom Digital Intelligence Technology Co Ltd
Current assignee: China Telecom Digital Intelligence Technology Co Ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2022-04-05
Also published as: WO2023116558A1

Abstract

The application provides a message processing method, a message processing device, electronic equipment and a storage medium. The method is applied to electronic equipment carrying an FPGA chip, the FPGA comprises cascade-connected first-in first-out memories FIFO, and the method comprises the following steps: acquiring a message body set to be processed and a macro definition file generated in advance according to a configuration file, wherein the configuration file comprises read-write states and bit widths corresponding to all message bodies in FIFO (first in first out) at each level; allocating required processing resources for each stage of FIFO according to the read-write state and bit width corresponding to the message body in each stage of FIFO; and controlling the FIFOs at all levels to respectively process the message bodies in the message body set to be processed by utilizing the allocated processing resources. By acquiring the message body set to be processed and the macro definition file and then distributing the processing resources required by the FIFOs at all levels according to the macro definition file, the resources in the FPGA are fully utilized, and the waste of the resources is avoided.

Description

Message processing method and device, electronic equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a message processing method and apparatus, an electronic device, and a storage medium.

Background

As the FPGA chip is more and more abundantly applied to application technology scenarios involving message processing, including, for example, virtualization scenarios, network application processing scenarios, data center heterogeneous design, and the like, the FPGA chip plays an important role.

Currently, there are two mainstream FPGA message processing methods: the first is the realization of a random access memory RAM based on an open address, each message body independently occupies an address, all message bodies share an address bus, the preemption of address lines can occur among a plurality of users, a unified controller is required for scheduling, and the message processing speed needs to be improved; the other is based on the realization of a first-in first-out memory FIFO, all message bodies processed by all levels of FIFO are combined into a message body set, the pipeline design in an FPGA is realized by utilizing the multiple levels of FIFO, the linear speed processing of the message processing is realized, but the processing resources needed by the message body set are overlarge and consume resources.

Disclosure of Invention

An object of the embodiments of the present application is to provide a message processing method, a message processing apparatus, an electronic device, and a storage medium, so as to reduce waste of resources in an FPGA.

In a first aspect, an embodiment of the present application provides a message processing method, which is applied to an electronic device equipped with a field programmable gate array FPGA, where the FPGA includes cascaded first-in first-out memories FIFO at different levels, and the method includes: acquiring a message body set to be processed and a macro definition file generated in advance according to a configuration file, wherein the message body set to be processed comprises a plurality of message bodies, and the configuration file comprises read-write states and bit widths corresponding to the message bodies in FIFO (first in first out) at all levels; allocating required processing resources for each stage of FIFO according to the read-write state and bit width corresponding to the message body in each stage of FIFO; and controlling the FIFOs at all levels to respectively process the message bodies in the message body set to be processed by utilizing the allocated processing resources.

In the embodiment of the application, by acquiring a message body set to be processed and a macro definition file generated according to a configuration file, the message body set to be processed comprises a plurality of message bodies, the configuration file comprises read-write states and bit widths corresponding to the message bodies in each stage of FIFO, required processing resources can be respectively allocated to the FIFO of each stage according to the read-write states and the bit widths corresponding to the message bodies in the FIFO of each stage, and then the FIFO of each stage is controlled to process the message bodies in the message body set to be processed by using the allocated processing resources. The flexible allocation of the processing resources in the FIFO of each level is realized through the setting of the configuration files, and the waste of the FIFO resources of each level is avoided.

Further, the allocating required processing resources for each level of FIFO according to the read-write state and bit width corresponding to the message body in each level of FIFO includes: respectively and dynamically adjusting the message bodies included in the message body set to be processed according to the read-write state corresponding to the message body in each level of FIFO to obtain a target message body set to be processed corresponding to each level of FIFO; determining the total bit width of the target message body set to be processed corresponding to each level of FIFO according to the bit width corresponding to the message body included in the target message body set to be processed corresponding to each level of FIFO; and allocating processing resources for the corresponding FIFO according to the total bit width of the target message body set to be processed corresponding to each stage of the FIFO.

In the embodiment of the application, the message bodies included in the message body set to be processed are dynamically adjusted according to the read-write states corresponding to the message bodies in each stage of FIFO to obtain the target message body set to be processed corresponding to each stage of FIFO, then the total bit width of the target message body set to be processed corresponding to each stage of FIFO is determined according to the bit width corresponding to the message bodies included in the target message body set to be processed corresponding to each stage of FIFO, and the processing resources can be allocated to the corresponding FIFO according to the total bit width of the target message body set to be processed. The processing resources required by the FIFOs at all levels can be calculated through the read-write state and bit width of each message body configured in the configuration file in the FIFOs at all levels, so that the reasonable distribution of the resources is realized, and the waste of the resources is avoided.

Further, the read-write state includes one of read-write, read-only, write-only, and transparent transmission, and the dynamically adjusting the message bodies included in the message body set to be processed according to the read-write state corresponding to the message bodies in each level of FIFO includes: and removing the message body of which the read-write state is transparent transmission from the message body set to be processed in each stage of FIFO.

In the embodiment of the application, the read-write state of the message body can comprise one of read-write, read-only, write-only and transparent transmission, and the message body with the read-write state in each level of FIFO as transparent transmission is removed from the message body set to be processed, so that a target message body set to be processed corresponding to each level of FIFO is obtained, compression of the message body set structure body to be processed of each level of FIFO is realized, processing resources required by each level of FIFO are reduced, and waste of void resources is avoided.

Further, the controlling each level of FIFO respectively utilizes the allocated processing resources to process the message body in the set of message bodies to be processed, including: determining a survival interval corresponding to each message body, wherein the survival interval is each level of FIFO in cascade connection and comprises an interval starting point and an interval end point; and taking the message body processed by the upper-level FIFO as the input of the lower-level FIFO according to the survival interval until the processing of the message body by the corresponding FIFO of each level in the survival interval is finished by utilizing the processing resources corresponding to the FIFO of each level.

In the embodiment of the application, by determining the survival interval corresponding to each message body, the survival interval is each level of FIFO including the interval starting point and the interval ending point, the message body processed by the upper level FIFO can be used as the input of the lower level FIFO according to the survival interval until the processing of the message body by each level of FIFO in the living space is completed by using the processing resources corresponding to each level of FIFO. Therefore, the processing of each message body by each stage of FIFO is realized, and the full utilization of processing resources is realized.

Further, the obtaining of the macro definition file generated in advance according to the configuration file includes: acquiring a pre-compiled configuration file; and translating the configuration file to generate a macro definition file which can be executed on an FPGA chip carried by the electronic equipment.

In the embodiment of the application, the configuration file is translated by acquiring the pre-programmed configuration file, so that the macro definition file which can be executed on the FPGA chip loaded on the electronic equipment is generated. Through the translation mode of the configuration file, the flexible arrangement of the macro definition file is realized, the adjustment of the corresponding message body sets in all levels of FIFO and the change of processing resources are facilitated, and the development efficiency of developers is improved.

Further, the method further comprises: modifying the corresponding read-write state or bit width of the message body in each stage of FIFO in the configuration file; or, defining a new message body in the configuration file, and adding the corresponding read-write state and bit width of the new message body in each stage of FIFO.

In the embodiment of the application, the read-write state or bit width of the included message body corresponding to each stage of FIFO can be modified in the configuration file, a new message body can be defined in the configuration file, and the read-write state and bit width of the message body corresponding to each stage of FIFO are increased, so that the modification of the configuration file on the FPGA is realized, the message processing design of each stage of FIFO on the FPGA is favorably adjusted, and the flexibility and configurability of the FPGA design are improved.

Further, the method further comprises: defining a new FIFO and a corresponding cascade position in the configuration file, and defining the read-write state and bit width of each message body in the new FIFO.

In the embodiment of the application, a new FIFO and the cascade position of the FIFO are defined in the configuration file, and then the read-write state and bit width of each message body in the FIFO are defined, so that the processing logic design of the FIFO is rapidly realized, and the message processing efficiency of the FPGA is further improved.

In a second aspect, an embodiment of the present application provides a message processing apparatus, where the apparatus includes: the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a message body set to be processed and a macro definition file generated in advance according to a configuration file, the message body set to be processed comprises a plurality of message bodies, and the configuration file comprises read-write states and bit widths corresponding to the message bodies in FIFO (first in first out) at each level; the distribution module is used for distributing required processing resources for each stage of FIFO according to the read-write state and bit width corresponding to the message body in each stage of FIFO; and the control module is used for controlling each stage of FIFO to respectively utilize the allocated processing resources to process the message bodies in the message body set to be processed.

In a third aspect, an embodiment of the present application provides an electronic device, including: the system comprises a processor, a memory and a bus, wherein the processor and the memory complete mutual interaction through the bus;

the memory stores program instructions executable by the processor, the processor being capable of performing the method of the first aspect when invoked by the program instructions.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including:

the computer readable storage medium stores computer instructions which cause the computer to perform the method of the first aspect.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic flowchart of a message processing method according to an embodiment of the present application;

fig. 2 is a schematic diagram of a specific processing procedure of a single FIFO according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a variation of a single FIFO message body according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Before introducing a message processing method provided in the embodiment of the present application, some concepts related in the embodiment of the present application are introduced:

FPGA (Field Programmable Gate Array, also called large-scale Programmable logic circuit): the product of further development on the basis of programmable devices. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

FIFO (First Input First Output memory): is a first-in first-out double-port buffer, i.e. the first data entering it is shifted out first, one of them is the input port of the memory and the other is the output port of the memory. With the characteristics of flexibility, convenience and high efficiency, the system is gradually widely applied to high-speed data acquisition, high-speed data processing, high-speed data transmission and multi-machine processing systems.

pipeline streamline design: a method of systematically dividing the combinational logic and inserting registers between the respective sections (stages) and temporarily storing intermediate data. The purpose is to decompose a large operation into a plurality of small operations, the time of each small operation is shorter, so the frequency can be improved, and the small operations can be executed in parallel, so the data throughput rate can be improved, and the line speed processing of various levels of FIFO can be realized.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Fig. 1 is a schematic flow chart of a message processing method according to an embodiment of the present disclosure, and as shown in fig. 1, the method may be applied to an electronic device equipped with a field programmable gate array FPGA, where the FPGA includes cascaded FIFOs, and the FPGA employs multiple cascaded FIFOs and a pipeline streamline design, so as to implement linear speed processing of a message body; the electronic device may be a smart phone, a tablet computer, a Personal Digital Assistant (PDA), a server, or the like; the server may specifically be an application server, and may also be a Web server. The method comprises the following steps:

step 101: the method comprises the steps of obtaining a message body set to be processed and a macro definition file generated in advance according to a configuration file, wherein the message body set to be processed comprises a plurality of message bodies, and the configuration file comprises read-write states and bit widths corresponding to the message bodies in FIFO (first in first out) of each level.

In a specific implementation process, the set of message bodies to be processed may be a set of message bodies processed in each stage of FIFO in the FPGA, and multiple message bodies may be in the set of message bodies to be processed, and each message body may be processed by a different FIFO. The configuration file can be a mapping file written by some high-level programming languages such as Python and Java, the configuration file can define the corresponding read-write state and bit width of each message body in each level of FIFO, the read-write state can be the read-write processing of FIFO to the message body such as read-write, read-only, write-only, etc., the bit width can be the data size occupied by the message body, such as 4bit and 8bit, and is related to the size of the message body, and the flexible conversion with the macro definition file can be realized by using the configuration file. The macro definition file can be a file of system verilog attribute executable on FPGA, the system verilog is a bottom-layer hardware description and verification language, is mainly positioned on the realization and verification process of a chip, provides strong connection capability for the design process of a system level, and can realize flexible design of a message body in a mode of pre-generating a configuration file.

Step 102: and allocating required processing resources for each stage of FIFO according to the read-write state and bit width corresponding to the message body in each stage of FIFO.

In a specific implementation process, in order to ensure that the size of the processing resource of each stage of the FIFO can accommodate the message body set to be processed corresponding to the FIFO, the processing resource required by each stage of the FIFO can be allocated according to the read-write state and bit width of each message body configured in the configuration file in each stage of the FIFO, the processing resource can be a random storage RAM resource required by each stage of the FIFO, and the electronic device can allocate the RAM resource required by each stage of the FIFO according to the writing and reading of the message body set to be processed by each stage of the FIFO, thereby realizing the maximum utilization of the processing resource.

Step 103: and controlling the FIFOs at all levels to respectively process the message bodies in the message body set to be processed by utilizing the allocated processing resources.

In a specific implementation process, after the electronic device has allocated the processing resources required by each stage of the FIFO, each stage of the FIFO is controlled to process the message bodies in the set of message bodies to be processed by using the allocated processing resources, the read-write states of each message body in each stage of the FIFO have been defined in the configuration file in the front, and the message bodies in the set of message bodies to be processed can be processed according to the read-write states of the message bodies, so that the whole processing process of the whole FPGA on the message bodies to be processed is completed, thereby realizing the maximum utilization of resources on the basis of the FIFO, maintaining the architecture design of the original FPGA, flexibly adjusting the processing resources required by each stage of the FIFO by using the configuration file, and improving the configurability and maintainability.

On the basis of the above embodiment, the allocating required processing resources for each level of FIFO according to the read-write state and bit width corresponding to the message body in each level of FIFO includes:

respectively and dynamically adjusting the message bodies included in the message body set to be processed according to the read-write state corresponding to the message body in each level of FIFO to obtain a target message body set to be processed corresponding to each level of FIFO;

determining the total bit width of the target message body set to be processed corresponding to each level of FIFO according to the bit width corresponding to the message body included in the target message body set to be processed corresponding to each level of FIFO;

and allocating processing resources for the corresponding FIFO according to the total bit width of the target message body set to be processed corresponding to each stage of the FIFO.

In a specific embodiment, dynamic adjustment of the set of message bodies to be processed by each level of FIFO can be achieved through the read-write state corresponding to the message bodies in each level of FIFO, and a target set of message bodies to be processed corresponding to each level of FIFO is obtained. And determining the total bit width of each stage of FIFO according to the message body bit width included in the target message body set to be processed, so as to allocate corresponding processing resources to each stage of FIFO according to the total bit width, thereby realizing the full utilization of the resources.

On the basis of the above embodiment, the read-write state includes one of read-write, read-only, write-only, and transparent transmission, and the dynamically adjusting the message bodies included in the message body set to be processed according to the read-write state corresponding to the message bodies in each level of FIFO includes:

and removing the message body of which the read-write state is transparent transmission from the message body set to be processed in each stage of FIFO.

In a specific implementation process, the read-write state may include read-write, read-only, write-only, and transparent transmission, the read-write state of each message body in each level of FIFO may be predefined in the configuration file, for example, if the read-write state of the message body a in the FIFO1 is read-write, the FIFO1 needs to allocate corresponding read-write resources to the message body, and if the read-write state of the message body B in the FIFO1 is transparent transmission, the message body does not occupy the processing resources of the FIFO1, and the message body may be transmitted through a general address in the FPGA, so that the message body whose read-write state is transparent transmission in each level of FIFO needs to be removed from the set of message bodies to be processed, thereby saving processing resources. Each FIFO is equivalent to a message processing module in pipeline and comprises a read interface and a write interface, a user can acquire the message body from the read interface in the message processing module, then write the message body into the FIFO through the write interface, and merge the message bodies in the message processing module to generate a target message body set to be processed corresponding to the FIFO as a factor for processing resource allocation. It can be understood that, for some technical scenarios read by users, that is, in the process that an external device needs to read a message body from the electronic device, it is not the read process of the lower-level FIFO, but it is also necessary to map and output a complete set of message bodies to be processed.

Fig. 2 is a schematic diagram of a specific processing procedure of a single FIFO according to an embodiment of the present application. Specifically, the change process of the target message body set to be processed obtained after the message body set to be processed in each FIFO is dynamically adjusted is described, as can be seen from the figure, each FIFO may include a read interface FIFO (rd) and a write interface FIFO (wr), the message body contents in the read interface and the write interface may be respectively determined according to the read-write state of each message body in the message body set to be processed, the message bodies included in the read interface may be Field a and Field E, the message bodies included in the write interface may be Field a and Field C, and for Field B and Field D, no processing is required in the FIFO, that is, no processing resources need to be allocated. And for the transmission process of the message bodies included in the corresponding message body set in each FIFO on the address bus, the complete message body set is transmitted on the address bus of the FPGA.

Fig. 3 is a schematic diagram of a variation of a single FIFO message body according to an embodiment of the present application, and mainly explains a variation of a set of target message bodies to be processed in a single FIFO by a schematic diagram of introducing a specific message body variation through an example FIFO. As shown in fig. 3, the left half of the diagram shows the state before the processing of the message body set in the FIFO, and the state including 5 message bodies is shown in table 1 below, where table 1 is the state before the processing of the message body set in the FIFO.

TABLE 1 status of message body set before processing in FIFO

Name of message body	Read-write state
		Field A	wr/rd (read-write)
Field B	no used (transparent transmission)
		Field C	wr (write only)
Field D	no used (transparent transmission)
		Field E	rd (read only)

The right half of the figure shows the state after the processing of the message body set in the FIFO, and since the read-write state corresponding to Field B and Field D is transparent transmission, the FIFO removes the transparent transmission of the two message bodies to obtain a compact target message body set to be processed, and therefore the target message body set to be processed includes 3 message bodies, as described in table 2 below, table 2 is the state after the processing of the message body set in the FIFO, and corresponding processing resources can be allocated to the FIFO according to the processed target message body set to be processed.

TABLE 2 post-processing states of message body sets in FIFO

Name of message body	Read-write state
		Field A	wr/rd (read-write)
Field C	wr (write only)
		Field E	rd (read only)

On the basis of the above embodiment, the controlling each stage of FIFOs respectively uses allocated processing resources to process the message body in the message body set to be processed, including:

determining a survival interval corresponding to each message body, wherein the survival interval is each level of FIFO in cascade connection and comprises an interval starting point and an interval end point;

and taking the message body processed by the upper-level FIFO as the input of the lower-level FIFO according to the survival interval until the processing of the message body by the corresponding FIFO of each level in the survival interval is finished by utilizing the processing resources corresponding to the FIFO of each level.

In a specific implementation process, a living space corresponding to each message body may be determined according to a corresponding read-write processing state of each message body in each stage of FIFO in a configuration file, the living space may be a continuous FIFO having an operation authority for the message body, and includes an interval starting point and an interval ending point, the interval starting point may be a first FIFO performing a write operation on the message body, that is, a FIFO into which the message body is written, and the interval ending point may be a last FIFO performing a read operation on the message body. The processing of each stage of FIFO to each message body is determined according to the living space of each message body, for example, three FIFOs, namely FIFO1, FIFO2 and FIFO3, which are connected in cascade, in the FIFO2, when the message body is defined as read-write or read-only attribute, the whole message body to be processed can be compressed to obtain a target message body set to be processed for reading the message body. It should be noted that the message body read from the FIFO3 comes from the input of the FIFO2 or the input of other addresses, and the write message body can be or-operated by using empty signal of FIFO empty, so that the FIFO3 synchronizes the message bodies to be read to the timing of the last arrival, thereby realizing the message synchronization operation of the FIFO 3.

If a plurality of message bodies are defined as read-write or write-only states, the FIFO can reorganize the message bodies into a target message body set to be processed, corresponding processing resources are distributed, the target message body set is replaced into the reading of the lower-level FIFO after the processing is finished, and the processing operation of each-level FIFO is sequentially carried out until the processing of each-level FIFO on the message bodies is finished.

On the basis of the above embodiment, the acquiring a macro definition file generated in advance according to a configuration file includes:

acquiring a pre-compiled configuration file;

and translating the configuration file to generate a macro definition file which can be executed on an FPGA chip carried by the electronic equipment.

In a specific implementation process, a pre-written configuration file is obtained first, and the configuration file may use a Python writing mapping file as a configuration file at the top layer, so as to implement the configuration of the read-write state and bit width of each message body. And then translating the configuration file, wherein the translation mode can be that the code rule instantiated according to a verilog template is written into a specified file so as to obtain a macro definition file, and the writing work of the FPGA design file is simplified by not directly modifying the macro definition file.

On the basis of the above embodiment, the method further includes:

modifying the corresponding read-write state or bit width of the message body in each stage of FIFO in the configuration file; alternatively, the first and second electrodes may be,

and defining a new message body in the configuration file, and increasing the corresponding read-write state and bit width of the new message body in each stage of FIFO.

In a specific implementation process, in the pre-written configuration file, the read-write state or bit width corresponding to the message body included in the message body set to be processed in each stage of FIFO may also be modified, and then a translation tool is used to generate a macro definition file of system verilog attributes, so as to implement editable macro definition file. And a new message body can be inserted into the message body set to be processed by defining the new message body, and the read-write state and bit width can be configured by the configuration file, so that the flexible change of the configuration file is realized.

On the basis of the above embodiment, the method further includes:

defining a new FIFO and a corresponding cascade position in the configuration file, and defining the read-write state and bit width of each message body in the new FIFO.

In a specific implementation process, the cascade position may be a specific positional relationship of the new FIFO defined in the configuration file in each stage of the FIFOs cascade-connected in the FPGA, and the new FIFO may be defined to implement the configuration of the FIFOs, and may also adjust the cascade sequence of the original FIFOs to obtain an optimal configuration. And then, the read-write state and bit width of the message body are added into the new FIFO, so that the FIFO can process the message body, and the maintainability of the FPGA is improved.

Fig. 4 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present application, where the apparatus may be a module, a program segment, or code on an electronic device. It should be understood that the apparatus corresponds to the above-mentioned embodiment of the method of fig. 1, and can perform various steps related to the embodiment of the method of fig. 1, and the specific functions of the apparatus can be referred to the description above, and the detailed description is appropriately omitted here to avoid redundancy. An embodiment of the present application provides a message processing apparatus, including:

an obtaining module 401, configured to obtain a to-be-processed message body set and a macro definition file pre-generated according to a configuration file, where the to-be-processed message body set includes multiple message bodies, and the configuration file includes read-write states and bit widths corresponding to the message bodies in each level of FIFO;

an allocating module 402, configured to allocate required processing resources to each level of FIFO according to the read-write state and bit width corresponding to the message body in each level of FIFO;

and a control module 403, configured to control each level of FIFO to process the message body in the message body set to be processed by using the allocated processing resource.

On the basis of the foregoing embodiment, the allocating module 402 is specifically configured to:

On the basis of the above embodiment, the read-write state includes one of read-write, read-only, write-only, and transparent transmission.

On the basis of the foregoing embodiment, the control module 403 is specifically configured to:

On the basis of the foregoing embodiment, the apparatus further includes a message body configuration module, configured to:

On the basis of the above embodiment, the apparatus further includes a FIFO configuration module configured to:

Fig. 5 is a schematic structural diagram of an electronic device provided in an embodiment of the present application, and as shown in fig. 5, the electronic device includes: a processor (processor)501, a memory (memory)502, and a bus 503; wherein the content of the first and second substances,

the processor 501 and the memory 502 interact with each other through the bus 503;

the processor 501 is used to call program instructions in the memory 502 to execute the message processing method provided by the above-mentioned method embodiments.

The processor 501 may be an integrated circuit chip having signal processing capabilities. The Processor 501 may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. Which may implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The Memory 502 may include, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Read-Only Memory (EPROM), Electrically Erasable Read-Only Memory (EEPROM), and the like.

The present embodiment discloses a computer program product comprising a computer program stored on a computer-readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the message processing method provided by the above-mentioned method embodiments.

The present embodiment provides a computer-readable storage medium, which stores computer instructions that cause the computer to execute the message processing method provided by the above method embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or mutual connection may be an indirect coupling or mutual connection of devices or units through some mutual interfaces, and may be in an electric, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A message processing method is characterized in that the method is applied to electronic equipment carrying a Field Programmable Gate Array (FPGA), the FPGA comprises first-in first-out memories (FIFO) of all levels which are connected in cascade, and the method comprises the following steps:

acquiring a message body set to be processed and a macro definition file generated in advance according to a configuration file, wherein the message body set to be processed comprises a plurality of message bodies, and the configuration file comprises read-write states and bit widths corresponding to the message bodies in FIFO (first in first out) at all levels;

allocating required processing resources for each stage of FIFO according to the read-write state and bit width corresponding to the message body in each stage of FIFO;

and controlling the FIFOs at all levels to respectively process the message bodies in the message body set to be processed by utilizing the allocated processing resources.

2. The method according to claim 1, wherein said allocating required processing resources for each level of FIFO according to the read-write status and bit width corresponding to said message body in each level of FIFO comprises:

3. The method according to claim 2, wherein the read-write state includes one of read-write, read-only, write-only, and transparent transmission, and the dynamically adjusting the message bodies included in the set of message bodies to be processed according to the read-write state corresponding to the message bodies in each level of FIFO includes:

4. The method according to claim 1, wherein the controlling of the FIFOs respectively processes the message body in the set of message bodies to be processed by using the allocated processing resources comprises:

5. The method according to claim 1, wherein the obtaining the macro definition file generated in advance according to the configuration file comprises:

acquiring a pre-compiled configuration file;

6. The method according to any one of claims 1-5, further comprising:

7. The method according to any one of claims 1-5, further comprising:

8. A message processing apparatus, comprising:

the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a message body set to be processed and a macro definition file generated in advance according to a configuration file, the message body set to be processed comprises a plurality of message bodies, and the configuration file comprises read-write states and bit widths corresponding to the message bodies in FIFO (first in first out) at each level;

the distribution module is used for distributing required processing resources for each stage of FIFO according to the read-write state and bit width corresponding to the message body in each stage of FIFO;

and the control module is used for controlling each stage of FIFO to respectively utilize the allocated processing resources to process the message bodies in the message body set to be processed.

9. An electronic device, comprising: a processor, a memory, and a bus, wherein,

the processor and the memory are communicated with each other through the bus;

the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any one of claims 1-7.

10. A computer-readable storage medium storing computer instructions which, when executed by a computer, cause the computer to perform the method of any one of claims 1-7.