CN1722144A - 设计和制造lsi的***和方法以及电子束数据生成*** - Google Patents
设计和制造lsi的***和方法以及电子束数据生成*** Download PDFInfo
- Publication number
- CN1722144A CN1722144A CNA2005100848882A CN200510084888A CN1722144A CN 1722144 A CN1722144 A CN 1722144A CN A2005100848882 A CNA2005100848882 A CN A2005100848882A CN 200510084888 A CN200510084888 A CN 200510084888A CN 1722144 A CN1722144 A CN 1722144A
- Authority
- CN
- China
- Prior art keywords
- patterned layers
- lsi
- patterning
- layout data
- electron beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004210482 | 2004-07-16 | ||
JP2004210482A JP4464218B2 (ja) | 2004-07-16 | 2004-07-16 | Lsi設計システム、lsi設計方法、及びレイアウトデータ構造 |
JP2004-210482 | 2004-07-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1722144A true CN1722144A (zh) | 2006-01-18 |
CN1722144B CN1722144B (zh) | 2011-02-09 |
Family
ID=35600893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2005100848882A Expired - Fee Related CN1722144B (zh) | 2004-07-16 | 2005-07-18 | 设计和制造lsi的***和方法以及电子束数据生成*** |
Country Status (3)
Country | Link |
---|---|
US (1) | US7370304B2 (zh) |
JP (1) | JP4464218B2 (zh) |
CN (1) | CN1722144B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105426556A (zh) * | 2014-09-19 | 2016-03-23 | 北京华大九天软件有限公司 | 版图设计规则文件中图层关系的可视化分析方法 |
KR20170068311A (ko) * | 2015-12-09 | 2017-06-19 | 삼성전자주식회사 | 테스트 패턴, 반도체 소자의 테스트 방법, 및 집적 회로의 레이아웃 설계를 위한 컴퓨터 구현 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0791887B1 (en) * | 1996-02-21 | 2001-05-23 | Matsushita Electric Industrial Co., Ltd. | Flip-Chip layout input apparatus and method |
JP3185754B2 (ja) | 1998-05-29 | 2001-07-11 | 日本電気株式会社 | 露光原版の作製方法 |
JP3822009B2 (ja) * | 1999-11-17 | 2006-09-13 | 株式会社東芝 | 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体 |
JP2002368088A (ja) * | 2001-06-05 | 2002-12-20 | Fujitsu Ltd | ダミーパターン発生工程とlcr抽出工程とを有するlsi設計方法及びそれを行うコンピュータプログラム |
-
2004
- 2004-07-16 JP JP2004210482A patent/JP4464218B2/ja not_active Expired - Fee Related
-
2005
- 2005-07-15 US US11/181,925 patent/US7370304B2/en not_active Expired - Fee Related
- 2005-07-18 CN CN2005100848882A patent/CN1722144B/zh not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105426556A (zh) * | 2014-09-19 | 2016-03-23 | 北京华大九天软件有限公司 | 版图设计规则文件中图层关系的可视化分析方法 |
KR20170068311A (ko) * | 2015-12-09 | 2017-06-19 | 삼성전자주식회사 | 테스트 패턴, 반도체 소자의 테스트 방법, 및 집적 회로의 레이아웃 설계를 위한 컴퓨터 구현 방법 |
CN107039402A (zh) * | 2015-12-09 | 2017-08-11 | 三星电子株式会社 | 测试图案、测试方法以及计算机实现方法 |
CN107039402B (zh) * | 2015-12-09 | 2022-01-11 | 三星电子株式会社 | 测试图案、测试方法以及计算机实现方法 |
KR102532200B1 (ko) | 2015-12-09 | 2023-05-12 | 삼성전자 주식회사 | 테스트 패턴, 반도체 소자의 테스트 방법, 및 집적 회로의 레이아웃 설계를 위한 컴퓨터 구현 방법 |
Also Published As
Publication number | Publication date |
---|---|
JP4464218B2 (ja) | 2010-05-19 |
CN1722144B (zh) | 2011-02-09 |
JP2006031469A (ja) | 2006-02-02 |
US20060015837A1 (en) | 2006-01-19 |
US7370304B2 (en) | 2008-05-06 |
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Legal Events
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PB01 | Publication | ||
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ASS | Succession or assignment of patent right |
Owner name: HU NAN QIU ZEYOU PATENT STRATEGIC PLANNING CO., LT Free format text: FORMER OWNER: QIU ZEYOU Effective date: 20101029 |
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C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: 410005 28/F, SHUNTIANCHENG, NO.185, FURONG MIDDLE ROAD, CHANGSHA CITY, HU NAN PROVINCE TO: 410205 JUXING INDUSTRY BASE, NO.8, LUJING ROAD, CHANGSHA HIGH-TECH. DEVELOPMENT ZONE, YUELU DISTRICT, CHANGSHA CITY, HU NAN PROVINCE |
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TA01 | Transfer of patent application right |
Effective date of registration: 20101105 Address after: Kanagawa, Japan Applicant after: Renesas Electronics Corporation Address before: Kanagawa, Japan Applicant before: NEC Corp. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110209 Termination date: 20140718 |
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EXPY | Termination of patent right or utility model |