CN1677627A - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

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CN1677627A
CN1677627A CN200510062526.3A CN200510062526A CN1677627A CN 1677627 A CN1677627 A CN 1677627A CN 200510062526 A CN200510062526 A CN 200510062526A CN 1677627 A CN1677627 A CN 1677627A
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松田友子
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Renesas Electronics Corp
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Abstract

提供一种能够抑制NiSi层转变为二硅化物的制造半导体器件的方法。在P－MOS晶体管和N－MOS晶体管二者中的栅极电极和源极/漏极区上形成NiSi层，硅化物层形成步骤。在包括NiSi层的整个区域上形成直接氮化物层，氮化物层形成步骤。然后将能够增加NiSi层的耐热温度的元素注入到NiSi层中，元素注入步骤。结果，能够增加NiSi层的耐热特性，并且由此能够抑制NiSi层转变为二硅化物。

Description

制造半导体器件的方法
本申请基于日本专利申请2004-104041，其内容在此作为参考引进。
技术领域
本发明涉及制造半导体器件的方法。
背景技术
在例如日本未决专利申请1993-90293中描述了制造半导体器件的常规方法。在该文件中公开的制造方法包括在MOS晶体管的栅极电极和源极/漏极电极上形成NiSi制成的单硅化物层，用来降低芯片的寄生电阻。
发明内容
但是，现在已经发现在采用上述制造方法的情况下，由于后续工艺中的热处理，NiSi层可以转变为二硅化物。一旦NiSi层转变为二硅化物，MOS晶体管的寄生电阻易于增加。
考虑到前述问题，以如下目的构思了本发明，即增加半导体器件中形成的NiSi层的耐热特性并抑制NiSi层被转变成二硅化物，以由此提高半导体器件的性能。
根据本发明，提供具有MOS晶体管的制造半导体器件的方法，包括：硅化物层形成步骤，在MOS晶体管的栅极电极和源极/漏极区中的至少一个上形成NiSi层；以及元素注入步骤，将抑制NiSi层转变为二硅化物的抑制元素注入到NiSi层中。
在该制造方法中，在元素注入工艺中，抑制NiSi层转变为二硅化物的抑制元素被引入到NiSi层中。结果，增加了NiSi层的耐热特性，并且因而抑制了NiSi层被后续工艺中的热处理转变为二硅化物。
根据本发明，建立了能够抑制NiSi层转变为二硅化物的制造半导体器件的方法。
附图说明
从结合附图的下面的描述中，本发明的上述和其它目的、优点和特征将更加明显，其中：
图1是用于说明根据本发明实施例的制造半导体器件的方法的示意性剖面图；
图2是用于说明根据本发明实施例的制造半导体器件的方法的示意性剖面图；
图3是用于说明根据本发明实施例的制造半导体器件的方法的示意性剖面图；
图4是用于说明根据本发明实施例的制造半导体器件的方法的示意性剖面图；
图5是用于说明根据本发明实施例的制造半导体器件的方法的示意性剖面图；
图6是用于说明根据本发明实施例的制造半导体器件的方法的示意性剖面图；以及
图7是用于说明根据本发明实施例的制造半导体器件的方法有利效果的线形图。
具体实施方式
现在将参考说明性实施例在此描述本发明。本领域技术人员将认识到使用本发明的讲解可以完成多个可变换的实施例并且本发明并不局限于用于说明性目的所示的实施例。
制造半导体器件的方法可以包括如下步骤：氮化物层形成步骤，在NiSi层上形成直接氮化物层；以及元素注入步骤可以包括通过直接氮化物层注入元素，使得元素到达NiSi层。该方法除了抑制NiSi层转变为二硅化物之外，还能够缓和直接氮化物层中的应力。
在本发明中，半导体器件可以具有P-MOS晶体管和N-MOS晶体管，并且直接氮化物层可以具有张应力。这里，在元素注入工艺中，元素可以仅被注入到P-MOS晶体管和N-MOS晶体管中形成的NiSi层中的在P-MOS晶体管上形成的NiSi层上。在直接氮化物层具有张应力的情况下，P-MOS晶体管的驱动电流降低，而N-MOS晶体管的驱动电流增加。因此，在元素注入工艺中仅在P-MOS晶体管的区域中进行元素注入能够缓和张应力，并且由此抑制了P-MOS晶体管中的驱动电流的降低。
在本发明中，半导体器件可以具有P-MOS晶体管和N-MOS晶体管，并且直接氮化物层可以具有压缩应力。这里，在元素注入工艺中，元素可以仅被注入到P-MOS晶体管和N-MOS晶体管中形成的NiSi层中的在N-MOS晶体管上形成的NiSi层上。在直接氮化物层具压缩应力的情况下，N-MOS晶体管的驱动电流降低，而P-MOS晶体管的驱动电流增加。因此，在元素注入工艺中仅在N-MOS晶体管的区域中进行元素注入能够缓和压缩应力，并且由此抑制了N-MOS晶体管中的驱动电流的降低。
NiSi层可以由NiSi制成。由于NiSi具有低阻，所以NiSi可以适合地作为硅化物层。
要注入的元素可以为从Ge、N、F、O和C组成的组中选出的至少一种。这些元素具有通过增加NiSi层的耐热温度来抑制转变为二硅化物和通过增加NiSi层的耐热温度来缓和直接氮化物层的应力的作用。
下文中，将参考附图，详细说明根据本发明的制造半导体器件的方法的优选实施例。这里，在所有附图中相同的组成部分被给予相同的标号，并且省略其重复的说明。
参考图1到6，将说明根据本发明制造半导体器件的方法的实施例。在该实施例中要制造的半导体器件是具有P-MOS晶体管和N-MOS晶体管的CMOS晶体管器件。
首先，如图1所示，在硅衬底上形成P-MOS晶体管10和N-MOS晶体管20。P-MOS晶体管10包括栅极电极12、栅极氧化层13、源极/漏极区14、LDD(轻掺杂漏极)区16和隔离物18。同样地，N-MOS晶体管20包括栅极电极22、栅极氧化层23、源极/漏极区24、LDD区26和隔离物28。P-MOS晶体管10和N-MOS晶体管20通过作为隔离区的STI(浅沟道隔离)区30彼此隔离。
然后如图2所示，在P-MOS晶体管10和N-MOS晶体管20二者中的栅极电极12、22和源极/漏极区14、24上形成作为单硅化物层的NiSi层42(硅化物层形成步骤)。这里，NiSi层42可以仅形成在栅极电极12、22和源极/漏极区14、24中的任何一个上。
然后，如图3所示，在包括NiSi层42的整个区域上形成作为层间氮化物膜的直接氮化物层44(氮化物层形成步骤)。直接氮化物层44意欲和随后所述的层间氧化物膜46一起构成层间介质膜。此外，在本实施例中，直接氮化物层44具有张应力。例如，直接氮化物层44可以由SiN制成。
然后，如图4所示，用光致抗蚀剂在整个N-MOS晶体管20上形成掩模M。
参考图5，可以增加NiSi层42的耐热温度的元素(下文中称作“抑制元素”)被注入到NiSi层42中(元素注入步骤)。在该阶段，由于N-MOS晶体管20的区域用掩模M覆盖，所以抑制元素仅被注入到P-MOS晶体管10的区域中。注入条件被设置为使得抑制元素到达NiSi层42。抑制元素的例子包括Ge、N、F、O和C。这些元素可以增加NiSi层42的耐热温度，从而抑制NiSi层42转变为二硅化物，并且还缓和直接氮化物层的应力。这里，可以注入抑制元素中仅仅一种，同时也可以组合地注入多种抑制元素。
最后，如图6所示，在直接氮化物层44上形成层间氧化物膜46。例如，可以采用SiO2作为层间氧化物膜46。
现在，将描述根据前述实施例的制造半导体器件的方法的有利效果。
在制造半导体器件的上述方法中，在元素注入工艺中，抑制元素被注入到NiSi层42中。由此，NiSi层42的耐热特性增加，从而能够抑制NiSi层42由于在后续工艺中的热处理而转变为二硅化物。由于NiSi2具有比NiSi更高的表面电阻，所以为了降低芯片的寄生电阻而抑制NiSi转变为二硅化物是十分重要的。此外，尽管NiSi转变为二硅化物导致漏电流的增加，所提出的制造方法也能够抑制这种漏电流的增加。
此外，在NiSi层42形成之后，通过注入步骤进行抑制元素到NiSi层42的引入。此后，易于独立地控制向P-MOS晶体管10的注入量以及向N-MOS晶体管20的注入量。例如，在该实施例中，由于采用掩模M，所以在P-MOS晶体管10和N-MOS晶体管20中形成的NiSi层42之中，能够十分容易地进行仅在形成在P-MOS晶体管10中的NiSi层42上的注入。
同时，为了将抑制元素引入到NiSi层中，抑制元素可以混和在用于淀积Ni层的溅射气体中。但是，由于不能够独立地控制在P-MOS晶体管10的区域中的NiSi层42和在N-MOS晶体管20的区域中的NiSi层42的注入量，该方法不理想。例如，在例如As被作为杂质引入到N-MOS晶体管20中的情况下，由于As还用来增加NiSi层的耐热温度，所以在P-MOS晶体管10和在N-MOS晶体管20二者中通过溅射引入相同量的抑制元素，导致了增加N-MOS晶体管20的区域中NiSi层的耐热温度的引入元素的量比增加P-MOS晶体管10的区域中NiSi层的耐热温度的引入元素的量大。因而，当形成NiSi层时，难于设置P-MOS晶体管10和N-MOS晶体管20之间的完全等效的反应温度。
另一方面，由于在形成NiSi层42的步骤时还没有引入抑制元素，所以根据该实施例的方法，也就是说，在NiSi层42的形成之后执行抑制元素注入能够防止上述问题。
此外，在元素注入步骤中，注入条件设置为使得抑制元素到达NiSi层42。这里，考虑到由于对栅极氧化层的冲击或注入可能损坏衬底，所以理想的是抑制元素不被注入到衬底和栅极氧化层。在这个方面中，由于注入的物质易于停留在金属中，所以易于确定注入条件使得抑制元素停留在NiSi层42中。
特别在该实施例中，抑制元素通过直接氮化物层44注入。这不仅提供了抑制NiSi层42转变为二硅化物的优点，而且提供了缓和直接氮化物层44中的应力的优点。
此外，仅在P-MOS晶体管10中形成的NiSi层42上进行抑制元素的注入。由于直接氮化物层44具有张应力，所以直接氮化物层44增加了N-MOS晶体管的驱动电流，而降低P-MOS晶体管的驱动电流。因此，仅在P-MOS晶体管10的区域中执行元素注入能够抑制P-MOS晶体管10的驱动电流的降低。
此外，尽管该实施例描述了采用具有张应力的直接氮化物层并且仅在P-MOS晶体管10的区域中注入抑制元素的情况，在这种情况中，抑制元素仅被注入到N-MOS晶体管20的区域中，也可以采用具有压缩应力的直接氮化物层。
此外，在该实施例中，形成层间介质膜，该层间介质膜具有形成为直接氮化物层44和层间氧化膜46的结构。该结构的优点是在通过蚀刻剥离层间介质膜以形成接触等时，直接氧化物层44可以作为蚀刻停止物。但是，不是必需提供直接氮化物层44。在不提供直接氮化物层44的情况下，也就是，当跳过形成氮化物层的步骤时，在硅化物层形成步骤之后可以立即执行元素注入步骤。在这种情况下，可以在P-MOS晶体管10和N-MOS晶体管20的两个区域中，或者仅在这两个区域之一中，注入抑制元素。
图7是在NiSi层中已经注入抑制元素和没有注入抑制元素的各情况下，以NiSi层的温度界限的形式示出了耐热温度的变化的线形图。通过直接氮化物层进行抑制元素的注入。在此所说的温度界限是指NiSi层转变为二硅化物，也就是NiSi2层的温度。图的纵轴表示表面电阻值(Ω/□)，横轴表示温度(摄氏度)。基于当转变为二硅化物时镍的表面电阻值增加的事实，从图中明显看出当注入抑制元素时，温度界限上升到500摄氏度之上，而在不执行注入的情况下，温度界限是大约450摄氏度。因此，注入抑制元素能够增加NiSi层的耐热温度，并由此抑制了NiSi层转变为二硅化物。
很明显本发明并不限于上述实施例，而是在不偏离本发明的范围和精神下可以修改和变化。

Claims (5)

1.一种制造具有MOS晶体管的半导体器件的方法，包括：
硅化物层形成步骤，在所述MOS晶体管的栅极电极和源极/漏极区中的至少一个上形成NiSi层；以及
元素注入步骤，将抑制所述NiSi层转变为二硅化物的抑制元素注入到所述NiSi层中。
2.根据权利要求1的方法，进一步包括：
氮化物层形成步骤，在所述NiSi层上形成层间氮化物膜，
其中所述元素注入步骤包括通过所述层间氮化物膜注入所述元素，使得所述元素到达所述NiSi层。
3.根据权利要求2的方法，所述半导体器件具有P-MOS晶体管和N-MOS晶体管，并且所述层间氮化物膜具有张应力，
其中所述元素注入步骤包括在所述P-MOS晶体管和所述N-MOS晶体管上形成的所述NiSi层中，仅在所述P-MOS晶体管上形成的所述NiSi层上注入所述元素。
4.根据权利要求2的方法，所述半导体器件具有P-MOS晶体管和N-MOS晶体管，并且所述层间氮化物膜具有压缩应力，
其中所述元素注入步骤包括在所述P-MOS晶体管和所述N-MOS晶体管上形成的所述NiSi层中，仅在所述N-MOS晶体管上形成的所述NiSi层上注入所述元素。
5.根据权利要求1的方法，其中所述抑制元素注入步骤包括注入从Ge、N、F、O和C组成的组中选出的至少一种元素。
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