CN1649088A - 半导体器件的形成方法和*** - Google Patents
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Abstract
本发明的第一方面是形成半导体器件的方法。所述方法包括:在衬底[415]中形成三维(3D)图案[405];以及按照半导体器件的所需特性在衬底[415]上淀积至少一种材料[410]。
Description
技术领域
本发明一般涉及半导体器件领域,更具体地说,涉及半导体器件的形成方法和***。
背景技术
在半导体加工行业,目前的主要发展方向是缩小现有结构并制造更小的结构。所述过程通常称为微加工。微加工具有重大影响的领域是微电子领域。具体地说,缩小的微电子结构通常可使该结构的价格更为低廉、具有更高的性能、能降低功耗、并在给定尺寸中含有更多的元件。虽然微加工在电子工业中已有广泛应用,它也可适用于其它应用,例如生物工艺学、光学、机械***、传感器件以及反应堆。
通常制造电子器件需要数次淀积和蚀刻步骤,这些步骤必需相互对准,对准的精度接近甚至超过器件的最小特征尺寸。目前是利用光刻技术将电子器件制造在平整的、刚性的、且不变形的衬底上,例如晶体硅或玻璃上。但生产这些器件的一种便宜得多的装置却基于压印平版印刷术(imprint lithography)。
压印平版印刷术通常是利用具有待制造的结构特征的母板和待形成图案的衬底材料之间的接触以高分辨率使衬底材料上的薄膜形成图案。具有图案的薄膜可以是介质、半导体、金属或有机物,并且可以以薄膜或单独的层的形式来形成图案。压印平版印刷术在卷装进出加工中特别有用,因为产量较高并能处理较宽的衬底。
在传统的光刻技术中,使用光学对准标记来保证逐次图案形成步骤之间的对准。虽然在卷装进出加工中也可使用光学对准标记,但这却是不实用的,原因有好几个。第一,由于基本的压印平版印刷过程不是光学性的,故增加了复杂性。其次,在卷装进出情况下衬底缺少平面性,由于场深度限制以及其它光学像差而导致光学对准精度方面的困难。最后,在卷装进出加工中使用的柔性衬底会因温度、湿度或机械应力的变化而发生尺寸改变。一个图案层相对于下一个图案层的这些变形和/或扩张会使大面积的精确对准根本不可能。
于是,需要一种能克服卷装进出制造过程中上述问题的器件制造方法和***。所述方法和***应简单,价廉并能容易地适应现有工艺。本发明解决了这些需求。
发明内容
本发明的一个方面是形成半导体器件的方法。所述方法包括在衬底上形成三维(3D)图案并按照半导体器件的所需特性在衬底上至少淀积一种材料。
本发明的其它方面和优点通过以下结合附图所作的详细说明就可一目了然,附图以实例的方式示明了本发明的原理。
附图说明
图1是按照本发明实施例的方法的高级流程图。
图2是按照本发明的实施例将三维图案形成到衬底中的过程流程图。
图3示出按照本发明另一实施例的配置。
图4示出按照本发明实施例的结构的侧视图。
图5示出用于按照本发明实施例形成三维图案的过程的流程图。
图5(a)-5(e)示出图5过程所得结构的侧视图。
图6是按照本发明实施例的交叉点阵列配置的图解说明。
图7说明用于按照本发明实施例形成交叉点阵列的过程。
图8示出按照本发明实施例的其中形成有三维图案的衬底。
图9和图10示出按照本发明实施例在执行图7的过程期间所得结构的X-X’和Y-Y’的截面图。
图11示出按照本发明实施例的示范交叉点结构。
具体实施方式
本发明涉及半导体器件的形成方法和***。现提出以下说明,以使本专业的技术人员能够利用本发明,并且此说明是在专利申请及其要求的范围内作出的。对于本专业的技术人员而言,对本发明所说明的实施例、一般原理以及特征的各种修改是显而易见的。因此,本发明不应限于所示实施例,而应包括与本文说明的原理和特征相一致的最广泛的范围。
如图所示,现公开半导体器件的形成方法和***。所述方法和***的各种实施例允许在任何加工步骤之前在器件衬底的三维结构中创建二维对准特征。随后的加工步骤,包括材料淀积、平面化和各向异性蚀刻等用来构建多层对准图案。所以,使用所述方法和***有可能增加半导体制造过程的灵活性。
虽然所公开的实施例是以用来形成半导体器件的形式加以说明的,但是,本专业的技术人员很容易地认识到,本发明同样可以用于其它类型的器件,例如机械、光学、生物学等器件。
图1是形成半导体器件的方法的高级流程图。第一步110包括在衬底中形成三维(3D)图案。在实施例中,所述衬底是适用于卷装进出加工的柔性衬底。最后步骤120包括按照半导体器件的所需特性在衬底上淀积至少一种材料。因此,尽管在直接压印过程中,特征的纵横比受到压印工具的材料特性的限制,但建议的在衬底中形成3维图案的过程缓解了对三维图案的纵横比的限制。所述建议的方法在形成交叉点存储器阵列方面特别有用。
在实施例中,步骤110通过将3D图案转移到衬底中来完成。图2是将3D图案转移到衬底中的过程的流程图。第一步210包括在衬底上淀积一层材料。在实施例中,所述材料层是聚合物材料,例如Norland光学粘接剂系列聚合物中的一种。在另一实施例中,所述层材料是光致抗蚀剂材料。第二步202包括将三维图案压印到所述层材料中。最后一步203包括将三维图案转移到衬底中。
在一个实施例中,步骤202是利用含有三维图案的压印工具来完成的。相应地,使压印工具与材料层接触,从而将三维图案压印到材料层中。利用压印工具在材料层中产生三维图案的方法在题目为”A Method and System for Forming a Semiconductor Device”的专利申请10/184,587中已有说明,所述专利已作为参考包括在本文内。
或者,可以通过模制过程在衬底中形成三维图案。图3示出按照本发明另一实施例的配置。所述配置包括模制滚筒310,所述模制滚筒包括医用刀片320和释放滚筒340。相应地,将聚酰亚胺母液化合物330注入模制滚筒310中,加热固化并从模制滚筒310释放到释放滚筒340上。
图4示出按照本发明的实施例的结构侧视图。如图4所示,材料层410包括三维图案405并与衬底和415相接触。衬底415可以是聚酰亚胺塑料片,塑料衬底上可以有或没有无机涂层。最好衬底415能够耐受至少160℃的温度。
将三维图案压印到材料层上以后,就利用一系列变薄和衬底蚀刻步骤将三维图案转移到衬底上。图5是将三维图案形成到衬底中的过程流程图。第一步501包括蚀刻材料层的一部分,以暴露出衬底的第一部分。图5(a)示出材料层410和衬底415的第一暴露部分420的侧视图。
第二步502包括选择性地蚀刻衬底的暴露部分。此时,衬底的蚀刻特性为:衬底的去除速率比聚合物层要快些。图5(b)示出衬底415在选择性蚀刻后的结构。
第三步503涉及去除另一部分材料,从而暴露出衬底的第二部分。图5(c)示出衬底415的第二暴露部分。
第四步504涉及选择性地蚀刻衬底的暴露部分。这一步的完成也是因为衬底的蚀刻特性为:衬底的去除速率比材料层要快些。图5(d)示出衬底415在再次选择性蚀刻后的结构。图5(d)中也可见材料层410的剩余部分。
最后步骤505包括去除材料层的剩余部分。图5(e)示出去除材料层剩余部分后的衬底415。
将三维图案转移到衬底中之后,具有图案的衬底就可形成各种半导体器件。相应地,具有图案的衬底在形成交叉点存储器阵列中特别有用。
交叉点阵列
最好,交叉点存储器阵列包括两层正交间隔平行导体组,半导体层设置在所述两层正交间隔平行导体组之间。两组导体形成行电极和列电极,所述行电极和列电极以这样的方式重叠,即,每个行电极精确地在一个地方与每个列电极交叉。
为了更好地理解交叉点阵列,请参阅图6。图6示出交叉点阵列配置600。在每个相交点,行电极610和列电极620之间通过半导体层630连接,半导体层630起到二极管和串联熔丝的作用。阵列中的二极管均定向为:如果将共用电位加在所有行电极和列电极之间,则所有二极管均向同一方向偏置。熔丝元件可以作为单独的元件实现,当临界电流通过时它就开路,或者它可以包括在二极管的性能之中。
本专业的技术人员很容易理解上述交叉点阵列可以用来形成各种半导体器件,包括但不限于晶体管、电阻器、电容器、二极管、熔丝、逆熔丝(anti-fuse)等。
图7示出按照本发明实施例形成交叉点阵列的工艺过程。为了说明,图8示出包括形成在其中的三维图案的衬底715。图9-10示出在实现图7的工艺过程时所得结构的X-X’和Y-Y’的截面图。
第一步701涉及在具有图案的衬底上淀积第一金属层。图7(a)示出包括在具有图案的衬底715上的第一金属层720的结构。在一个实施例中,第一金属层720是一层或多层金属、有机物、介质或半导体。如果淀积具有强的方向性,则具有图案的衬底715需要有锥度的侧壁轮廓,以便使金属层720有好的阶梯式覆盖。
第二步702涉及将第一平面化聚合物加到第一金属层上。图7(b)示出与第一金属层720相接触的第一平面化聚合物730。平面化聚合物的实例为光致抗蚀剂、紫外光(uv)-可固化聚合物以及旋涂玻璃(spin-on glass)。
第三步703包括去除第一平面化聚合物的一部分。图7(c)示出包括平面化聚合物730’剩余部分的结构。在一个实施例中,通过反应离子蚀刻(RIE)过程来去除第一平面化聚合物,相对于第一金属层来选择所述蚀刻过程。
在RIE中,将衬底放入反应器中,将数种气体引入反应器。利用RF功率源在气体混合物中触发等离子体,将气体分子***为离子。离子被朝向待蚀刻的材料表面加速并在所述表面发生反应,形成另一种气态材料。这就是众所周知的反应离子蚀刻的化学部分。还有物理部分,其性质类似于溅射淀积过程。
如果离子具有足够高的能量,它们没有化学反应就可从蚀刻材料中轰击出原子。要研发能平衡化学和物理蚀刻的干法蚀刻工艺是个非常复杂的任务,因为有许多参数需要调节。改变平衡就可能影响蚀刻的各向异性,因为化学部分是各向同性的,而物理部分是高度各向异性的。相应地,RIE能够进行非常有方向性的蚀刻。
第四步704包括利用第一平面化聚合物作为蚀刻掩模来蚀刻部分第一金属层。图7(d)示出去除部分第一金属层后的结构。如图所示,剩余部分的第一平面化聚合物730’和剩余部分的第一金属层720’都一起留了下来。在一个实施例中,所述蚀刻步骤可选择性地去除第一金属层而不去除第一平面化聚合物或衬底。
第五步705包括选择性地蚀刻衬底。图7(e)示出选择性地蚀刻衬底715后的结构。所述蚀刻步步骤也是选择性的,即剩余部分的第一平面化聚合物730’和剩余部分的第一金属层720’都留在衬底715上。
第六步706包括去除剩余部分的第一平面化聚合物。图7(f)示出去除剩余部分的第一平面化聚合物后的结构。如图所示,只有剩余部分的第一金属层720’留在衬底715上。
所述工艺过程继续进行到图8。下一步707涉及在剩余部分的第一金属层720’上淀积第二金属。图7(g)示出在剩余部分的第一金属层720’上淀积第二金属层740后的结构。和第一金属层类似,第二金属层740是一层或多层金属、有机物、介质或半导体。
下一步708包括将第二平面化聚合物加到第二金属层上。图7(h)示出淀积第二平面化聚合物750后的结构。所述聚合物可以和第一平面化聚合物是同一类型,或者也可使用不同的聚合物。
下一步709包括去除部分第二平面化聚合物,从而暴露出部分第二金属层。图7(i)示出包括剩余部分的第二平面化聚合物750’和暴露部分的第二金属层740’的结构。在一个实施例中,第二平面化聚合物利用反应离子蚀刻(RIE)工艺去除,相对于第二金属层来选择所述蚀刻工艺。
下一步710包括利用第二平面化聚合物作为蚀刻掩模来蚀刻部分第二金属层。图7(j)示出去除部分第二金属层后的结构。如图所示,剩余部分的第二平面化聚合物750’和剩余部分的第二金属层740’都留了下来。在一个实施例中,所述蚀刻步骤可选择性地去除第二金属层而不去除第二平面化聚合物或衬底。
最后一步711包括去除剩余部分的第二平面化聚合物。图7(k)示出去除剩余部分第二平面化聚合物后的结构。交叉点存储器阵列也包括两层正交间隔平行导体组,半导体层设置在所述两层正交间隔平行导体组之间。两组导体形成行电极和列电极,所述行电极和列电极以这样的方式重叠,即,每个行电极精确地在一个地方与每个列电极交叉。
在示范实施例中,第一金属层包括金属薄膜、本征硅层和掺杂硅。第二金属层包括本征a-硅层、掺杂硅和金属薄膜。图11示出示范的交叉点结构1100。结构1100包括衬底1110上的第一金属层1120和第二金属层1130。第一金属层1120包括金属薄膜1121、本征硅层1122和掺杂硅1123。第二金属层1130包括本征a-硅层1131、掺杂硅1132和第二金属薄膜1133。所以,交叉点1100是与a-硅二极管结合的逆熔丝存储器开关。
以上公开了半导体器件的形成方法和***。所述方法和***的各种实施例允许在任何加工步骤之前在器件衬底的三维结构中创建二维对准特征。随后的加工步骤,包括材料淀积、平面化和各向异性蚀刻等用来构建多层对准图案。所以,使用所述方法和***有可能增加半导体制造过程的灵活性。
虽然已根据所示实施例对本发明作了说明,但本专业的技术人员应很容易理解对这些实施例可以作改动,而这些改动都还在本发明的精神和范围之内。所以本专业的技术人员可以作许多改动而不背离所附权利要求书的精神和范围。
Claims (10)
1.一种形成半导体器件的方法,所述方法包括:
在衬底[415]中形成三维(3D)图案[405];以及
按照所述半导体器件的所需特性在所述衬底[415]上淀积至少一种材料[410]。
2.如权利要求1所述的方法,其中形成所述三维(3D)图案[405]的步骤还包括:
在所述衬底[415]上淀积材料层[410];
将所述三维图案[405]压印到所述材料层[410]中;以及
将所述三维图案[405]转移到所述衬底[415]中。
3.如权利要求1所述的方法,其中所述半导体器件包括交叉点存储器阵列[600]。
4.如权利要求2所述的方法,其中所述半导体器件是以下器件中的至少一种:晶体管、电阻器、电容器、二极管、熔丝和逆熔丝。
5.如权利要求2所述的方法,其中将所述三维图案[405]压印到所述材料层[410]中的步骤还包括利用三维压印工具来创建所述三维图案[405]。
6.一种用于形成半导体器件的***,它包括:
用于在衬底[415]上形成图案[405]的装置,其中所述图案[405]是三维的;以及
用于按照所述半导体器件的所需特性在所述衬底[415]上淀积至少一种半导体材料[410]的装置。
7.如权利要求6所述的***,其中所述半导体器件包括交叉点存储器阵列[600]。
8.如权利要求6所述的***,其中用于形成所述图案[405]的所述装置还包括:
用于在所述衬底[415]上淀积材料层[410]的装置;
用于将三维图案[405]压印到所述材料层[410]中的装置;以及
用于将所述三维图案[405]转移到所述衬底[415]中的装置。
9.如权利要求7所述的***,其中用于在所述衬底[415]上淀积至少一种半导体材料[410]的所述装置还包括:
用于淀积两组导体以及所述两组导体之间的半导体层[630]的装置,所述两组导体形成行电极和列电极[610]、[620],所述行电极和列电极以这样的方式重叠,即,每个所述行电极[610]精确地在一个地方与每个所述列电极[620]交叉。
10.如权利要求7所述的***,其中所述半导体器件是以下器件中的至少一种:晶体管、电阻器、电容器、二极管、熔丝和逆熔丝。
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US8049110B2 (en) * | 2008-10-01 | 2011-11-01 | Hewlett-Packard Development Company, L.P. | Microelectronic device |
US9034233B2 (en) | 2010-11-30 | 2015-05-19 | Infineon Technologies Ag | Method of processing a substrate |
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US5772905A (en) * | 1995-11-15 | 1998-06-30 | Regents Of The University Of Minnesota | Nanoimprint lithography |
US6309580B1 (en) * | 1995-11-15 | 2001-10-30 | Regents Of The University Of Minnesota | Release surfaces, particularly for use in nanoimprint lithography |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
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US6552409B2 (en) | 2001-06-05 | 2003-04-22 | Hewlett-Packard Development Company, Lp | Techniques for addressing cross-point diode memory arrays |
US6580144B2 (en) | 2001-09-28 | 2003-06-17 | Hewlett-Packard Development Company, L.P. | One time programmable fuse/anti-fuse combination based memory cell |
US6743368B2 (en) | 2002-01-31 | 2004-06-01 | Hewlett-Packard Development Company, L.P. | Nano-size imprinting stamp using spacer technique |
US7037639B2 (en) * | 2002-05-01 | 2006-05-02 | Molecular Imprints, Inc. | Methods of manufacturing a lithography template |
US6861365B2 (en) | 2002-06-28 | 2005-03-01 | Hewlett-Packard Development Company, L.P. | Method and system for forming a semiconductor device |
US6900881B2 (en) * | 2002-07-11 | 2005-05-31 | Molecular Imprints, Inc. | Step and repeat imprint lithography systems |
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