CN1630038A - 蚀刻液及应用该蚀刻液选择性去除阻障层的导电凸块制造方法 - Google Patents
蚀刻液及应用该蚀刻液选择性去除阻障层的导电凸块制造方法 Download PDFInfo
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
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Abstract
一种具有选择性去除阻障层的导电凸块蚀刻液,包括下列步骤:提供一已制备完成集成电路组件的半导体基底,其上具有一金属层(metal layer)或凸垫(bonding pad)。形成一护层(passivation)于该半导体基底上,并使已形成的该金属层或凸垫表面部分曝露出来。形成一阻障层(barrier layer)于该护层及部分曝露的金属层或凸垫表面。形成一凸块底导层(conductive under bump metallurgy layer)于该阻障层上。于该凸块底导层上以涂布曝光的方式定义凸块的图案以形成一孔洞(hole);再形成一导电凸块层填入该孔洞,并去除残留的涂布物。蚀刻该凸块底导层,再以特定组成的蚀刻液去除该阻障层。以热制程将导电凸块溶化回流而形成一球形导电凸块。
Description
技术领域
本发明是关于一种半导体焊接凸块(solder bump)制程的蚀刻配方,是利用特定组成的蚀刻液来避免裸露的电路结构于蚀刻时受到伤害。
背景技术
在半导体制程中,当晶圆上的各种组件和内联机完成后,会于最上层形成连接垫(bonding pad)及保护层,该保护层是用来防止半导体组件和内联机遭受污染、刮伤与湿气的影响。后续则会利用微影与蚀刻制程,于保护层上定义形成一开口,以使设置于保护层底部的连接垫(bonding pad)曝露出来,使组件透过内联机、焊垫、以及焊垫上的焊接凸块(solder bump)而与外界电路板形成电连接。而目前电连接的方式,则大多采用覆晶(flip chip)技术。
广义的覆晶技术泛指将芯片翻转后,以面朝下的方式透过一金属导体与外界电路板进行电接合。一般而言,金属导体包含有金属凸块(metal bump)、卷带接合(tape-automated bonding)、非等向性导电胶(anisotropicconductive adhesives)、高分子凸块(polymer bump)、打线成球(stud bump)等等,这其中以金属凸块技术最为成熟,亦被广泛应用于量产的产品上。金属凸块的成型方法很多,常见者有蒸镀、溅镀、电镀、印刷、打线成型、喷射成型等,而金属凸块的材料则依不同的需求,有高温锡铅(SnPb)、低温锡铅、金、镍、铜等覆晶植球(solder balls)。
请参考图1A至图1F,其显示习知凸块(bumping)的制作方法的示意图。如图1A所示,提供一半导体基底10,其包含有制备完成的集成电路组件(在此未显示),一铝垫(bonding pad)12及金属凸垫(bumping pad)11是设置于该半导体基底10表面上。之后,请参考图1B,以一保护层(passivation)14是覆盖住该半导体基底10表面的所有集成电路组件,以及一第一开口16是定义形成于保护层14上,以使该金属凸垫11的表面部分曝露出来。其次,如图1C所示,于半导体基底10表面上依序形成一阻障层(barrier layer)18以及一金属层20。接着,如图1D所示,于半导体基底10表面上形成一厚膜光阻层22,其包含有一第二开口24是以涂布微影方式用来定义金属凸块位置的图案。
然后,如图1E所示,于第二开口24内电镀一金属凸块26以形成一导电金属凸块。之后,如图1F所示,再将厚膜光阻层22剥除之后,依序将金属凸块26区域以外的金属层20与阻障层18以蚀刻法去除,直到曝露出保护层14为止。最后,再加热金属凸块26使其形成球形金属凸块。
然而,于实际制程经验上,在制作金属凸块过程中面临蚀刻阻障层的步骤时,如图1F所示,其蚀刻液往往会对阻障层造成侧蚀(side etch)28,且亦有可能对裸露的电路结构如铝垫(Al pad),熔线(fuse)等造成伤害,进而影响组件特性。因此,亟待针对上述问题谋求改善的道,而使得产能及良率得以提升。
发明内容
有鉴于上述问题,本发明的目的在于提供一种蚀刻液及利用该蚀刻液选择性去除阻障层的导电凸块制造方法,其可选择性去除导电凸块(conductive bumping)下面的阻障层(barrier layer),而不伤害导电凸块及对裸露的电路结构如铝垫(Al pad),熔线(fuse)等造成伤害。
为达成上述目的,本发明是提供一种蚀刻液,其为过氧化氢(Hydrogenperoxide)、磺酸基水杨酸(Sulfosalicylic acid)、硫酸钾(Potassiumsulfate)、苯并***(Benzotriazole)及水(Water for makeup)的组成液,将该蚀刻液控制在适当的温度及酸碱值可选择性去除阻障层而不伤害导电凸块,并应用此发明于导电凸块的制造方法。
首先,提供一已制备完成集成电路组件的半导体基底,且其上具有一金属层(metal layer)及凸垫(bonding pad)。接下来,直接形成一阻障层于该金属层(metal layer)及凸垫(bonding pad)表面。随后,形成一凸块底导层(conductive under bump metallurgy layer)于该阻障层上。后续,于该凸块底导层上以涂布曝光的方式定义该凸块的图案以形成一孔洞(hole);之后,再形成一导电凸块层填入该孔洞,并去除该残留的涂布物。蚀刻该凸块底导层,再以特定组成的蚀刻液去除该阻障层。最后,加热该导电凸块使其形成一球形导电凸块。
附图说明
为使本发明的上述目的、特征和优点能更明显易懂,下文特举一较佳实施例,并配合所附图式,作详细说明如下:
图示说明:
图1A-图1F为一习知的半导体导电凸块制作剖面图。
图2A-图2D为本发明较佳实施例中的半导体导电凸块制作剖面图。
符号说明:
半导体基底-10;铝垫-12;金属凸垫-11;保护层-14;第一开口-16;阻障层-18;金属层-20;第二开口-24;光阻层-22;金属凸块-26;侧蚀-28。
半导体基底-121;金属层-119;凸垫-123;孔洞-133;阻障层-127;凸块底导层-129;光阻层-131;导电凸块-135。
具体实施方式
对于一导电凸块制程而言,于业界其有不同的结构运用。于此处特提举一实施例以说明本发明的方法应用在导电凸块制程。
首先,请参考图2A,提供一已制备完成集成电路组件(未显示)的半导体基底121,且其上具有一金属层119,其材质例如一金属铝垫(Al pad)以作为后续的导电凸块制程之用,以及一凸垫123(bonding pad),其材质例如一金属铝凸垫(Al pad)以作为后续的wire bonding或测试(testing)之用。
后续,请参考图2B,以溅镀法(sputting)、蒸镀法(evaporation)或化学气相沉积法(CVD)顺应性沉积一阻障层127(barrier layer)于该曝露的金属层119及凸垫123表面以作为用来阻挡金属于后续热制程所引发的扩散,阻障层材质例如一钨化钛金属层(TiW);并且,于形成阻障层127之前最好先于半导体基底121表面施行一湿式或干式的表面洁净处理以增加阻障层127与半导体基底121间的附着性。随后,顺应性沉积一凸块底导层129(conductive under bump metallurgy layer)于该阻障层127上,其有助于与后续将形成的金属凸块间的附着性,其为导电材质例如是一金属铜(Cu)。后续,于该凸块底导层129上以涂布方式形成一罩幕层131(masklayer),材料例如一光阻或高分子感光层,再以微影技术的对准曝光方式定义后续将形成的导电凸块(conductive bump)图案于该半导体基底121上而形成一孔洞133(hole),以作为后续形成导电凸块的电镀模板(platingtemplate)。最后,以电镀方式形成一导电凸块135层填入该孔洞133,该导电凸块135材质是一锡基材料,例如锡铅(Sn-based,SnPb)、锡(Sn)、铅(Pb)、银(Ag)或铜(Cu)或含以上金属的合金的金属焊料。
接下来,请参考图2C,藉由施行一湿式或干式蚀刻制程以去除该导电凸块135图案以外的罩幕层131。罩幕层去除之后,再以已形成的导电凸块135为罩幕,以等向性湿蚀刻(isotropic etching)方式将该曝露的凸块底导层129去除,该湿蚀刻剂例如一氢氧化铵(Ammonium Hydroxide)。之后,再藉以一等向性湿蚀刻方式将该曝露的阻障层127去除,而暴露出不制作导电凸块135的凸垫123(Al pad)及熔线(fuse)区。由于本发明的阻障层蚀刻液不会对阻障层127造成侧蚀,亦不会对裸露的电路结构如铝垫(Al pad),熔线(fuse)等造成伤害,故不须于铝垫或熔在线加一层保护层,更因此节省了一道制程。该蚀刻液有一特定的组成,例如一化学混合剂(chemical mixture),其内容包括:
1.过氧化氢(Hydrogen peroxide):10-20%
2.磺酸基水杨酸(Sulfosalicylic acid):2-30公克/公升
3.硫酸钾(Potassium sulfate):25-200公克/公升
4.苯并***(Benzotriazole):1-10公克/公升
5.水(Water for makeup)
6.温度:30-70℃
7.酸碱值<7
最后,请参考图2D,以例如热退火方式将导电凸块135加热,使焊接部分的材料产生熔化(fluxed)、回流(reflowed)及洁净的效果,该导电凸块135遂形成一球形导电凸块,以利后续与外界电路板形成较佳的电连接特性。
上述本发明的蚀刻液配方其应用的范围包括运用在不同比例的锡铅甚至无铅的导电凸块制程。此Ti-W蚀刻剂不仅只会迅速地溶解Ti-W化合物,而不会侵蚀例如铝、铬、铜或铅锡焊料,亦不会对阻障层造成侧蚀,更重要的是,不会对裸露的电路结构如铝垫(Al pad),熔线(fuse)等造成伤害,可确保组件特性不受影响。
Claims (18)
1.一种蚀刻液,其可选择性去除阻障层而不伤害导电凸块,其组成以每公升水为基准,包括:
1000毫升10-20%体积比的过氧化氢;
2-30公克的磺酸基水杨酸;
25-200公克的硫酸钾;以及
1-10公克的苯并***。
2.根据权利要求1所述的蚀刻液,其中该蚀刻液的温度为30-70℃。
3.根据权利要求1所述的蚀刻液,其中该蚀刻液的酸碱值小于7。
4.根据权利要求1所述的蚀刻液,其中该阻障层是包括一钨化钛层。
5.根据权利要求1所述的蚀刻液,其中该导电凸块是包括一锡、铅、银或铜或含以上金属的合金的金属焊料。
6.一种选择性去除阻障层的导电凸块制造方法,适用于一含集成电路的半导体基底,其上形成有一金属层及一凸垫,包括下列步骤:
顺应性形成一阻障层于该金属层及凸垫上;
电镀形成一导电凸块于该阻障层上;以及
蚀刻去除该导电凸块以外的阻障层以露出该金属层及凸垫,其中该步骤所用的蚀刻液,其组成以每公升水为基准,包括:
1000毫升10-20%体积比的过氧化氢;
2-30公克的磺酸基水杨酸;
25-200公克的硫酸钾;以及
1-10公克的苯并***。
7.根据权利要求6所述的选择性去除阻障层的导电凸块制造方法,其中该金属层是包括一铝金属层。
8.根据权利要求6所述的选择性去除阻障层的导电凸块制造方法,其中该阻障层是包括一钨化钛层。
9.根据权利要求6所述的选择性去除阻障层的导电凸块制造方法,其中形成一导电凸块之前更包括形成一凸块底导层于该阻障层上。
10.根据权利要求9所述的选择性去除阻障层的导电凸块制造方法,其中该凸块底导层是包括一铜金属层。
11.根据权利要求6所述的选择性去除阻障层的导电凸块制造方法,其中该导电凸块是包括一锡、铅、银或铜或含以上金属的合金的金属焊料。
12.一种选择性去除阻障层的导电凸块制造方法,适用于一含集成电路的半导体基底,其上形成有一金属层及一凸垫,包括下列步骤:
形成一阻障层于该金属层及凸垫上;
形成一导电凸块于该阻障层上;以及
去除该导电凸块以外的阻障层,以露出该金属层及凸垫;其中该步骤所用的蚀刻液,其组成以每公升水为基准,包括:
1000毫升10-20%体积比的过氧化氢;
2-30公克的磺酸基水杨酸;
25-200公克的硫酸钾;以及
1-10公克的苯并***。
13.根据权利要求12所述的选择性去除阻障层的导电凸块制造方法,其中该金属层是包括一铝金属层。
14.根据权利要求12所述的选择性去除阻障层的导电凸块制造方法,其中该凸垫是包括一铝金属层。
15.根据权利要求12所述的选择性去除阻障层的导电凸块制造方法,其中该阻障层是包括一钨化钛层。
16.根据权利要求12所述的选择性去除阻障层的导电凸块制造方法,其中形成一导电凸块之前更包括形成一凸块底导层于该阻障层上。
17.根据权利要求16所述的选择性去除阻障层的导电凸块制造方法,其中该凸块底导层是包括一铜金属层。
18.根据权利要求12所述的选择性去除阻障层的导电凸块制造方法,其中该导电凸块是包括一锡、铅、银或铜或含以上金属的合金的金属焊料。
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CN101211798B (zh) * | 2006-12-29 | 2010-12-08 | 台湾积体电路制造股份有限公司 | 焊料凸块结构及其制作方法 |
CN110010576A (zh) * | 2018-01-05 | 2019-07-12 | 颀邦科技股份有限公司 | 具凸块结构的半导体装置及其制造方法 |
CN110310939A (zh) * | 2018-03-27 | 2019-10-08 | 矽品精密工业股份有限公司 | 基板结构及其制法及导电凸块 |
CN117497483A (zh) * | 2023-12-27 | 2024-02-02 | 日月新半导体(昆山)有限公司 | 集成电路制造方法以及集成电路装置 |
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US5462638A (en) * | 1994-06-15 | 1995-10-31 | International Business Machines Corporation | Selective etching of TiW for C4 fabrication |
US6015505A (en) * | 1997-10-30 | 2000-01-18 | International Business Machines Corporation | Process improvements for titanium-tungsten etching in the presence of electroplated C4's |
JP2003293174A (ja) * | 2002-04-05 | 2003-10-15 | Nippon Paint Co Ltd | マグネシウム金属及び/又は合金用酸エッチング溶液及び表面処理方法 |
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CN101211798B (zh) * | 2006-12-29 | 2010-12-08 | 台湾积体电路制造股份有限公司 | 焊料凸块结构及其制作方法 |
CN110010576A (zh) * | 2018-01-05 | 2019-07-12 | 颀邦科技股份有限公司 | 具凸块结构的半导体装置及其制造方法 |
CN110310939A (zh) * | 2018-03-27 | 2019-10-08 | 矽品精密工业股份有限公司 | 基板结构及其制法及导电凸块 |
CN110310939B (zh) * | 2018-03-27 | 2021-04-30 | 矽品精密工业股份有限公司 | 基板结构及其制法及导电凸块 |
CN117497483A (zh) * | 2023-12-27 | 2024-02-02 | 日月新半导体(昆山)有限公司 | 集成电路制造方法以及集成电路装置 |
CN117497483B (zh) * | 2023-12-27 | 2024-04-12 | 日月新半导体(昆山)有限公司 | 集成电路制造方法以及集成电路装置 |
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