CN1625813A - 平面雪崩光电二极管 - Google Patents
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Abstract
本发明包括一种平面雪崩光电二极管，其包括限定平面接触区域的第一n－型半导体层，和具有p－型扩散区域的第二n－型半导体层。该结构进一步的特征包括n－型半导体倍增层、n－型半导体吸收层，以及p－型接触层。进一步的实施例包括一种平面雪崩光电二极管，其具有限定平面接触区域的第一n－型半导体层，n－型半导体倍增层，n－型半导体吸收层，以及与p－型接触层电耦合的p－型半导体层。
Description
技术领域
本发明涉及雪崩光电二极管，特别地，涉及具有平面p-n结的台式结构雪崩光电二极管。
背景技术
由于已知的光子和电子间的相互作用，近些年在光电探测器领域取得了巨大的进展，特别是在利用半导体材料的光电探测器领域。一种基于半导体的光电探测器称作雪崩光电二极管。这种类型的结构通常由大量用作不同的目的，例如吸收和倍增，的固体半导体材料构成。
雪崩光电二极管结构通过激发态电荷载流子的行为提供大增益的主要益处，激发态电荷载流子在倍增层中产生大量的电子空穴对。然而，雪崩光电二极管产生大量电荷载流子是如此地高效以致于有被饱和的危险，从而对器件带宽产生有害影响。为了防止电荷载流子崩溃，强制电场在雪崩光电二极管内自我调控，且特别地期望使倍增层中的电场显著地高于吸收层的电场。
台式雪崩光电二极管具有暴露的高场pn结(exposed high fieldp-n junction)，其难以用绝缘材料层钝化。因此，标准商业InP/InGaAs雪崩光电二极管使用平面扩散结构，其隐埋pn结从而使得坚固耐用、器件寿命延长。然而这些InP雪崩光电二极管需要对p-型半导体区域的深度和掺杂密度进行极其精确的扩散控制。这种关键控制是至关重要的，因为该扩散控制着倍增区域内的电场大小、雪崩区域的长度以及电荷控制。
目前还没有提出真正的平面InAlAs雪崩光电二极管。现有的雪崩光电二极管具有腐蚀隔离环(etched isolation ring)，其被腐蚀暴露出高场雪崩区域的顶部，之后进行深度钛轰击以进一步隔离高场区域。然后进行锌扩散以接触p-型半导体区域。这是非常复杂的结构，需要关键的腐蚀和轰击步骤。尽管有这些努力，但是人们认为，这种雪崩光电二极管的寿命比它们的标准平面雪崩光电二极管短10倍，因此不足以用于电信使用。
因此，技术上需要一种简单而有效的雪崩光电二极管，其能够廉价地加以制造且具有高效的关键控制。因而，本发明涉及一种平面雪崩光电二极管，其包括限定平面接触区域的第一n-型半导体层，和具有p-型扩散区域的第二n-型半导体层。该结构进一步的特征包括n-型半导体倍增层和n-型半导体吸收层以及p-型接触层。p-型扩散区域与p-型接触层直接相邻布置，借此降低平面雪崩光电二极管的电容，同时增加结构的速度、寿命和成本效益。本发明进一步的实施例和优点在下面通过参考附图加以讨论。
附图简述
图1是根据本发明第一实施例的平面雪崩光电二极管的剖面图。
图2是根据本发明可选择实施例的平面雪崩光电二极管的剖面图。
图3是根据本发明可选择实施例的微型台平面雪崩光电二极管的剖面图。
优选实施例详细说明
根据本发明的优选实施例，出于光电导目的提供了一种外延结构。光电导结构是雪崩光电二极管，其通过在pn结进行扩散p-型掺杂加以优化以提高性能。本发明结构和制造方法的详情在这里进一步加以讨论。
参考图1，显示了根据本发明第一实施例的平面雪崩光电二极管10的剖面图。平面雪崩光电二极管10包括p-型接触层12和提供平面接触区域的第一n-型半导体层28。在第二n-型半导体层16上布置p-型接触层12，第二n-型半导体层16包括用于控制p-n结处电场的p-型扩散区域14，p-n结由p-型接触层12和第二n-型半导体层16形成。
平面雪崩光电二极管10进一步包括n-型半导体吸收层20，其通过第一分级层(grading layer)18a与第二n-型半导体层隔离。n-型吸收层20布置在n-型半导体倍增层24上。在优选实施例中，n-型半导体吸收层20通过p-型半导体电荷控制层22和优选地第二分级层18b与n-型倍增层24隔离。用于收集电子的一对n-型接触层26示出位于第一n-型半导体层28上。
第一n-型半导体层28从由三元半导体或者族III-V半导体构成的中选择。因此，第一n-型半导体层28是族III中的任意两个元素与族V中的一个元素的组合，或者相反，是族V中两个元素与族III中一个元素的组合。下面显示了周期表中典型族的表格。
| 族II | 族III | 族IV | 族V |
| 锌(Zn) | 铝(Al) | 硅(Si) | 磷(P) |
| 镉(Cd) | 镓(Ga) | 锗(Ge) | 砷(As) |
| 汞(Hg) | 铟(In) | 锑(Sb) |
在优选实施例中，第一n-型半导体层28是InAlAs。然而，应当理解，第一n-型半导体层28可以是任何为平面雪崩光电二极管10的优化性能提供所需能带隙的三元半导体。
n-型半导体倍增层24也从由三元半导体或者族III-V的半导体构成的组中选择。在优选实施例中，n-型半导体倍增层24是InAlAs。优选地，n-型半导体吸收层20也从由三元半导体或者族III-V的半导体构成的组中选择。在优选实施例中，n-型半导体吸收层20是InGaAs。然而，应当理解，n-型半导体吸收层20和n-型半导体倍增层24可以是任何为平面雪崩光电二极管10的优化性能提供所需能带隙的三元半导体。
第二n-型半导体层16也从由三元半导体或者族III-V的半导体构成的组中选择。如前，第二n-型半导体层16是族III中的任意两个元素与族V中一个元素的组合，或者相反，是族V中两个元素与族III中一个元素的组合。在优选实施例中，第二n-型半导体层16是InAlAs。然而，应当理解，第二n-型半导体层18可以是任何为平面雪崩光电二极管10的优化性能提供所需能带隙的三元半导体。
注意到，第二n-型半导体层16部分地限定了p-型扩散区域14，其位于在先前和p-型接触区域12之间形成的结附近。p-型扩散区域14降低了前述p-n结处平面雪崩光电二极管10的电容，借此提高了结构的整体速度。
平面雪崩光电二极管10的一个方面是所有的临界层厚度和掺杂浓度都在起始晶体生长中调节，从而处于优良的控制之下，能够可再现地(reproducibly)生长，且在整个晶片上均匀。因此，在制造期间与处理控制有关的困难，特别是那些与扩散步骤有关的困难，在本发明中不存在。
在本发明的另一个方面中，如图2所示，平面雪崩光电二极管110包括场控制结构30，例如n-型注入施主或者深施主(deep donor)。场控制结构30示意地显示为一对进入平面雪崩光电二极管110的侵入体。然而，在实际应用中，场控制结构30由经过注入处理的平面雪崩光电二极管110区域构成，如这里进一步讨论的。
和在本发明第一实施例中的一样，平面雪崩光电二极管110包括p-型接触层12和提供平面接触区域的第一n-型半导体层28。p-型接触层12布置在第二n-型半导体层16上，第二n-型半导体层16包括p-型扩散区域14，其用于控制由p-型接触层12和第二n-型半导体层16形成的p-n结处的电场。场控制结构30在前述p-n结附近提供了附加的电场降低。
场控制结构30优选地采取注入n-型半导体或离子的形式。例如，场控制结构30可以采取具有注入到平面雪崩光电二极管110内的Si的区域形式。选择地，深施主，例如氢或氦，能够注入到由场控制结构30表示的区域内。场控制结构30的效果也能够通过输入区域(region of import)的氢钝化实现。各种形式的场控制结构30都不渗入n-型半导体倍增层24，因为在该区域中期望维持高电场。
在可选择实施例中，如图3所示，平面雪崩光电二极管210包括微型台结构。如此，上述的第二n-型半导体层用外延生长的p-型半导体层32代替。优选地，p-型半导体层32是InAlAs，但是应当理解，p-型半导体层32可以是能够为优化性能提供合适能带隙的任何类型的III-V半导体。
如在先前实施例中一样，平面雪崩光电二极管210还包括p-型接触层12和提供平面接触区域的第一n-型半导体层28。p-型接触层12布置在p-型半导体层32的上面。钝化层34以对称的方式布置在p-型半导体层32和平面雪崩光电二极管其余结构的附近。
在图3所示的实施例中，初始生长全部结构，包括p-型半导体层32，然后加以腐蚀直到第一n-型半导体吸收层20。前述处理限定了控制相关电容区域的局部p-接触区域，从而产生低电容和高速雪崩光电二极管。而且，整个平面雪崩光电二极管32外延地生长，且不需要任何p-型扩散。
形成钝化区域34的一种特别有利的方法是利用湿氧化。p-型半导体层32能够被氧化到其中一个n-型半导体吸收层20或者第一分级层18a。类似地，外台面(outer mesa)的侧面，其包括n-型半导体倍增层24、p-型半导体电荷控制层和第二分级层18b，能够如图3所示地被氧化。最后，可以氧化第一n-型半导体层28，从而在未氧化和氧化层之间存在过渡界面(gradual interface)。这会降低第一n-型半导体层28和n-型半导体倍增层24之间界面处的电场，导致更好的钝化。
钝化方法可以与质子或氧注入相结合，以便附加控制p-型半导体电荷控制层22和减小外台面边缘的场，从而进一步改进钝化。合适的钝化技术包括使用表面钝化材料，例如BCB(环丁烯苯)(benzocyclobutene)。选择地，其它的表面钝化材料，例如二氧化硅、氮化硅或者聚酰亚胺，也能够用于钝化平面雪崩光电二极管210的外侧。
正如所说明的，本发明比现有的雪崩光电二极管提供了大量的优点。特别地，本发明的结构是真正平面的。而且，图1所示平面雪崩光电二极管10的结构与典型的InP/InGaAs雪崩光电二极管的几何形状相反，因为电子在n-型半导体倍增层24中雪崩，这与在先前的雪崩光电二极管中发现的InP倍增区域内的空穴雪崩相反。该结构倒换允许InGaAs吸收区域内的低场区域位于器件的顶部，而不是象在标准InP雪崩光电二极管中一样的高场雪崩区域。
对本领域技术人员应当显而易见，上述实施例只是本发明许多可能的具体实施例的少数几个实例。本领域技术人员能够容易地设计大量的各种其它布置而不背离由随后的权利要求限定的本发明的精神和范围。
Claims (29)
1.一种平面雪崩光电二极管，包括：
限定接触区域的第一n-型半导体层；
具有p-型扩散区域的第二n-型半导体层；
n-型半导体倍增层；
n-型半导体吸收层；和
p-型接触层；
其中p-型扩散区域布置成与p-型接触层直接相邻。
2.根据权利要求1的平面雪崩光电二极管，进一步包括至少一个分级层，其与n-型半导体吸收层相邻布置。
3.根据权利要求1的平面雪崩光电二极管，进一步包括p-型半导体电荷控制层，其与n-型半导体倍增层相邻布置。
4.根据权利要求1的平面雪崩光电二极管，进一步包括至少一个n-型接触层。
5.根据权利要求1的平面雪崩光电二极管，其中第一n-型半导体层是InAlAs。
6.根据权利要求1的平面雪崩光电二极管，其中第二n-型半导体层是InAlAs。
7.根据权利要求1的平面雪崩光电二极管，其中n-型半导体倍增层是InAlAs。
8.根据权利要求1的平面雪崩光电二极管，其中n-型半导体吸收层是InGaAs。
9.一种制造平面雪崩光电二极管的方法，包括如下步骤：
提供限定接触区域的第一n-型半导体层；
沉积第二n-型半导体层；
沉积n-型半导体倍增层；
沉积n-型半导体吸收层；
沉积p-型接触层；和
扩散直接与p-型接触层相邻的p-型扩散区域，由此降低平面雪崩光电二极管的电容。
10.根据权利要求9的方法，进一步包括沉积至少一个与n-型半导体吸收层相邻的分级层的步骤。
11.根据权利要求9的方法，进一步包括沉积与n-型半导体倍增层相邻的p-型半导体电荷控制层的步骤。
12.根据权利要求9的方法，进一步包括沉积至少一个n-型接触层的步骤。
13.根据权利要求9的方法，其中第一n-型半导体层是InAlAs。
14.根据权利要求9的方法，其中第二n-型半导体层是InAlAs。
15.根据权利要求9的方法，其中n-型半导体倍增层是InAlAs。
16.根据权利要求9的方法，其中n-型半导体吸收层是InGaAs。
17.一种平面雪崩光电二极管，包括限定接触区域的第一n-型半导体层，和p-型接触区域，该平面雪崩光电二极管包括：
具有p-型扩散区域的第二n-型半导体层；
n-型半导体倍增层；
n-型半导体吸收层；以及
其中p-型扩散区域布置成与p-型接触层直接相邻。
18.根据权利要求17的平面雪崩光电二极管，其中第一n-型半导体层是InAlAs，第二n-型半导体层是InAlAs，n-型半导体倍增层是InAlAs，而n-型半导体吸收层是InGaAs。
19.一种平面雪崩光电二极管，包括：
限定接触区域的第一n-型半导体层；
p-型半导体层；
n-型半导体倍增层；
n-型半导体吸收层；和
p-型接触层；
其中p-型半导体层布置成与p-型接触层直接相邻。
20.根据权利要求19的平面雪崩光电二极管，进一步包括至少一个与n-型半导体吸收层相邻布置的分级层。
21.根据权利要求19的平面雪崩光电二极管，进一步包括与n-型半导体倍增层相邻布置的p-型半导体电荷控制层。
22.根据权利要求19的平面雪崩光电二极管，进一步包括至少一个n-型接触层。
23.根据权利要求19的平面雪崩光电二极管，其中第一n-型半导体层是InAlAs。
24.根据权利要求19的平面雪崩光电二极管，其中第二n-型半导体层是InAlAs。
25.根据权利要求19的平面雪崩光电二极管，其中n-型半导体倍增层是InAlAs。
26.根据权利要求19的平面雪崩光电二极管，其中n-型半导体吸收层是InGaAs。
27.根据权利要求19的平面雪崩光电二极管，其中p-型半导体层是InAlAs。
29.根据权利要求19的平面雪崩光电二极管，进一步包括钝化区域，该钝化区域包括一部分p-型半导体层和一部分n-型半导体吸收层。
30.根据权利要求29的平面雪崩光电二极管，其中钝化区域进一步包括一部分第一分级层18a和一部分n-型半导体倍增层24。
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2003
- 2003-02-03 AU AU2003214995A patent/AU2003214995A1/en not_active Abandoned
- 2003-02-03 WO PCT/US2003/003323 patent/WO2003065418A2/en active Application Filing
- 2003-02-03 CA CA2474560A patent/CA2474560C/en not_active Expired - Lifetime
- 2003-02-03 CN CNA038030381A patent/CN1625813A/zh active Pending
- 2003-02-03 EP EP03710845.3A patent/EP1470575B1/en not_active Expired - Lifetime
- 2003-02-03 JP JP2003564912A patent/JP4938221B2/ja not_active Expired - Lifetime
- 2003-02-03 US US10/502,110 patent/US7348607B2/en not_active Expired - Lifetime
-
2004
- 2004-04-30 US US10/836,878 patent/US7348608B2/en not_active Expired - Lifetime
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2010
- 2010-10-12 JP JP2010229902A patent/JP2011009788A/ja active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103081130A (zh) * | 2010-09-02 | 2013-05-01 | Ntt电子股份有限公司 | 雪崩光电二极管 |
| US9006854B2 (en) | 2010-09-02 | 2015-04-14 | Ntt Electronics Corporation | Avalanche photodiode |
| CN103081130B (zh) * | 2010-09-02 | 2016-06-22 | Ntt电子股份有限公司 | 雪崩光电二极管 |
| CN103390680A (zh) * | 2012-05-10 | 2013-11-13 | 三菱电机株式会社 | 雪崩光电二极管及其制造方法 |
| CN104603958A (zh) * | 2012-05-17 | 2015-05-06 | 派克米瑞斯有限责任公司 | 平面雪崩光电二极管 |
| CN108075010A (zh) * | 2012-05-17 | 2018-05-25 | 派克米瑞斯有限责任公司 | 平面雪崩光电二极管 |
| CN107768462A (zh) * | 2017-11-02 | 2018-03-06 | 天津大学 | 两级台面铟镓砷/铟磷雪崩光电二极管及其制备方法 |
| CN111684599A (zh) * | 2017-12-06 | 2020-09-18 | 脸谱科技有限责任公司 | 多光电二极管像素单元 |
| CN111684599B (zh) * | 2017-12-06 | 2023-12-08 | 元平台技术有限公司 | 多光电二极管像素单元 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003065418A3 (en) | 2003-12-18 |
| JP2011009788A (ja) | 2011-01-13 |
| EP1470575A4 (en) | 2010-05-05 |
| AU2003214995A1 (en) | 2003-09-02 |
| EP1470575A2 (en) | 2004-10-27 |
| US7348607B2 (en) | 2008-03-25 |
| EP1470575B1 (en) | 2018-07-25 |
| US20050156192A1 (en) | 2005-07-21 |
| US7348608B2 (en) | 2008-03-25 |
| JP4938221B2 (ja) | 2012-05-23 |
| JP2005539368A (ja) | 2005-12-22 |
| CA2474560C (en) | 2012-03-20 |
| WO2003065418A2 (en) | 2003-08-07 |
| CA2474560A1 (en) | 2003-08-07 |
| US20040251483A1 (en) | 2004-12-16 |
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