CN1617212A - Voltage stabilizing compensating type follower - Google Patents
Voltage stabilizing compensating type follower Download PDFInfo
- Publication number
- CN1617212A CN1617212A CN 200310115309 CN200310115309A CN1617212A CN 1617212 A CN1617212 A CN 1617212A CN 200310115309 CN200310115309 CN 200310115309 CN 200310115309 A CN200310115309 A CN 200310115309A CN 1617212 A CN1617212 A CN 1617212A
- Authority
- CN
- China
- Prior art keywords
- transistor
- grid
- drain electrode
- voltage
- linear amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The present invention provides a kind of voltage stabilizing and compensating follower and aims at providing follower with relatively high reaction speed and less vibration. It has one second linear amplifier, rather than comparator, and two transistors (MN1 and MN2) with grids connected to the same bias line to make the transistor MP2 and the transistor MN2 enter saturation state while the output voltage drifts upwards so as to make the transistor MN3 on. The voltage stabilizing and compensating makes the voltage dividing output possess stable voltage and no vibration.
Description
Technical field
The present invention relates to a kind of voltage stabilizing offset-type follower (follower), relate in particular to a kind of voltage stabilizing offset-type follower that adopts the voltage stabilizing compensation solution of the driver output voltage that solves LCD.
Background technology
The design of the driver of LCD is to utilize the driving of follower as each dividing potential drop, not only can stablize each partial pressure value, and can be according to different bias requirement, the suitable charge or discharge LCD with the different demands of arranging in pairs or groups is provided on one's own initiative.
The practice (seeing also Fig. 1) of known stable high level dividing potential drop is to add one to push away and fall resistance DR1 or comparator C 1 on dividing potential drop RV1 (dividing potential drop between resistance R 1, R2), when output end voltage V1 rises, comparator C 1 induction and open metal-oxide semiconductor (MOS) MN output end voltage V1 is retracted.But the follower of the output end voltage V1 that driver produces in known is the malleation trend drives (Drive high easy), this follower itself descends to having to voltage and well retracts compensation effect, but when its electrical level rising, but can't efficiently it be retracted to hold voltage.
The shortcoming of the known practice is to fix through pushing away the electric current that falls resistance DR1, so can't bring into play effect timely; The reaction velocity of comparator C 1 can be slower again, needs 6000 nanoseconds (ns) approximately, and be easy to generate vibration 20 (seeing also Fig. 2).
Again, the way of known stable low-level output voltage (seeing also Fig. 3) is to add one to promote resistance PR4 or comparator C 4 on output end voltage V4, when output end voltage V4 descends, comparator C 4 induction and open metal-oxide semiconductor (MOS) MP output end voltage V4 is retracted.But in the known practice, the follower of the output end voltage V4 that driver produces is that the low pressure trend drives (Drive low easy), this follower itself rises to have to voltage and well retracts voltage regulation result, but when its level descends, but can't efficiently it be retracted to hold voltage.
The shortcoming of the known practice electric current that promotes resistance PR4 that is to flow through is fixed, so can't bring into play effect timely; The reaction velocity of comparator C 4 can be slower again, needs 6000 nanoseconds (ns) approximately, and be easy to generate vibration 40 (seeing also Fig. 4).
Summary of the invention
So fundamental purpose of the present invention is to solve above-mentioned known defective, avoid defective to exist, the invention provides a kind of voltage stabilizing offset-type follower, it is slow and be easy to generate the problem of vibration that purpose is to solve the follower reaction velocity of known drive device dividing potential drop.
To achieve these goals, method of the present invention is to replace known comparer with one second linear amplifier, the output terminal of this first linear amplifier is connected with its negative pole (-), and extend to the dividing potential drop output terminal by an output line, it is characterized in that this dividing potential drop also inserts the positive pole (+) of one second linear amplifier when inserting the positive pole (+) of first linear amplifier, the output terminal of same this second linear amplifier is connected with its negative pole (-).
The output terminal of this second linear amplifier also is connected with a transistor (MN1) with a transistor (MP1) again, and the grid (G) of this transistor (MN1) connects a bias line.One transistor (MP2) is connected with above-mentioned output line, its grid (G) is connected with the grid (G) of above-mentioned transistor (MP1), and the drain electrode (D) of this transistor (MP2) is connected with the drain electrode (D) of a transistor (MN2), and the grid (G) of this transistor (MN2) is the same as with the grid (G) of above-mentioned transistor (MN1) being connected to a bias line.The drain electrode (D) of one transistor (MN3) is connected with above-mentioned output line, and its grid (G) is connected with the grid (G) of above-mentioned transistor (MP2).
Therefore, the advantage of voltage stabilizing offset-type follower provided by the invention for reaction velocity faster second linear amplifier replace known comparer, need approximately only 200 nanoseconds (ns), and the voltage of dividing potential drop output terminal (V1) is stablized nonoscillatory.And identical circuit bind mode by the replacement of transistor kind, can be done the voltage stabilizing compensation of voltage to the low level dividing potential drop.
Description of drawings
Fig. 1 is the circuit diagram that known malleation trend drives follower.
Fig. 2 is a V1 voltage output synoptic diagram among Fig. 1.
Fig. 3 is the circuit diagram that known low pressure trend drives follower.
Fig. 4 is a V4 voltage output synoptic diagram among Fig. 3.
Fig. 5 is the circuit diagram that malleation trend of the present invention drives follower.
Fig. 6 is that output voltage V out and output end voltage V1 concern synoptic diagram among Fig. 3.
Fig. 7 is an output end voltage V1 output synoptic diagram among Fig. 3.
Fig. 8 is the circuit diagram that low pressure trend of the present invention drives follower.
Fig. 9 is an output end voltage V4 output synoptic diagram among Fig. 8.
Embodiment
Relevant detailed content of the present invention and technical descriptioon, existing conjunction with figs. is described as follows:
Seeing also shown in Figure 5ly, is the circuit diagram that malleation of the present invention trend drives follower.As shown in the figure: dividing potential drop RV1 (dividing potential drop between resistance R E1, the RE2) Dian Chu of driver (not shown) and the positive pole (+) of one first linear amplifier OP1 are joined, the output terminal of this first linear amplifier OP1 is connected with its negative pole (-), and extend to dividing potential drop output end voltage V1 by an output line 50, it is characterized in that this dividing potential drop RV1 also inserts the positive pole (+) of one second linear amplifier OP2 when inserting the positive pole (+) of the first linear amplifier OP1, equally, the output terminal of this second linear amplifier OP2 also is connected with its negative pole (-).
Again, the output terminal of this second linear amplifier OP2 also is connected with the source S of a transistor MP1, and the drain D of this transistor MP1 is connected with the grid G of self and is connected with the drain D of a transistor MN1, and the source S of this transistor MN1 is connected with power supply Vss, and its grid G meets a bias line BN.
One transistor MP2, the source S of this transistor MP2 is connected with above-mentioned output line 50, its grid G is connected with the grid G of above-mentioned transistor MP1, and the drain D of this transistor MP2 is connected with the drain D of a transistor MN2, the source S of this transistor MN2 is connected with power supply Vss, and its grid G is the same as being connected to a bias line BN with the grid G of above-mentioned transistor MN1.
One transistor MN3, the drain D of this transistor MN3 is connected with above-mentioned output line 50, and its grid G is connected with the drain D junction of transistor MN2 with the drain D of above-mentioned transistor MP2, and its source S is connected with power supply Vss.
Wherein, this transistor MP1 and transistor MP2 are that matrix is that the metal oxide semiconductor field effect of positive ion structure is answered transistor (P-MOSFET); This transistor MN1, transistor MN2 and transistor MN3 are that matrix is that the metal oxide semiconductor field effect of negative ion structure is answered transistor (N-MOSFET).
By the circuit of the invention described above, the voltage stabilizing reaction velocity that can reach output end voltage V1 is fast, and stable nonoscillatory, its action relationships following (it being described with Fig. 5 circuit diagram):
One, when output end voltage V1 equals the voltage of dividing potential drop RV1, when promptly voltage did not float, the gate-source voltage of transistor MP1 (VgsMP1) equaled the gate-source voltage (VgsMP2) of transistor MP2, and available VgsMP1=VgsMP2 represents.Make the W/L of the W/L of transistor MP1 greater than transistor MP2 again in design, wherein, the distance of grid is called passage length (L) between source electrode and the drain electrode, and the width of source electrode and drain electrode itself is called channel width (W); The electric current I 1 of transistor MP1 of flowing through under all saturated state of transistor MP1, transistor MP2 will be greater than the electric current I 2 of the transistor MP2 that flows through (I1＞I2).But transistor MN1 equals transistor MN2, so under the saturated state of transistor MN1, transistor MN2 is conducting (turn-on), the output voltage V out between this moment transistor MP2 and transistor MN2 is an electronegative potential, and transistor MN3 closes (turn-off).
Two, when the electrical level rising of output end voltage V1, the gate-source voltage of transistor MP2 (VgsMP2) increases, last transistor MN2 reaches state of saturation, this moment is under transistor MP2 and the equal state of saturation of transistor MN2, output voltage V out between transistor MP2 and transistor MN2 equals output end voltage V1 level and takes advantage of the drain-source electrode resistance (Drain-Source Resistor) in transistor MP2 (RdsMP2) to add drain-source electrode resistance (RdsMN2) sum of transistor MN2 divided by the drain-source electrode resistance (RdsMP2) of transistor MP2, relational expression represents that as Vout=(V1-Vss) * RdsMP2/ (RdsMP2+RdsMN2) this moment, the design of Vout needed to have higher current potential to be enough to turn-on transistor MN3.
Three, if output end voltage V1 raises up when too high, transistor MP2 will enter linear conducting (Turn-on linear), and transistor MN2 reaches state of saturation, output voltage V out between transistor MP2 and transistor MN2 will be noble potential (near output end voltage V1) at this moment, and transistor MN2 is conducting at this moment.
Now represent when the output end voltage V1 rising voltage difference delta V with calculation mode, how the W/L ratio of transistor MP1 and transistor MP2 can make transistor MP2 and transistor MN2 enter state of saturation simultaneously, and circuit promptly of the present invention can be controlled the induced electricity pressure reduction Δ V of desire compensation.
Transistor MP1:
I1＝(K/2)(W
MP1/L
MP1)(VgsMP1-Vth)^2
Again, VgsMP1=RV1-VB
VB＝RV1-Vth-ΔV1
(wherein, RV1 is the fixed reference potential value by resistance R E1 and resistance R E2 dividing potential drop, Δ V1=(2L
MP1* I1/KW
MP1) ^0.5)
(according to basic calculating formula I1=(the K/2) (W of MOS
MP1/ L
MP1) (VgsMP1-Vth) ^2, about open radical sign and get (I1) ^0.5=(KW
MP1/ 2L
MP1) ^0.5 (VgsMP1-Vth), get VgsMP1=Vth+ (2L at last
MP1* I1/KW
MP1) ^0.5, this (2L
MP1* I1/KW
MP1) ^0.5 is Δ V1 value)
So I1=(K/2) (W
MP1/ L
MP1) (Δ V1) ^2
Transistor MP2:
I2＝(K/2)(W
MP2/L
MP2)(VgsMP2-Vth)^2
Again, VgsM2=RV1-VB
VB＝RV1-Vth-ΔV1
V1＝RV1+ΔV
So I2=(K/2) (W
MP2/ L
MP2) (Δ V+ Δ V1) ^2
Again, I1=I2, and make L
MP1=L
MP2
Can get Δ V=((W
MP1/ W
MP2) ^0.5-1) * Δ V1
Wherein, output voltage V out between this transistor MN2 and output end voltage V1's concerns that synoptic diagram as shown in Figure 6.
Like this, according to the advantage of the follower of voltage stabilizing of the present invention compensation be with reaction velocity faster the second linear amplifier OP2 replace known comparator C 1, approximately only need 200 nanoseconds (ns), and output end voltage V1 stablizes nonoscillatory 70 (seeing also Fig. 7).
Another embodiment of the present invention be with matrix among the last embodiment be the metal oxide semiconductor field effect of positive ion structure to answer transistor to replace to matrix be that the metal oxide semiconductor field effect of negative ion structure is answered transistor, to answer transistor to replace to matrix be that the metal oxide semiconductor field effect of positive ion structure is answered transistor and matrix is the metal oxide semiconductor field effect of negative ion structure; According to above-mentioned identical circuit bind mode, can do the voltage stabilizing compensation of a voltage to the low level dividing potential drop.Its circuit description following (seeing also shown in Figure 8):
Dividing potential drop RV4 (dividing potential drop between resistance R E4, the RE5) Dian Chu of driver (not shown) and the positive pole (+) of one first linear amplifier OP81 are joined, the output terminal of this first linear amplifier OP81 is connected with its negative pole (-), and extend to output end voltage V4 by an output line 80, it is characterized in that this dividing potential drop RV4 also inserts the positive pole (+) of one second linear amplifier OP82 when inserting the positive pole (+) of the first linear amplifier OP81, equally, the output terminal of this second linear amplifier OP82 is connected with its negative pole (-).
The output terminal of this second linear amplifier OP82 can substitute for the source S with a transistor MN21 and is connected again, and the drain D of this transistor MN21 is connected with the grid G of self and is connected with the drain D of a transistor MP21, the source S of this transistor MP21 is connected with power supply V0, and its grid G meets a bias line BP.
One transistor MN22, the source S of this transistor MN22 is connected with above-mentioned output line 50, its grid G is connected with the grid G of above-mentioned transistor MN21, and the drain D of this transistor MN22 is connected with the drain D of a transistor MP22, the source S of this transistor MP22 is connected with power supply V0, and its grid G is the same as being connected to a bias line BP with the grid G of above-mentioned transistor MP21.
One transistor MP23, the drain D of this transistor MP23 is connected with above-mentioned output line 80, and its grid G is connected with the drain D junction of transistor MP22 with the drain D of above-mentioned transistor MN22, and its source S is connected with power supply V0.
Wherein this transistor MN21 and transistor MN22 are that matrix is that the metal oxide semiconductor field effect of negative ion structure is answered transistor; This transistor MP21, transistor MP22 and transistor MP23 are that matrix is that the metal oxide semiconductor field effect of positive ion structure is answered transistor.
By the circuit of the foregoing description, the voltage stabilizing reaction velocity that can reach output end voltage V4 is fast, and stable nonoscillatory, its action relationships following (it being described with Fig. 8 circuit diagram):
One, when output end voltage V4 equals the voltage of dividing potential drop RV4, when promptly voltage did not float, the gate-source voltage of transistor MN21 (VgsMN21) equaled the gate-source voltage (VgsMN22) of transistor MN22, and available VgsMN22=VgsMN22 represents.Make the W/L of the W/L of transistor MN21 greater than transistor MN22 again in design, wherein, the distance of grid is called passage length (L) between source electrode and the drain electrode, and the width of source electrode and drain electrode itself is called channel width (W); The electric current I 1 of transistor MN21 of flowing through under all saturated state of transistor MN21, transistor MN22 will be greater than the electric current I 2 of the transistor MN22 that flows through (I1＞I2).But transistor MP21 equals transistor MP22, so under the saturated state of transistor MP21, transistor MP22 is conducting (turn-on), and the output voltage V out between transistor MN22 and transistor MP22 is an electronegative potential at this moment, and transistor MP23 closes (turn-off).
Two, when the electrical level rising of output end voltage V4, the gate-source voltage of transistor MN22 (VgsMP2) increases, last transistor MP22 reaches state of saturation, this moment is under transistor MN22 and the equal state of saturation of transistor MP22, output voltage V out between transistor MN22 and transistor MP22 equals output end voltage V4 level and takes advantage of drain-source electrode resistance (RdsMP22) sum that adds transistor MP22 in the drain-source electrode resistance (RdsMN22) of transistor MN22 divided by the drain-source electrode resistance (RdsMN22) of transistor MN22, relational expression represents that as Vout=(V0-V4) * RdsMN22/ (RdsMN22+RdsMP22) this moment, the design of Vout needed to have higher current potential to be enough to turn-on transistor MP23.
Three, if output end voltage V4 raises up when too high, transistor MN22 will enter linear conducting, and transistor MP22 reaches state of saturation, and the output voltage V out between transistor MN22 and transistor MP22 will be noble potential (near output end voltage V1) at this moment, and transistor MP22 is conducting at this moment.
Now represent when the output end voltage V4 rising voltage difference delta V with calculation mode, how the W/L ratio of transistor MN21 and transistor MN22 can make transistor MN22 and transistor MP22 enter state of saturation simultaneously, and circuit promptly of the present invention can be controlled the induced electricity pressure reduction Δ V of desire compensation.
Transistor MN21:
I1＝(K/2)(W
MN21/L
MN21)(VgsMN21-Vth)^2
Again, VgsMN21=RV4-VB
VB＝RV4-Vth-ΔV4
(wherein, RV4 is the fixed reference potential value by resistance R E4 and resistance R E5 dividing potential drop, Δ V4=(2L
MN21* I1/KW
MN21) ^0.5)
(according to basic calculating formula I1=(the K/2) (W of MOS
MN21/ L
MN21) (VgsMN21-Vth) ^2, about open radical sign and get (I1) ^0.5=(KW
MN21/ 2L
MN21) ^0.5 (VgsMN21-Vth), get VgsMN21=Vth+ (2L at last
MN21* I1/KW
MN21) ^0.5, this (2L
MN21* I1/KW
MN21) ^0.5 is Δ V4 value)
So I1=(K/2) (W
MN21/ L
MN21) (Δ V4) ^2
Transistor MN22:
I2＝(K/2)(W
MN22/L
MN22)(VgsMN22-Vth)^2
Again, VgsMN22=RV4-VB
VB＝RV4-Vth-ΔV4
V4＝RV1+ΔV
So I2=(K/2) (W
MN22/ L
MN22) (Δ V+ Δ V4) ^2
Again, I1=I2, and make L
MN21=L
MN22
Can get Δ V=((W
MN21/ W
MN22) ^0.5-1) * Δ V4
In this way, according to the advantage of voltage stabilizing offset-type follower of the present invention be with reaction velocity faster the second linear amplifier OP82 replace known comparator C 1, approximately only need 200 nanoseconds (ns), and output end voltage V4 stablizes nonoscillatory 90 (seeing also Fig. 9).
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (6)
1. voltage stabilizing offset-type follower, employing is at the voltage stabilizing compensation solution of the driver high-level output voltage of LCD, dividing potential drop (RV1) Dian Chu of driver and the positive pole (+) of one first linear amplifier (OP1) are joined, the output terminal of described first linear amplifier (OP1) is connected with its negative pole (-), and extends to an output end voltage (V1) by an output line (50);
It is characterized in that: described dividing potential drop (RV1) also inserts the positive pole (+) of one second linear amplifier (OP2) when inserting the positive pole (+) of first linear amplifier (OP1), equally, the output terminal of described second linear amplifier (OP2) is connected with its negative pole (-);
The output terminal of described again second linear amplifier (OP2) also is connected with the source electrode (S) of a transistor (MP1), and the drain electrode (D) of described transistor (MP1) is connected with the grid (G) of self and is connected with the drain electrode (D) of a transistor (MN1), the source electrode (S) of described transistor (MN1) is connected with power supply (Vss), and its grid (G) connects a bias line (BN);
One transistor (MP2), the source electrode (S) of described transistor (MP2) is connected with above-mentioned output line (50), its grid (G) is connected with the grid (G) of above-mentioned transistor (MP1), and the drain electrode (D) of described transistor (MP2) is connected with the drain electrode (D) of a transistor (MN2), the source electrode (S) of described transistor (MN2) is connected with power supply (Vss), and its grid (G) is the same as being connected to a bias line (BN) with the grid (G) of above-mentioned transistor (MN1);
One transistor (MN3), the drain electrode (D) of described transistor (MN3) is connected with above-mentioned output line (50), its grid (G) is connected with drain electrode (D) junction of transistor (MN2) with the drain electrode (D) of above-mentioned transistor (MP2), and its source electrode (S) is connected with power supply (Vss).
2. voltage stabilizing offset-type follower according to claim 1 is characterized in that described transistor (MP1) and transistor (MP2) are that matrix is that the metal oxide semiconductor field effect of positive ion structure is answered transistor.
3. voltage stabilizing offset-type follower according to claim 1 is characterized in that described transistor (MN1), transistor (MN2) and transistor (MN3) are that matrix is that the metal oxide semiconductor field effect of negative ion structure is answered transistor.
4. voltage stabilizing offset-type follower according to claim 1, also can be used for the voltage stabilizing compensation of low-level output voltage, the positive pole (+) that dividing potential drop (RV4) the some place of driver is connect one first linear amplifier (OP81) joins, the output terminal of described first linear amplifier (OP81) is connected with its negative pole (-), and extends to an output end voltage V4 by an output line (80);
It is characterized in that: the output terminal of described second linear amplifier (OP82) can substitute for being connected with the source electrode (S) of a transistor (MN21), and the drain electrode (D) of described transistor (MN21) is connected with the grid (G) of self and is connected with the drain electrode (D) of a transistor (MP21), the source electrode (S) of described transistor (MP21) is connected with power supply (V0), and its grid (G) connects a bias line (BP);
One transistor (MN22), the source electrode (S) of described transistor (MN22) is connected with above-mentioned output line (80), its grid (G) is connected with the grid (G) of above-mentioned transistor (MN21), and the drain electrode (D) of described transistor (MN22) is connected with the drain electrode (D) of a transistor (MP22), the source electrode (S) of described transistor (MP22) is connected with power supply (V0), and its grid (G) is the same as being connected to a bias line (BP) with the grid (G) of above-mentioned transistor (MP21);
One transistor (MP23), the drain electrode (D) of described transistor (MP23) is connected with above-mentioned output line (80), its grid (G) is connected with drain electrode (D) junction of transistor (MP22) with the drain electrode (D) of above-mentioned transistor (MN22), and its source electrode (S) is connected with power supply (V0).
5. voltage stabilizing offset-type follower according to claim 4 is characterized in that described transistor (MN21) and transistor (MN22) are that matrix is that the metal oxide semiconductor field effect of negative ion structure is answered transistor.
6. voltage stabilizing offset-type follower according to claim 4 is characterized in that described transistor (MP21), transistor (MP22) and transistor (MP23) are that matrix is that the metal oxide semiconductor field effect of positive ion structure is answered transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101153097A CN100365693C (en) | 2003-11-14 | 2003-11-14 | Voltage stabilizing compensating type follower |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101153097A CN100365693C (en) | 2003-11-14 | 2003-11-14 | Voltage stabilizing compensating type follower |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1617212A true CN1617212A (en) | 2005-05-18 |
| CN100365693C CN100365693C (en) | 2008-01-30 |
Family
ID=34760387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101153097A Expired - Fee Related CN100365693C (en) | 2003-11-14 | 2003-11-14 | Voltage stabilizing compensating type follower |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100365693C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783593B (en) * | 2009-12-31 | 2013-01-16 | 上海三基电子工业有限公司 | Numerical control high voltage power supply with automatic linearity compensation |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3813463B2 (en) * | 2000-07-24 | 2006-08-23 | シャープ株式会社 | Drive circuit for liquid crystal display device, liquid crystal display device using the same, and electronic equipment using the liquid crystal display device |
| JP2002312043A (en) * | 2001-04-10 | 2002-10-25 | Ricoh Co Ltd | Voltage regulator |
| DE10160098A1 (en) * | 2001-12-07 | 2003-06-18 | Koninkl Philips Electronics Nv | Arrangement for controlling a display device |
-
2003
- 2003-11-14 CN CNB2003101153097A patent/CN100365693C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783593B (en) * | 2009-12-31 | 2013-01-16 | 上海三基电子工业有限公司 | Numerical control high voltage power supply with automatic linearity compensation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100365693C (en) | 2008-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1109403C (en) | Logic circuit | |
| CN1311631C (en) | High-frequency switched circuit | |
| JP4804142B2 (en) | High-speed gate drive circuit | |
| CN1237040A (en) | Logic circuit having reduced power consumption | |
| CN1671049A (en) | Drive circuit for voltage driven type semiconductor element | |
| CN1497840A (en) | Buffer circuit and driver IC | |
| CN1485810A (en) | Rotating transfer mechanism and zooming camera having the same | |
| CN1918794A (en) | Differential driving circuit and electronic equipment including the same | |
| CN1841933A (en) | Voltage level converter circuit and semiconductor integrated circuit device | |
| CN1926491A (en) | Reference voltage generating circuit | |
| CN1716445A (en) | Semiconductor memory device and semiconductor integrated circuit | |
| CN1780124A (en) | Semiconductor device | |
| CN1812263A (en) | Buffer circuit and integrated circuit | |
| CN1773705A (en) | MOS transistor circuit | |
| CN103944361A (en) | Field effect transistor high-speed drive circuit high in power and resistant to interference | |
| CN1266838C (en) | Semiconductor integrated circuit device capable of generating stably constant current under low power voltage | |
| CN1258878C (en) | Amplitude converting circuit | |
| CN1932953A (en) | Display driving circuit | |
| CN1773859A (en) | Semiconductor integrated circuit device and method for producing the same | |
| CN2886917Y (en) | Temperature compensation circuit | |
| CN1909232A (en) | Semiconductor integrated circuit | |
| CN1573637A (en) | Power supply circuit | |
| CN203722596U (en) | A high-frequency anti-interference MOS tube negative voltage driving circuit | |
| CN1713521A (en) | Differential amplifier circuit and method for controlling base bais voltage of differential amplifier circuit | |
| CN1617212A (en) | Voltage stabilizing compensating type follower |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080130 Termination date: 20091214 |