CN1591180A - Mask mfg. method - Google Patents
Mask mfg. method Download PDFInfo
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- CN1591180A CN1591180A CN 03150650 CN03150650A CN1591180A CN 1591180 A CN1591180 A CN 1591180A CN 03150650 CN03150650 CN 03150650 CN 03150650 A CN03150650 A CN 03150650A CN 1591180 A CN1591180 A CN 1591180A
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Abstract
The present invention discloses a mask plate production method by using electronic beam exposure. Said method includes the following steps: providing an earthed mask plate substrate; on the described substrate coating resist; using electronic beam to expose several registration mark patterns and current tube core patterns on the described substrate; using electronic beam to expose other patterns on the described substrate except for the above-mentioned patterns; removing resist exposed by electronic beam; etching the substrate portion which is not covered by resist and forming mask pattern on the substrate; and removing residual resist from substrate.
Description
Technical field
A kind of method for producing mask of relate generally to of the present invention relates more specifically to a kind of method for producing mask that exposes with electron beam.
Background technology
The mask that is used for the IC manufacturing is generally the mask of dwindling several times.The electron beam graph exposure is mainly used in the making of mask.The first step of mask manufacturing is circuit diagram intactly to be depicted with computer-aided design (CAD) (CAD) system by circuit designers.Then, the data message that CAD is obtained is sent to the pattern generator of electron beam image exposure.After this, again design transfer on the mask that is coated with the material of electron beam sensitive.Mask is generally formed by covering one deck chromium film on melting at the bottom of the silica-base of coagulating.Circuit pattern is at first transferred to the electronics sensitive layer, and then transfers to the chromium rete under it, and the making of mask has just been finished.
One group of complete IC technological process generally comprises nearly 15 to 20 different mask.Figure on each mask is represented one deck IC design, and for example isolated area is that one deck, gate regions are one deck etc.For the pattern that the employed mask of different flow processs is produced can align, need utilize the alignment mark of making on the mask.And align for the circuit pattern itself that guarantees to make on each layer mask, that is to say that the pattern that produces with original circuit design is corresponding, also need on each layer mask, make register mark, utilize the mask self that this mark assurance is dispatched from the factory to align, its registration error meets designing requirement.
In the process of utilizing electron beam exposure making mask, need on the resist surface, carry out electron beam scanning, in this process, because the fluctuation in the charging of electron beam focalizer, the external electrical field, the effects such as charging (resist charging) effect of mask substrate, the position of electron beam exposure may be offset, and the pattern that causes producing has error.The position of the register mark of each layer mask also is offset if be used to align, and then must cause the alignment of reticle pattern bigger error to occur.Since register mark generally be designed to be positioned at circuit pattern around, thereby a part wherein is relatively near the alignment pattern of mask periphery.
Because the scan characteristic of electron beam, when pattern is used in the peripheral alignment of exposure, have apparent in view charge effects, the electric charge of assembling on the mask surface can not very fast release, so when the exposure register mark, high energy electron in the electric charge of accumulation and the exposure electron beam interacts, and can cause register mark bigger error to occur, influences the quality of mask.If the area that the generation alignment pattern will be exposed is bigger, when for example using negative resist, then charge effects be can not ignore especially to the influence of registration error.
Summary of the invention
Consider the problems referred to above, the purpose of this invention is to provide and to reduce because of in the electron beam scanning process mask method for making of the registration error that the charge effects of mask substrate causes.This method comprises the steps:
The mask substrate of a ground connection is provided; In described substrate, apply resist; With described suprabasil a plurality of register mark patterns of electron beam exposure and circuit die pattern; Other patterns except that above-mentioned pattern that will make on the mask of electron beam exposure; Removal is by the resist of electron beam exposure; The base part that corrosion is not covered by resist forms mask pattern in substrate; Remove remaining resist in the substrate.
The method of stating is in the use made in the process of mask, can carry out baking processing to it after applying resist, can increase the adhesive property of resist and mask substrate.
The method of stating is in the use made in the process of mask, can after removing by the resist of electron beam exposure the resist pattern be toasted, and improves the adhesiveness of itself and mask substrate.
Make in the process of mask to state method in the use, the substrate of used mask substrate can be to melt tripoli with fixed attention, covers the chromium film on it.This is smaller because melt the thermal expansivity that coagulates tripoli, and is higher to short wavelength's optical transmission rate, and its physical strength is also higher simultaneously.The parameters such as imaging ratio of the size of the lens photic zone in the exposure machine of the mask that the size of mask is made by use and 4: 1 or 5: 1 are determined.Mask has certain thickness, thereby avoids substrate distortion and cause the error of pattern.
Used resist is the polymkeric substance to electron beam sensitive in this mask method for making.Use electron beam exposure to make mask and will use electron sensitive resist.Electron sensitive resist is a kind of polymkeric substance, and its character and general optics use resist similar, also are divided into positive corrosion-resisting agent and negative resist.For positive corrosion-resisting agent, constitute the polymkeric substance of resist and the destruction that the interaction between the electronics causes chemical bond, thereby form short molecular structure, cause the resist molecular weight of electron beam irradiation area to diminish, in ensuing developing process, dissolve because of the developer solution intrusion.Positive corrosion-resisting agent commonly used has PMMA (poly-methyl acrylate) and PBS.The resolution of positive electronic bundle resist can reach 0.1um or littler.For negative resist, the electron beam irradiation makes crosslinked polymer together, causes producing complicated three-dimensional structure at the electron beam irradiated region, and the non-irradiated region of the molecular weight ratio of this polymkeric substance is big.Like this, the resist of non-irradiated region can be dissolved in the developer solution, and developer solution can not corrode the high molecular resist that irradiation forms through electron beam.COP is a kind of negative resist commonly used.
In this mask method for making, electron beam carries out vector mode scanning on the mask surface.The scan mode of focused beam mainly is divided into two kinds of forms: sequential scanning and vector scan.In sequential scan system, the resist pattern utilize electron beam regularly vertical moving depict, in scanning process, any Probability Area on the electron beam sequential scanning mask is not needing exposed areas then in time to close.And in the vector scan mode, electron beam only is directed into the pattern place that needs, and electron beam does not need sequentially to scan the entire chip area when a pattern jumps to the another one pattern.The vector scan mode can be saved the time shutter greatly.
In this mask method for making, be around chip design and registration pattern, promptly the mask periphery is made the alignment pattern, and they are used for the pattern at each layer mask that the design transfer on the mask is alignd to wafer the time.
In this mask method for making, a plurality of register marks are distributed in around the described circuit die pattern.
In this mask method for making, alignment pattern is the pre-align pattern according to the standard design of ASML company.For example, if the mask made is used for the exposure desk that Dutch ASML company produces, then should on mask, make the pre-align pattern of its use according to the request for utilization of the exposure desk of the said firm.The shape of pattern, size and the position on mask should meet the code requirement that ASML company is provided fully.
With respect to conventional art, utilize the present invention to obtain a lot of benefits.Use the present invention, can reduce the registration error of mask.In certain embodiments, can reduce registration error over halfly, help to reduce the total error in the mask fabrication process, thereby help improving the productive rate that mask is produced.
Below with reference to the accompanying drawings, in conjunction with the embodiments, describe the present invention, make that purpose of the present invention, feature and beneficial effect are more obvious.
Description of drawings
Fig. 1 is the process flow diagram of mask method for making according to an embodiment of the invention.
Fig. 2 is the distributing position of explanation register mark on mask and the synoptic diagram of the cause of charge effects.
Fig. 3 illustrates the part of the mask that comprises pre-align mark and register mark.
Fig. 4 illustrates the alignment mark of making when using negative resist.
Fig. 5 A is the situation that register mark that traditional mask method for making is made departs from from the precalculated position.
The situation that Fig. 5 B is to use the register mark on the mask that method of the present invention makes to depart from from the precalculated position.
Embodiment
A lot of details have been set forth below in the detailed description of the present invention, so that fully understand the present invention.But, there are not these details can implement the present invention yet, be clearly for a person skilled in the art.Known method, process etc. is not described in detail, and a presumptuous guest usurps the role of the host to avoid, desalinated main contents of the present invention.
1 describe at first, in conjunction with the accompanying drawings to 4 pairs of one embodiment of the present of invention of accompanying drawing.Accompanying drawing 1 is the process flow diagram of mask method for making according to an embodiment of the invention.Manufacturing process is from step 100.In step 102, provide a substrate that is used to make mask.In a preferred embodiment, tripoli covers one deck chromium film as substrate on it to melt with fixed attention in substrate.Fig. 2 shows the upper left of mask substrate.Making in the process of mask of electron beam exposure, this substrate should ground connection.Can see in Fig. 2, be not that whole melting with fixed attention all covered the chromium film on the tripoli substrate, and the upper left corner of substrate does not use the chromium film to cover.
Then, in step 104, in the mask substrate that is provided, apply the resist that electron beam exposure is used.General adopt rotary process with resist-coating to the mask substrate.Its principle is to utilize the centrifugal force that produces when rotating, and will drop in suprabasil resist and throw away, under the centrifugal force acting in conjunction of resist surface tension and rotation, is extended to the uniform resist film of thickness.The thickness of film should be taken into account the requirement of two aspects of defect concentration on resolution and the substrate surface.It should be noted that before applying resist in the substrate, should guarantee the substrate cleaning, for example, can adopt ultrasonic cleaning and abundant, be bonded on the substrate surface to prevent foreign matter through freon gas.
In another preferred embodiment of the present invention, baking processing has also further been carried out in the mask substrate that has applied resist.The purpose of doing like this is to make the resist sufficiently dry, thereby increases and the viscosity of substrate.Toast thickness and anticorrosive additive material that used temperature and time depends on the resist film.
Then, in step 106, begin with electron beam exposure register mark and circuit die pattern.The pattern generator of electron beam image exposure is used to control the information of focused beam at the scanning motion of mask substrate surface according to the layout patterns generation of the circuit that circuit designers is designed, for example, these information can be the computer instructions of controlling electron beam polarization etc.In the present embodiment, the control focused beam scans on the mask surface, at first expose register mark pattern A part and circuit die pattern B part, as shown in Figure 3.
Then, in step 108, control focused beam, other patterns in the described substrate that exposes except that above-mentioned pattern.As shown in Figures 2 and 3, these patterns are distributed in around register mark pattern and the circuit die pattern in the mask substrate, are positioned at the more outer part of enclosing of mask substrate.In a preferred embodiment of the invention, be distributed in and comprise alignment pattern used when on wafer, exposing resist in the pattern of mask periphery with mask.For example, produce, then need on mask, produce the alignment pattern that meets the said firm's standard, as shown in Figure 4 if used exposure stage is an ASML company.
After exposure is finished,, remove by the resist of electron beam exposure in step 110, or be called resist developed after, expose the mask substrate that is not covered by resist.In step 112, the base part with chemical mordant or plasma etching are not covered by resist forms mask pattern in substrate then.In a preferred embodiment of the invention, after resist develops, remaining resist in the substrate is handled, for example baking, thereby improve resist and the bonding of base material and the corrosion resistivity of resist, prevent contingent eating thrown phenomenon in corrosion process.
At last,, remove remaining resist in the substrate, obtain the mask of figure in step 114.
The occasion that is particularly suitable for adopting negative resist with the mask manufacture method method of electron beam exposure provided by the present invention.Fig. 4 shows when using negative resist, according to the standard of ASML company, and the pre-align pattern that need in the mask substrate, make.Because what use is negative resist, so in order to obtain the pre-align mark, must carry out electron beam exposure to the square area of 8.5mm * 8.5mm size on mask.Fig. 3 shows the relative position relation of this pre-align mark C and register mark B.As can be seen from Figure 3, when using negative resist,, therefore, in the process of using electron beam exposure, may produce the accumulation of electric charge in this zone owing to need exposed areas to be far longer than the size of pre-align mark.If use traditional exposure method, for example, electron beam scans left to bottom right from the mask substrate, because pre-align is marked at the outside of register mark, then in this exposure process, the zone that produces the pre-align mark must at first be exposed.Then, electron beam exposure register mark.Because the electric charge accumulation is arranged in the zone that produces the pre-align mark, and should the zone and to produce the zone of register mark more approaching, so the electric charge of these accumulation might interact with the intrafascicular electronics of focused electron, cause the exposure position of register mark to produce error.But in method provided by the present invention, register mark and die pattern are at first exposed, so the exposure of register mark can not be subjected to the influence (charge effects) of electric charge of exposure accumulation of other patterns of mask periphery, thereby can reduce alignment error relatively, and then reduce the total error in the mask manufacture process.
Fig. 5 A is the situation that register mark that traditional mask method for making is made departs from from the precalculated position.The situation that Fig. 5 B is to use the register mark on the mask that method of the present invention makes to depart from from the precalculated position.In Fig. 5 A and Fig. 5 B, the size and Orientation of the length of arrow and the skew of direction indication register mark.
Following table 1 has provided the mean deviation situation of each register mark among Fig. 5 A.The result who provides is the arithmetic mean of each point measurement result.
Table 1
| Directions X (um) | Y direction (um) | |
| Smallest offset | ????-0.036 | ????-0.022 |
| Peak excursion | ????0.038 | ????-0.029 |
Following table 2 has provided the mean deviation situation of each register mark among Fig. 5 B.
Table 2
| Directions X (um) | Y direction (um) | |
| Smallest offset | ????-0.022 | ????-0.019 |
| Peak excursion | ????0.017 | ????0.015 |
From table 1 and table 2 as can be seen, use electron beam exposure method provided by the present invention after, register mark about the absolute value of the peak excursion on directions X and the Y direction all is reduced to original half, thereby help to reduce the error of system.
Though described illustrative of the present invention and preferred embodiment now here in detail; but should be appreciated that inventive concept can be carried out multiple specializing and use, the various modifications and variations of doing according to spirit of the present invention all belong to appended protection domain as claim.
Claims (11)
1. mask manufacture method with electron beam exposure comprises step:
The mask substrate of a ground connection is provided;
In described substrate, apply resist;
With described suprabasil a plurality of register mark patterns of electron beam exposure and circuit die pattern;
With other patterns except that above-mentioned pattern in the described substrate of electron beam exposure;
Resist is developed;
The base part that corrosion is not covered by resist forms mask pattern in substrate;
Remove remaining resist in the substrate.
2. the method for claim 1 also is included in after the coating resist, and it is carried out baking processing.
3. method as claimed in claim 2, also be included in resist developed after, the resist pattern is toasted, improve the adhesiveness of itself and mask substrate.
4. as claim 1,2 or 3 described methods, wherein, the substrate of described mask is to melt tripoli with fixed attention, is the chromium film on it.
5. as claim 1,2 or 3 described methods, wherein, described resist is the polymkeric substance to electron beam sensitive.
6. as claim 1,2 or 3 described methods, wherein, in the exposure process, the scan mode of electron beam is a vector scan.
7. as claim 1,2 or 3 described methods, wherein, described resist is a negative resist.
8. as claim 1,2 or 3 described methods, wherein, described resist is positive resist.
9. method as claimed in claim 7, wherein, described other patterns comprise the pre-align pattern at least.
10. method as claimed in claim 7, wherein, described a plurality of register marks are distributed in around the described circuit die pattern.
11. method as claimed in claim 9, wherein, described alignment pattern is the pre-align pattern according to the standard design of ASML company.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03150650 CN1248049C (en) | 2003-08-29 | 2003-08-29 | Mask mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03150650 CN1248049C (en) | 2003-08-29 | 2003-08-29 | Mask mfg. method |
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| Publication Number | Publication Date |
|---|---|
| CN1591180A true CN1591180A (en) | 2005-03-09 |
| CN1248049C CN1248049C (en) | 2006-03-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03150650 Expired - Lifetime CN1248049C (en) | 2003-08-29 | 2003-08-29 | Mask mfg. method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394306C (en) * | 2005-04-04 | 2008-06-11 | 中国科学院微电子研究所 | Prepn process of exposure registering mark for mixing and matching between electron beam and optical device |
| CN101382742B (en) * | 2008-10-15 | 2011-10-05 | 清溢精密光电（深圳）有限公司 | Developing method for mask plate |
| US8748313B2 (en) | 2009-10-23 | 2014-06-10 | Semiconductor Manufaturing International (Shanghai) Corporation | Electroforming technique for mask formation |
| CN104635994A (en) * | 2015-03-17 | 2015-05-20 | 蚌埠玻璃工业设计研究院 | Method for manufacturing touch screen metal pattern |
| CN108073035A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of restorative procedure of lithography mask version and lithography mask version defect |
-
2003
- 2003-08-29 CN CN 03150650 patent/CN1248049C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394306C (en) * | 2005-04-04 | 2008-06-11 | 中国科学院微电子研究所 | Prepn process of exposure registering mark for mixing and matching between electron beam and optical device |
| CN101382742B (en) * | 2008-10-15 | 2011-10-05 | 清溢精密光电（深圳）有限公司 | Developing method for mask plate |
| US8748313B2 (en) | 2009-10-23 | 2014-06-10 | Semiconductor Manufaturing International (Shanghai) Corporation | Electroforming technique for mask formation |
| CN104635994A (en) * | 2015-03-17 | 2015-05-20 | 蚌埠玻璃工业设计研究院 | Method for manufacturing touch screen metal pattern |
| CN104635994B (en) * | 2015-03-17 | 2017-07-11 | 蚌埠玻璃工业设计研究院 | A kind of preparation method of touch-screen metallic pattern |
| CN108073035A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of restorative procedure of lithography mask version and lithography mask version defect |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1248049C (en) | 2006-03-29 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111202 |
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Effective date of registration: 20111202 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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Granted publication date: 20060329 |
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