CN1567215A - Low powered backup and repair structure of static random access memory - Google Patents
Low powered backup and repair structure of static random access memory Download PDFInfo
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- CN1567215A CN1567215A CN 03142973 CN03142973A CN1567215A CN 1567215 A CN1567215 A CN 1567215A CN 03142973 CN03142973 CN 03142973 CN 03142973 A CN03142973 A CN 03142973A CN 1567215 A CN1567215 A CN 1567215A
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Abstract
It is a kind of static random memory (SRAM) cell power structure. The structure can reduce the power that caused by fault memory cell, as well as reduce the power of whole chip. It controls the circuit from VSS to 6-transistor by NMOS transistor. The VSSEN circuit can decode and check the fault region. So under the normal interval, VSSEN signal can close NMOS transistor to cut VSS circuit and disable a fault cell or region cell. Or under the backup interval, VSSEN signal can open NMOS transistor so to access the VSS path and enable a backup cell or region cell.
Description
Technical field
(Static Random Access Memory SRAM), refers to a kind of SRAM memory location power structure especially to the invention relates to a kind of SRAM.
Technical background
The main design of SRAM all is towards memory body being displayed minimum power that memory location (cell) consumed and effort.At present existing many kinds of solutions are suggested, and comprise the power that is consumed by reduction failure memory body memory location, and then reduce the power that entire chip consumed.
United States Patent (USP) case numbers 5,703,816 provide a kind of method, and this method is before encapsulation, spare row (redundant columns) by the memory body memory location replaces failed row (failed columns), with the electric current of awaiting orders (standby current) that is reduced in fault memory location among the SRAM.This patent case provides a kind of device, and this device can be closed supply of current and be given the bit line right to precharge (precharge) the circuit electric crystal of (bit line pair), and the memory location power lead circuit that can close memory body memory location display failed row.
United States Patent (USP) case numbers 6,175,938 has disclosed the structure of a kind of reduction by the caused electric current of awaiting orders of processing procedure flaw.After standby memory location replaces the fault memory location, each bit line V
DDPolysilicon on the path (polysilicon) fuse can open circuit, to reduce the electric current of awaiting orders of fault memory location.
United States Patent (USP) case numbers 6,097,647 has disclosed a kind of method, and this method is to utilize electrically isolated mode, with memory body memory location and the power lead and the ground wire cut-out of having no idea to repair.This method also can make normally functioning memory body store the grid display and work on, and eliminate the failure memory body memory location the many electric current of additionally awaiting orders.
These lower powered memory body display memory locations are by static complementary metal oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) flip-flop (flip-flop) circuit constitutes, and uses a pair of phase inverter that intercouples to be used as storage unit.The CMOS flip-flop is actually in the extreme little in static power consumption, and main consumption is caused by the contact leakage current.Comprise in the circuit of memory body display memory location at this, the consumption of power is very crucial.For lower powered specification, some fault memory locations exceed with regard to being enough to produce enough big electric current this chip power requirements.
Therefore need a kind of mechanism, this mechanism can reduce the power of leakage current and entire chip by this with the optionally decapacitation of memory location of fault.
Summary of the invention
Fundamental purpose of the present invention provides and a kind ofly effectively fault electric current that memory location causes in the low power SRAM display is dropped to minimum mechanism.
Secondary objective of the present invention provides a kind of device, and this device can be used to detect the existence that in the SRAM memory body which memory location or the memory location in which district have leakage path.In order to achieve the above object, the invention provides a kind of SRAM memory body memory location with a backup repair structure.In this structure, SRAM memory body memory location is connected to a high reference voltage and a low reference voltage, and has one and cut off device, can cut off being connected between low reference voltage and SRAM memory body memory location.
The present invention also provides the method for the leakage current that a kind of reduction produced by fault memory location in the SRAM display, and this method includes following steps:
A: a plurality of SRAM memory body memory locations in the SRAM display are connected to a high reference voltage and a low reference voltage;
Whether b: testing this SRAM display has the fault memory location;
C: replace this fault memory location by normal backup memory location; And
D: the low reference voltage of cut-out is connected with this fault memory location, uses the leakage current of reduction from this fault memory location, makes chip overall power structure constant.
Should be controlled by an activation signal (VSSEN) in low reference voltage path, this enable signal is used for completely cutting off the fault memory location under the specified condition of array test.This enable signal also is used for decoding which memory body memory location in low power SRAM or which district's memory location is enabled (enabled), and which fault memory location is cut off connection.The disengagement failure memory location leads to the path of low reference voltage, and replace the fault memory location with normal backup memory location and can lower the power that is produced by the fault memory location, and the backup memory location of fault also can be reduced the electric current and the power of chip by this by decapacitation (disabled).Via this method, leakage current is minimized, and then reduce the power that entire chip consumed.
As for detailed construction of the present invention, application principle, effect and effect, then the explanation of doing with reference to following accompanying drawing can be understood completely:
Description of drawings
Fig. 1 is six electric crystals (6T) the SRAM memory location structure of a standard in the prior art;
Fig. 2 is six electric crystal SRAM memory location structures of the present invention, wherein the enable signal (VSSEN) of subsidiary one low reference voltage
Fig. 3 is a calcspar, and this low reference voltage enable signal (VSSEN) of how decoding is described, with the fault memory location in the decapacitation normal storage lattice district, and activation is used for replacing the memory location of this fault memory location in standby memory location district;
Fig. 4 be expression to the normal memory body memory location in the low power SRAM, activation/decapacitation steering logic is the circuit diagram of execution how;
Fig. 5 be expression to the backup memory body memory location in the low power SRAM, activation/decapacitation steering logic is the circuit diagram of execution how;
Fig. 6 is how a plurality of memory body memory locations of illustration are connected to low reference voltage enable signal (VSSEN);
Fig. 7 is an operational flowchart of the present invention.
Embodiment
See also Fig. 1, this is a standard six electric crystal SRAM memory locations.Concerning the ultra low power SRAM of a 8M bit capacity, (word line, when WL) closing, the electric current of awaiting orders of memory body memory location is less than 20 micromicroamperes under 85 ℃, and the electric current of awaiting orders when room temperature is between 1 to 2 micromicroampere approximately when its word group line.
Access device N3 and N4 provide a convertible path to data turnover memory location.Except reading or writing, it all is the state that remains on electronegative potential usually that word group line WL chooses signal.Two character line BL, BLB then provide this data path.The selection of word group line and bit line is to finish by demoder.Suppose that left side that the logical one of being deposited is defined as flip-flop is in the state of noble potential, that is to say that N2 is a closing state.
The running program of the memory body memory location of Fig. 1 is as follows: this word group line WL is the state at electronegative potential when armed state, when receiving high reference voltage, N4 and N3 is opened.One of them is a low-potential state to force bit line BL or BLB, and another bit line is still kept high potential state simultaneously, to finish write activity.For instance, write a logical one, bit line BLB is forced to into the state of electronegative potential.This memory body memory location is designed so that the drain of N1 and the gate of N2 can bring under the critical voltage (threshold voltage).So N2 closes, and the drain voltage of N2 is because electric current flows to N4 and rises from P2; N1 opens, and word group line WL can be returned to the usual electronegative potential of awaiting orders, and the memory body memory location writes " 1 " simultaneously.
See also Fig. 2, it is six electric crystal SRAM memory location structures of the present invention, wherein the enable signal (VSSEN) of subsidiary one low reference voltage.When the memory body memory location has not detected fault therein the time, VSSEN just remains on noble potential, and its included NMOS electric crystal is in conducting state; And, read a logical one with this memory location activation, bit line is being the high potential state that is under the high reference voltage (VCC) at the beginning to BLB, BL.Elected when reserving the memory body memory location, to hanging down reference voltage (VSS), and flow through P12 and N14 are to character line BL via N11 and N13 for electric current.The state that the N11 maintenance is opened.Read a logical zero, elected when reserving the memory body memory location, to low reference voltage VSS, and stream process P11 and N13 are to character line BLB via N12 and N14 for electric current.The state that the N12 maintenance is opened.When having detected fault in the memory body memory location time, VSSEN just becomes the state of electronegative potential, and its NMOS electric crystal just becomes nonconducting state, and with memory location decapacitation from memory body.
After memory body is manufactured, can whether there be the test of any fault memory location usually.Prior art requires whole son displays (sub array) is all gone to detect.If in test, a memory body memory location or the memory location in a district has been detected fault, whole son displays all can be replaced.The present invention then can narrow down to scope on the bit line in the trip, just have only a bit line to guild deleted.See also Fig. 3, how its explanation carries out the decoding action of VSSEN.Signal EN is the output of steering logic 10, and is connected to drain (drain) end points of device 14.Signal TMEN is the output of demoder 12, and is connected to the drain end points of device 18.Signal TESTMODE is the output of phase inverter 16, and the output of this phase inverter 16 is connected to device 14 and installs 18 gate (gate) end points.Device 14 and install 18 source electrode (source) end points and be connected to signal VSSEN.When detecting electric current when exceeding default current specification, if should display memory location in the interval of normal storage lattice, just with the replacement of backup memory location; And if this display memory location is in standby memory location interval, with regard to this memory location of decapacitation.In normal storage lattice interval, signal EN is except this memory location is replaced by a standby memory location, other the time be to be in the state of noble potential.In the interval of standby memory location, signal EN except this memory location is used to replace a fault memory location, other the time be to be in the state of electronegative potential.
See also Fig. 4 and Fig. 5, this two figure represents respectively how fuse is used for setting the high electronegative potential of OUTB and OUT, thereby sets the high electronegative potential of signal EN among the figure three.If Fig. 4 represents the memory location in the normal storage lattice interval fault is arranged, fuse 26 will be burnt, make this memory location decapacitation, just make VSSEN be in electronegative potential.EN (is OUTB to normal memory location) is the output of phase inverter 24, also is device 22 gates simultaneously.If this memory location is the fault memory location, interrupt the fuse 26 that is connected to device 20 and installs 22 source electrode, make by the anti-phase EN that becomes of the INITIALB of phase inverter 24.Fig. 5 represents to burn fuse 29 makes this memory location activation, just makes VSSEN be in the situation of noble potential, standby memory location can be replaced normal memory location.EN (is OUT to standby memory location) is the output of phase inverter 27.The input of phase inverter 27 is the output of phase inverter 25, also is the gate end points of device 23 simultaneously, if this memory location will be used, the fuse 29 that is connected to device 21 and installs 23 source electrode just makes INITIALB by becoming EN.According to above mode, the display memory location that does not have to use can be by decapacitation, so can any influence not arranged to the electric current of awaiting orders.Prior art requires to cut off VDD and two power supply feed lines of VSS.If but use method of the present invention, and as long as cut off VSS power supply feed lines, just only needing fewer electric crystal, the cost of the consumed power of chip and circuit design just can reduce to minimum by this.
See also Fig. 6, find a fault memory location if this figure shows, the memory location that comprises this fault memory location is capable just deleted from display, and it is capable to add a normal standby memory location then.In this method, it is capable that low reference voltage enable signal (VSSEN) is connected to each memory body memory location, just 30 arrives n0, makes the present invention more simpler than prior art.
Please refer to Fig. 7, it is an operational flowchart of the present invention.According to the present invention, this method may further comprise the steps, and 40: provide the SRAM of a SRAM memory location display, and each memory location all is connected to a high reference voltage and a low reference voltage;
42: detect this SRAM and whether display the defectiveness memory location;
44: replace the fault memory location by normal standby memory location;
46:, low reference voltage path is cut off with the decapacitation of fault memory location.
So the leakage current of fault memory location is lowered, do not influence the power supply architecture of chip other parts simultaneously yet.
But the above for a preferred embodiment of invention, is not to be used for limiting scope of the invention process only.Be that the equalization that all the present patent application claims are done changes and modification, be all the contained lid of claim of the present invention.
The figure number explanation
WL: word group line
BL, BLB: bit line pair
N1-N4, P1, P2: electric crystal
N11-N14, P11, P12: electric crystal
10 control logics
12 decoders
14 electric crystal devices (cmos switch)
16 phase inverters
18 electric crystal devices (cmos switch)
20 electric crystal devices
22 electric crystal devices
24 phase inverters
26 fuses
21 electric crystal devices
23 electric crystal devices
25 phase inverters
27 phase inverters
29 fuses
30-n0 memory body memory location is capable
40-46 operational flowchart of the present invention
Claims (16)
1. one kind has the SRAM memory body memory location that backs up repair structure, includes:
One is connected to the SRAM memory body memory location of a high reference voltage and a low reference voltage; And
One cuts off device, can cut off being connected between this low reference voltage and this SRAM memory body memory location.
2. the SRAM memory body memory location that the backup repair structure is arranged as claimed in claim 1, it is characterized in that: described shearing device is VSS activation (VSSEN) circuit that comprises N type complementary metal oxide semiconductor (NMOS) electric crystal.
3. the SRAM memory body memory location that the backup repair structure is arranged as claimed in claim 1 is characterized in that: described shearing device can cut off being connected between low reference voltage and SRAM memory body memory location, to reduce the leakage current from this memory location.
4. the SRAM memory body memory location that the backup repair structure is arranged as claimed in claim 1 is characterized in that: described shearing device can be selected activation or decapacitation one display memory location district according to the result of detecting fault memory location.
5. one kind has the SRAM of backup repair structure to display, and includes:
A plurality of SRAM memory body memory locations that are connected to a high reference voltage and a low reference voltage; And one cut off device, can cut off wherein one or more be connected of this low reference voltage and this SRAM memory body memory location.
6. the SRAM display that the backup repair structure is arranged as claimed in claim 5, it is characterized in that: described shearing device is VSS activation (VSSEN) circuit that comprises N type complementary metal oxide semiconductor (NMOS) electric crystal.
7. the SRAM display that the backup repair structure is arranged as claimed in claim 5, it is characterized in that: described shearing device can be used to cut off being connected between those memory locations of this low reference voltage and delegation or multirow, to reduce the leakage current that comes from this row or multirow memory location.
8. the SRAM display that the backup repair structure is arranged as claimed in claim 5 is characterized in that: described shearing device can be selected activation or decapacitation one display memory location district according to the result of detecting fault memory location.
9. method that lowers the caused leakage current of failure memory body display memory location in the SRAM display may further comprise the steps:
A: a plurality of SRAM memory locations in the SRAM display are connected to a high reference voltage and a low reference voltage;
Whether b: testing this SRAM display has the fault memory location;
C: replace this fault memory location with normal backup memory location; And
D:,, make chip overall power structure constant to reduce leakage current from this fault memory location by low this fault memory location of reference voltage decapacitation.
10. the method for the caused leakage current of failure memory body display memory location in the attenuating as claimed in claim 9 SRAM display, it is characterized in that: a described test pattern enable signal TMEN is decoded, and is used for the tested memory location of activation.
11. the method for the caused leakage current of failure memory body display memory location in the attenuating SRAM display as claimed in claim 9, it is characterized in that: a described test pattern enable signal TMEN decodes, and is used to measure the memory location magnitude of current in the test pattern.
12. the method for the caused leakage current of failure memory body display memory location in the attenuating SRAM display as claimed in claim 9, it is characterized in that: if the fault memory location is in normal interval, test mode signal TMEN is substituted the fault memory location.
13. the method for the caused leakage current of failure memory body display memory location in the attenuating SRAM display as claimed in claim 9, it is characterized in that: if the fault memory location is between backup area, test mode signal TMEN makes the decapacitation of fault memory location.
14. the method for the caused leakage current of failure memory body display memory location in the attenuating SRAM display as claimed in claim 9, it is characterized in that: if the fault memory location is in normal interval, the VSS enable signal makes the fault memory location by decapacitation.
15. the method for the caused leakage current of failure memory body display memory location in the attenuating SRAM display as claimed in claim 9 is characterized in that: if the memory location between backup area is used for replacing the fault memory location, the VSS enable signal is with regard to activation backup display memory location.
16. the method for the caused leakage current of failure memory body display memory location in the attenuating SRAM display as claimed in claim 9 is characterized in that: a described VSS enable signal is connected to delegation's memory body display memory location.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031429734A CN100462932C (en) | 2003-06-13 | 2003-06-13 | Low powered backup and repair structure of static random access memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031429734A CN100462932C (en) | 2003-06-13 | 2003-06-13 | Low powered backup and repair structure of static random access memory |
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| CN1567215A true CN1567215A (en) | 2005-01-19 |
| CN100462932C CN100462932C (en) | 2009-02-18 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409110B (en) * | 2007-11-21 | 2011-10-19 | 钰创科技股份有限公司 | Storage module for repairing defect storage unit cell and repairing method thereof |
| CN104620323A (en) * | 2012-09-13 | 2015-05-13 | 高通股份有限公司 | Reference cell repair scheme |
| CN105244060A (en) * | 2015-09-25 | 2016-01-13 | 北京兆易创新科技股份有限公司 | Chip based test processing method and apparatus |
| CN106021015A (en) * | 2015-03-24 | 2016-10-12 | 邱沥毅 | Non-volatile static random access memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204029A (en) * | 1995-01-23 | 1996-08-09 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| EP0821412B1 (en) * | 1996-06-17 | 2006-09-13 | United Microelectronics Corporation | Hemispherical-grained silicon top-gate electrode for improved soft-error immunity in SRAMs |
| JP2003060087A (en) * | 2001-08-10 | 2003-02-28 | Mitsubishi Electric Corp | Semiconductor memory |
-
2003
- 2003-06-13 CN CNB031429734A patent/CN100462932C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409110B (en) * | 2007-11-21 | 2011-10-19 | 钰创科技股份有限公司 | Storage module for repairing defect storage unit cell and repairing method thereof |
| CN104620323A (en) * | 2012-09-13 | 2015-05-13 | 高通股份有限公司 | Reference cell repair scheme |
| CN104620323B (en) * | 2012-09-13 | 2018-03-20 | 高通股份有限公司 | Reference unit recovery scenario |
| CN106021015A (en) * | 2015-03-24 | 2016-10-12 | 邱沥毅 | Non-volatile static random access memory |
| CN105244060A (en) * | 2015-09-25 | 2016-01-13 | 北京兆易创新科技股份有限公司 | Chip based test processing method and apparatus |
| CN105244060B (en) * | 2015-09-25 | 2019-01-01 | 北京兆易创新科技股份有限公司 | A kind of test processing method and device based on chip |
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| CN100462932C (en) | 2009-02-18 |
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