CN1560906A - Manufacturing method of nano-line on semiconductor material - Google Patents
Manufacturing method of nano-line on semiconductor material Download PDFInfo
- Publication number
- CN1560906A CN1560906A CNA2004100164629A CN200410016462A CN1560906A CN 1560906 A CN1560906 A CN 1560906A CN A2004100164629 A CNA2004100164629 A CN A2004100164629A CN 200410016462 A CN200410016462 A CN 200410016462A CN 1560906 A CN1560906 A CN 1560906A
- Authority
- CN
- China
- Prior art keywords
- silicon
- top layer
- diaphragm
- silica
- layer medium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Weting (AREA)
- Micromachines (AREA)
Abstract
The invention relates to a manufacturing method based on semi-conductor material nanometer line. It uses bird nozzle effect in semi-conductor process and wet corrosion or dry etching technology of the semi-conductor to produce lines with nanometer scale, it likes the rectangular or ladder cross section, and it can form protection film on the surface of the top media, carries on adulteration of boron, and phosphor. The method includes (1) using the SOI silicon plate on (100) or (110) crystal surface top; (2) using the SOI silicon plate and isotropy or wet/dry etching and corrosion technologies; (3) using the dry etching technology, then using the isotropy or anisotropy to corrode; (4) using the isotropy corrosion technology of the silicon, then using the dry etching technology to produce.
Description
Technical field
The present invention relates to a kind of manufacture method of monocrystalline silicon line of nanoscale, specifically, be a kind of " beak " effect and the wet etching of semi-conducting material or dry etching technology is processed nano wire on the semi-conducting material on the dielectric layer method of utilizing in the semiconductor technology.Belong to the micro-nano-technology field.
Background technology
Under the promotion of Highgrade integration tide, modern technologies will be more and more urgent to the demand of nanoscale function element.One-dimensional material such as nano wire, nanotube is as requisite functional unit in the nano-device, and it is important all the more that the status in the research in nanotechnology field seems.
In addition, in recent ten years, in the Condensed Matter Physics field, people are to low-dimensional, and the research of small scale material shows keen interest.Nanostructure is in the current scientific technological advance forward position, has challenging research field.Especially in recent years, the semi-conducting material line of nanoscale more and more is subject to people's attention.On the one hand, because its potential application prospect, such as: the semiconductor device miniaturization, improve integrated level, and be used to make some particular device etc.; On the other hand, because the special physical property that shows under miniature scale of semi-conducting material is such as skin effect, mechanics effect, the characteristics of luminescence and quantum scale effect etc. more and more are subjected to the attention of scientific circles.
Therefore, it is controlled to produce yardstick, and unified and standard nanowires of semiconductor material, becomes the target that people lay siege to.Since to utilize it to make nano electron device, thus its purity, and operability also becomes the key factor of weighing the nano wire quality.
With silicon materials the most frequently used in the semi-conducting material is example, the method of making silicon nanowires at present mainly contains three classes: the first kind is a chemical vapor deposition, physical vapor deposition, the method of growth such as laser ablation method and solid-liquid solid method, assisting down of catalyst, grow nanowire [(1) M.K.Sunkara randomly on large-area substrate, S.Sharma, R.Miranda, G.Lian and E.C.Dickey, Bulksynthesis of silicon nanowires using a low temperature vapor liquid solidmethod, Applied Physics letters, Vol.79, Num 10,3 September 2001; (2) Feng Sunqi, Yu Dapeng, Zhang Hongzhou, Bai Zhigang, fourth or, Hang Qingling, the Zou quintessence, Wang Jingjing, the growth mechanism of one dimension silicon nanowires and the research of quantum limitation effect thereof, Chinese science A collects, the 29th the volume, the 10th phase, 1999.10].The nano wire of working it out like this utilizes the whole bag of tricks that it is ridden on the electrode again, makes various nano-devices.Its shortcoming is to be difficult to operation and location, gives the extensive integrated difficulty of bringing, and the uniformity of purity and yardstick all can't well be guaranteed in addition.Second class is to use electron beam or focused ion beam directly to write [[3] Toshiyuki Toriyama, Daisuke Funai and SusumuSugiyama, Piezoresistance measurement on single crystal siliconnanowires, Journal of Applied Physics Vol.93, Num 11 January 2003].The shortcoming of these class methods is cost of manufacture costlinesses, also is unfavorable for producing in batches.The 3rd class is to utilize silicon materials self character or special silicon materials (for example silicon on the insulator (SOI)), take structural design and technology controlling and process cleverly, avoid the expensive of high accuracy photoetching process, produce satisfactory nano wire [[4] H.Namatsu, M.Nagase, K.Kurihara, K.lwadate and K.Murase, 10-nmSilicon Lines Fabricated in (110) Silicon, Microelectronic Engineering vol.27,71-74,1995; [5] Gen Hashiguchi and Hidenori Mimura, Fabrication ofSilicon Quantum Wires Using Separation by lmplanted Oxygen Wafer, Jpn.J.Appl.Phys, Vol.33, L1649-L1650,1994].These class methods have been utilized the advantage of the batch making of planar technique, can be compatible mutually with ripe semiconductor technology, and made silicon nanowires yardstick is controlled, and uniform specification is easy to realize array.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of based semiconductor material nano line.It mainly utilizes " beak " effect in the semiconductor technology (Bird ' s Break) and the wet etching of semi-conducting material or the lines of dry etching technology processing and preparing nanoscale on the semi-conducting material on the dielectric layer, the location accurately, technology is simple, is convenient to integrated.
The objective of the invention is to reach by the following method:
(1) semi-conducting material on the selection dielectric layer, as soi wafer, the silicon on the sapphire (SOS) etc. have top layer medium 1, intermediate medium 2 and substrate 3 above.
(2) optionally form diaphragm 4, shown in Fig. 1 (a) on the surface of top layer medium 1.
(3) remove not protected top layer medium 1, expose the front side wall 5 of the top layer medium 1 that is not removed, shown in Fig. 1 (b).
(4) form another layer diaphragm 6; front side wall 5 is protected; because the combination of diaphragm 4 and top layer medium 1 is not very tight, there is stress in its interface, so in the process that forms diaphragm 6; diaphragm 6 can be got between diaphragm 4 and the protected top layer medium 1; formation is similar to the structure of beak shape, promptly produces so-called " beak effect ", and this structure is a beak 7 by label in the present invention; its composition is identical with diaphragm 6, shown in Fig. 1 (c).
(5) remove residual diaphragm 4, keep diaphragm 6 and beak 7 simultaneously, shown in Fig. 1 (d).
(6) remove the not top layer medium 1 below diaphragm 6 and beak 7; the top layer medium 1 of diaphragm 6 and beak 7 belows can partly be remained simultaneously; its marginal portion forms rear wall 8; promptly form the nano wire 9 on the middle dielectric layer 2 between rear wall 8 and the front side wall 5; its composition is identical with top layer medium 1, shown in Fig. 1 (e).
On this basis, nano wire is carried out technology subtract carefully (for example oxidation etc.), obtain thinner nano wire.
As required, can remove the middle dielectric layer 2 of nano wire 9 belows, form unsettled nano wire 9 (shown in Fig. 1 (f)), perhaps before in above-mentioned steps (2), optionally top layer medium 1 material is mixed, can make the nano wire 9 of different conduction-types.The mode of mixing comprises diffusion and ion injection etc., and the type of doping comprises boron, phosphorus or other dopant material etc.
The anisotropic corrosion technique that manufacture method provided by the invention can be used for the soi wafer in (100), (110) crystal orientation and silicon is made approximate rectangular or trapezoid cross section silicon nanowire or utilize the isotropic etch of any crystal orientation soi wafer and silicon, the silicon nanowire that lithographic technique is made approximate rectangular cross section.
Compare with existing method, the method has following characteristics:
(1) utilize the intrinsic effect (beak effect) in the semiconductor technology to form mask, the autoregistration effect is arranged, good reliability greatly reduces the difficulty of photoetching process.
(2) the application semi-conducting material is extensive, by different corrosion technologies (wet method anisotropy burn into wet method isotropic etch, dry etching etc.), can make the silicon nanowires of different cross section shape or different trends at the monocrystalline silicon surface of (100) face, (110) face or any crystal face respectively.
(3) technology is simple, and processing cost is low, can produce in batches.
The silicon nanowire that uses method provided by the invention to make can be used to study low dimension semiconductor character, can also make senser element, electronic device, fiber waveguide device, luminescent device etc., and can produce in batches, has a wide range of applications.
Description of drawings
Fig. 1: the manufacture method schematic diagram of nano wire among the present invention;
Fig. 2: utilize the soi wafer of (100) crystal face top layer silicon to make the silicon nanowires processing step in isosceles trapezoid cross section;
Fig. 3: utilize the soi wafer of (100) crystal face top layer silicon to make the silicon nanowires processing step of square-section;
Fig. 4: utilize the soi wafer of (110) crystal face top layer silicon to make the silicon nanowires processing step of square-section;
Fig. 5: the isotropic etch fabrication techniques nano-silicon beam process step of utilizing soi wafer and silicon;
Fig. 6: utilize the dry etching technology of soi wafer and silicon to make nano-silicon beam process step;
Fig. 7: with the anisotropic etch of silicon, use isotropic etch fabrication techniques nano-silicon beam process step more earlier;
Fig. 8: with the isotropic etch of silicon, make nano-silicon beam process step with anisotropic corrosion technique more earlier;
Fig. 9: with the anisotropic etch of silicon, the dry etching technology of recycle silicon is made nano-silicon beam process step earlier;
Figure 10: with the dry etching technology of silicon, the anisotropic etch of recycle silicon is made nano-silicon beam process step earlier;
Figure 11: use the dry etching technology of silicon earlier, the isotropic etch fabrication techniques nano-silicon beam process step of recycle silicon;
Figure 12: with the isotropic etch technology of silicon, the dry etching technology of recycle silicon is made nano-silicon beam process step earlier;
Figure 13: the nano wire PN junction schematic diagram that is made into.
(a) → (f) is the idiographic flow of preparation process among Fig. 1 and Fig. 2,
Fig. 3-13 is the process schematic representation after the processing step change (seeing corresponding embodiment explanation for details)
Axes of coordinates shown in Fig. 2,3,4,5,7,8,9,10 is represented corresponding SOI material orientation in the processing step.
Among the figure: 1: top layer medium 2: intermediate medium 3: substrate 4: diaphragm 5: front side wall 6: diaphragm 7: beak 8: rear wall 9: nano wire 10: the top layer medium of doping
Embodiment
Below by embodiment concrete application of the present invention is described, semiconductor medium material selection soi wafer, but application of the present invention not only is confined to the SOI material, also not only is confined to embodiment.
Embodiment 1: utilize the soi wafer of the top layer silicon of (100) to make isosceles trapezoid cross section nano-silicon beam (Fig. 2)
Select soi wafer, top layer medium 1 is＜100〉crystal orientation monocrystalline silicon face, and the composition of intermediate medium 2 is a silica, and the composition of substrate 3 is a silicon, and the composition of diaphragm 4 is a silicon nitride, and the composition of diaphragm 6 is a silica, makes the silicon nanowires 9 on the intermediate medium 2.Utilize the hydrofluoric acid of dilution to empty intermediate medium 2 following above the top layer medium 1 then, just become airborne nano-silicon beam.The concrete manufacture craft of this device is as follows:
(1) the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium 1 is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm 4.
(2) photoetching silicon nitride diaphragm 4, the border lines are along＜110〉direction, shown in Fig. 2 (a).
(3) utilize anisotropic etchant (as potassium hydroxide or tetramethyl ammonium hydroxide solution etc.) the corrosion silicon top layer medium 1 of silicon to silica middle dielectric layer 2, (111) face of silicon top layer medium 1 occurs owing to corrosion rate is extremely low from stopping, form front side wall 5, front side wall 5 is 54.7 ° with the bottom surface angle, and the height of front side wall 5 is the thickness of silicon top layer medium 1.Shown in Fig. 2 (b).
(4) clean back growth one deck silica, form diaphragm 6 and beak 7, shown in Fig. 2 (c).
(5) remove silicon nitride diaphragm 4, expose following silicon top layer medium 1 and silica beak 7, shown in Fig. 2 (d).
(6) use the anisotropic etchant (as potassium hydroxide or tetramethyl ammonium hydroxide solution etc.) of silicon to corrode the silicon top layer medium 1 that does not have silica front side wall 5 and beak 7 to block, occur from stopping at (111) of silicon top layer medium 1 face, form rear wall 8 at other direction, rear wall 8 also is 54.7 ° with the bottom surface angle.Folded zone (cross section is the prism of approximate isosceles trapezoid), two side is monocrystalline silicon nano line 9, shown in Fig. 2 (e).
(7) utilize the silica middle dielectric layer 2 of solution removal silica diaphragm 6 such as dilute hydrofluoric acid and silicon nanowires 9 belows after cleaning, promptly form unsettled silicon nanowires 9, shown in Fig. 2 (f).
Embodiment 2: utilize the soi wafer of the top layer silicon of (100) to make approximate rectangular cross section nano-silicon beam
Manufacturing process steps among the embodiment 1 is done following change (number of steps is with embodiment 1, and step among the embodiment 1 (2) (3) (6) is done following change successively, and all the other are identical with embodiment 1):
(2) photoetching silicon nitride diaphragm 4, the border lines are along＜100〉direction, shown in Fig. 3 (a).
(3) utilize anisotropic etchant (as potassium hydroxide or tetramethyl ammonium hydroxide solution etc.) the corrosion silicon top layer medium 1 of silicon to silica intermediate medium 2, since corrosive liquid downwards with the corrosion rate identical (its erosional surface is (100) face) of side direction, so form approximately perpendicular front side wall 5, the height of front side wall 5 is the thickness of silicon top layer medium 1, shown in Fig. 3 (b).
(6) use the anisotropic etchant (as potassium hydroxide or tetramethyl ammonium hydroxide solution etc.) of silicon to corrode the silicon top layer medium 1 that does not have silica front side wall 5 and beak 7 to block, form vertical rear wall 8.Silicon rear wall 8 is monocrystalline silicon nano line 9 with silicon front side wall 5 folded zones (cross section is approximate rectangular prism), shown in Fig. 3 (c).
Embodiment 3: utilize the soi wafer of the top layer silicon of (110) to make approximate rectangular cross section nano-silicon beam
Semi-conducting material among the embodiment 1 is changed to silicon top layer medium and is＜110〉crystal orientation soi wafer, and manufacturing process steps takes turns doing following change, and all the other are identical with embodiment 1:
(2) photoetching silicon nitride diaphragm 4, the border lines are along＜112〉crystal orientation, shown in Fig. 4 (a).
(3) anisotropic etchant (as potassium hydroxide or tetramethyl ammonium hydroxide solution etc.) the corrosion silicon top layer medium 1 that utilizes silicon occurs forming vertical front side wall 5, shown in Fig. 4 (b) perpendicular to (111) of bottom surface slow erosional surface to silica intermediate medium 2.
(6) use the anisotropic etchant (as potassium hydroxide or tetramethyl ammonium hydroxide solution etc.) of silicon to corrode the silicon top layer medium 1 that does not have silica front side wall 5 and beak 7 to block, form vertical rear wall 8.Silicon rear wall 8 is monocrystalline silicon nano line 9 with silicon front side wall 5 folded zones (cross section is approximate rectangular prism), shown in Fig. 4 (c).
Embodiment 4: the isotropic etch fabrication techniques nano-silicon beam that utilizes soi wafer and silicon
Silicon top layer medium can be the soi wafer in any crystal orientation in the semi-conducting material among the embodiment 1, and manufacturing process steps takes turns doing following change, and all the other are identical with embodiment 1:
(2) photoetching silicon nitride diaphragm 4, the border lines can be any direction, shown in Fig. 5 (a).
(3) utilize the isotropic etch liquid (as mixed liquor of hydrofluoric acid, nitric acid, acetic acid etc.) of silicon, control stirring extent and etching time, stop corrosion when corroding silicon top layer medium 1, form the front side wall 5 of approximate circular arc, shown in Fig. 5 (b) to silica intermediate medium 2.
(6) use isotropic etch liquid (as the mixed liquor of hydrofluoric acid, nitric acid, acetic acid etc.) the silicon top layer medium 1 that corrosion does not have silica front side wall 5 and beak 7 to block of silicon, form circular arc rear wall 8.Silicon rear wall 8 and silicon front side wall 5 folded zones are monocrystalline silicon nano line 9, shown in Fig. 5 (c).
Embodiment 5: utilize the dry etching technology of soi wafer and silicon to make the nano-silicon beam
(3) utilize the dry etching technology of silicon, etch silicon top layer medium 1 stops etching during to silica intermediate medium 2, forms approximately perpendicular front side wall 5, as Fig. 6 (a) with (b).
(6) use the dry etching technology of silicon to etch away the silicon top layer medium 1 that does not have silica front side wall 5 and beak 7 to block, form circular arc rear wall 8.Silicon rear wall 8 and silicon front side wall 5 folded zones are monocrystalline silicon nano line 9, shown in Fig. 6 (c).
All the other are with embodiment 4.
Embodiment 6: utilize the anisotropic etch of silicon to combine with the isotropic etch technology and make the nano-silicon beam
The manufacturing process steps of embodiment 1,2,3 can be done following change (number of steps is with embodiment 1) respectively:
(6) use isotropic etch liquid (as the mixed liquor of hydrofluoric acid, nitric acid, acetic acid etc.) the silicon top layer medium 1 that corrosion does not have silica front side wall 5 and beak 7 to block of silicon, form circular arc rear wall 8.Silicon rear wall 8 and silicon front side wall 5 folded zones are monocrystalline silicon nano line 9.
Embodiment 7: utilize the anisotropic etch of silicon to combine with the isotropic etch technology and make the nano-silicon beam
The manufacturing process steps of embodiment 1,2,3 can be done following change (number of steps is with embodiment 1) respectively:
(3) utilize the isotropic etch liquid (as the mixed liquor of hydrofluoric acid, nitric acid, acetic acid etc.) of silicon, control stirring extent and etching time, corrosion silicon top layer medium 1 stop corrosion during to silica intermediate medium 2, form the front side wall 5 of approximate circular arc.
This processing step schematic diagram was respectively shown in Fig. 8 (a) and (b), (c) after embodiment 1,2,3 did above-mentioned change.
Among the embodiment 1,2,3 in the bracket of step (6) about the deletion of the declaratives of silicon nanowires 9 cross sections, all the other are respectively with embodiment 1,2,3.
Embodiment 8: utilize the anisotropic etch of silicon to combine with dry etching technology and make the nano-silicon beam
The manufacturing process steps of embodiment 6 is done following change (number of steps is with embodiment 1):
(6) use the dry etching technology of silicon to etch away the silicon top layer medium 1 that does not have silica front side wall 5 and beak 7 to block, form near normal rear wall 8.Silicon rear wall 8 and silicon front side wall 5 folded zones are monocrystalline silicon nano line 9.
Be the corresponding Fig. 9 of changing into the (a) and (b) of schematic diagram Fig. 7 (a) and (b), (c), (c) of embodiment 6 after the above-mentioned change.All the other are respectively with embodiment 6.
Embodiment 9: utilize the anisotropic etch of silicon to combine with dry etching technology and make the nano-silicon beam
The manufacturing process steps of embodiment 7 is done following change (number of steps is with embodiment 1):
(3) utilize the dry etching technology of silicon, etch silicon top layer medium 1 stops etching during to silica intermediate medium 2, forms approximately perpendicular front side wall 5.
Be the corresponding Figure 10 of changing into the (a) and (b) of schematic diagram Fig. 8 (a) and (b), (c), (c) of embodiment 7 after the above-mentioned change.All the other are respectively with embodiment 7.
Embodiment 10: utilize the isotropic etch of silicon to combine with dry etching technology and make the nano-silicon beam
The manufacturing process steps of embodiment 4 is done following change (number of steps is with embodiment 1):
(3) utilize the dry etching technology of silicon, etch silicon top layer medium 1 stops etching during to silica intermediate medium 2, forms approximately perpendicular front side wall 5.
This step schematic diagram as shown in figure 11 after embodiment 4 did above-mentioned change.All the other are respectively with embodiment 4.
Embodiment 11: utilize the isotropic etch of silicon to combine with dry etching technology and make the nano-silicon beam
The manufacturing process steps of embodiment 4 is done following change (number of steps is with embodiment 1):
(6) utilize the dry etching technology of use silicon to etch away the silicon top layer medium 1 that does not have silica front side wall 5 and beak 7 to block, form circular arc rear wall 8.Silicon rear wall 8 and silicon front side wall 5 folded zones are monocrystalline silicon nano line 9.
This step schematic diagram as shown in figure 12 after embodiment 4 did above-mentioned change.All the other are respectively with embodiment 4.
Embodiment 12: make the PN junction on the silicon nanowire
Select N type substrate, in advance boron diffusion was carried out in specific zone before making nano wire, this regional silicon top layer Media ID is a doped region top layer medium 10.Make the nano wire that to make in the future, vertically have half to become the P type.And then according to front embodiment 1 to 12 described technical process making silicon nanowire.PN junction on the silicon nanowire that is made into as shown in figure 13.
Claims (10)
1. the nano wire manufacture method of a based semiconductor material is characterized in that its manufacture craft is:
(a) silicon on selection soi wafer or the sapphire is the semi-conducting material on the dielectric layer, top layer medium (1) is arranged above, intermediate medium (2) and substrate (3);
(b) form diaphragm (4) on the surface of top layer medium (1);
(c) remove not protected top layer medium (1), expose the front side wall (5) of the top layer medium (1) that is not removed;
(d) form another layer diaphragm (6), front side wall (5) is protected, and in the process that forms diaphragm (6), diaphragm (6) is got between diaphragm (4) and the protected top layer medium (1), formation is similar to the structure of beak shape, promptly produces so-called " beak effect ";
(e) remove residual diaphragm (4), keep diaphragm (6) and beak (7) simultaneously;
(f) remove the not top layer medium (1) below diaphragm (6) and beak (7); the top layer medium (1) of diaphragm (6) and beak (7) below is partly remained simultaneously; its marginal portion forms rear wall (8); promptly form the nano wire (9) on the middle dielectric layer (2) between rear wall (8) and the front side wall (5), its composition is identical with top layer medium 1.
2. by the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that described nano wire or be approximate rectangular or trapezoid cross section.
3. by the nano wire manufacture method of claim 1 or 2 described a kind of based semiconductor materials, it is characterized in that the middle dielectric layer (2) that removes described nano wire (9) below forms unsettled nano wire.
4. press the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that forming diaphragm (4) before on the surface of top layer medium (1), optionally top layer medium (1) material is mixed, thereby produce the nano wire (9) of different conduction-types; Described doping type is boron or phosphorus or other doping; The mode of mixing is diffusion or ion injection.
5. by the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that:
(A) utilize the SOI of (100) top layer silicon to make isosceles trapezoid nano-silicon beam, its manufacture craft is:
(a) get the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium (1) is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm (4);
(b) photoetching silicon nitride diaphragm (4), the border lines are along＜110〉direction;
(c) be the anisotropic etchant of silicon with potassium hydroxide or tetramethyl ammonium hydroxide solution, corrosion silicon top layer medium (1) is to silica middle dielectric layer (2), (111) face of silicon top layer medium (1) occurs from stopping, form front side wall (5), front side wall (5) is 54.7 ° with the bottom surface angle, and the height of front side wall (5) is the thickness of silicon top layer medium (1);
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) re-use the anisotropic etchant of potassium hydroxide or tetramethyl ammonium hydroxide solution silicon, the silicon top layer medium (1) that corrosion does not have silica front side wall (5) and beak (7) to block, occur from stopping at (111) of silicon top layer medium (1) face, form rear wall 8 at other direction, rear wall 8 also is 54.7 ° with the bottom surface angle; Folded zone, two side is a monocrystalline silicon nano line 9; Its cross section is the prism of approximate isosceles trapezoid;
(g) utilize silica middle dielectric layer (2) below dilute hydrofluoric acid solution removal silica diaphragm (6) and the silicon nanowires (9) after cleaning, promptly form unsettled silicon nanowires (9);
(B) manufacture craft of utilizing the SOI of the top layer silicon of (110) to make approximate rectangular cross section is:
(a) get the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium (1) is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm (4);
(b) photoetching silicon nitride diaphragm 4, the border lines are along＜112〉crystal orientation;
(c) be the anisotropic etchant of silicon with potassium hydroxide or tetramethyl ammonium hydroxide solution, corrosion silicon top layer medium (1) occurs forming vertical front side wall (5) perpendicular to (111) of bottom surface slow erosional surface to silica intermediate medium (2);
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) use potassium hydroxide or tetramethyl ammonium hydroxide solution to corrode the silicon top layer medium (1) that does not have silica front side wall (5) and beak (7) to block, form vertical rear wall (8) as the anisotropic etchant of silicon.Silicon rear wall (8) is monocrystalline silicon nano line (9) with the folded zone of silicon front side wall (5), and cross section is approximate rectangular prism;
(g) utilize silica middle dielectric layer (2) below dilute hydrofluoric acid solution removal silica diaphragm (6) and the silicon nanowires (9) after cleaning, promptly form unsettled silicon nanowires (9);
6. by the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that utilizing the isotropic etch fabrication techniques nano-silicon beam of soi wafer and silicon, its manufacture craft is:
(a) get appoint between the SOI material in crystal orientation, the thickness of monocrystalline silicon top layer medium (1) cleans the back deposited silicon nitride and forms diaphragm (4) less than 300nm;
(b) photoetching silicon nitride diaphragm (4), the border lines can be any direction;
(c) utilize the isotropic etch liquid of the mixed liquor silicon of hydrofluoric acid, nitric acid, acetic acid, corrosion silicon top layer medium 1 stops corrosion during to silica intermediate medium 2, forms the front side wall (5) of approximate circular arc;
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) use the isotropic etch corrosion of above-mentioned silicon not have the front side wall 5 of silica and the silicon top layer medium 1 that beak 7 blocks, form circular arc rear wall 8, silicon rear wall 8 and silicon front side wall 5 folded zones are monocrystalline silicon nano line 9;
(g) utilize silica middle dielectric layer (2) below dilute hydrofluoric acid solution removal silica diaphragm (6) and the silicon nanowires (9) after cleaning, promptly form unsettled silicon nanowires (9);
7. by the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that utilizing the dry etching technology of soi wafer and silicon to make the nano-silicon beam, its manufacture craft is:
(a) get the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium (1) is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm (4);
(b) photoetching silicon nitride diaphragm (4), the border lines are along＜110〉direction;
(c) utilize the dry etching technology of silicon, etch silicon top layer medium (1) stops etching during to silica intermediate medium (2), forms approximately perpendicular front side wall (5);
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) use the dry etching technology of silicon to etch away the silicon top layer medium (1) that does not have silica front side wall (5) and beak (7) to block, form circular arc rear wall (8).Silicon rear wall (8), the zone folded with silicon front side wall (5) is monocrystalline silicon nano line (9);
8. by the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that utilizing the anisotropic etch of the silicon making nano-silicon beam that combines with isotropic etch, its manufacture craft is:
(a) get the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium (1) is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm (4);
(b) photoetching silicon nitride diaphragm (4), the border lines are along＜110〉direction;
(c) be the anisotropic etchant of silicon with potassium hydroxide or tetramethyl ammonium hydroxide solution, corrosion silicon top layer medium (1) is to silica middle dielectric layer (2), (111) face of silicon top layer medium (1) occurs from stopping, form front side wall (5), front side wall (5) is 54.7 ° with the bottom surface angle, and the height of front side wall (5) is the thickness of silicon top layer medium (1);
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) mixed liquor that uses hydrofluoric acid, nitric acid, the acetic acid silicon top layer medium (1) that do not have silica front side wall (5) and beak (7) to block as the isotropic etch corrosion of silicon, form the rear wall (8) of circular arc or nearly circular arc, the folded zone of silicon rear wall (8) and silicon front side wall (5) is monocrystalline silicon nano line 9;
9. press the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that the described anisotropic etch that utilizes silicon combines with dry etching technology makes silicon nano-silicon beam, and its manufacture craft can be selected any one in following two kinds:
(A) (a) get the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium (1) is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm (4);
(b) photoetching silicon nitride diaphragm (4), the border lines are along＜110〉direction;
(c) utilize isotropic etch hydraulic control system stirring extent and the etching time of the mixed liquor of hydrofluoric acid, nitric acid, acetic acid, stop corrosion during corrosion silicon top layer medium (1) to silica intermediate medium (2), form the front side wall (5) of approximate circular arc for silicon;
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) re-use the anisotropic etchant of potassium hydroxide or tetramethyl ammonium hydroxide solution silicon, the silicon top layer medium (1) that corrosion does not have silica front side wall (5) and beak (7) to block, occur from stopping at (111) of silicon top layer medium (1) face, form rear wall 8 at other direction, rear wall 8 also is 54.7 ° with the bottom surface angle, and folded zone, two side is a monocrystalline silicon nano line 9; Its cross section is the prism of approximate isosceles trapezoid;
(B) (a) get the SOI material in (100) crystal orientation, the thickness of monocrystalline silicon top layer medium (1) is less than 300nm, cleans the back deposit silicon nitride and forms diaphragm (4);
(b) photoetching silicon nitride diaphragm (4), the border lines are along＜110〉direction;
(c) be the anisotropic etchant of silicon with potassium hydroxide or tetramethyl ammonium hydroxide solution, corrosion silicon top layer medium (1) is to silica middle dielectric layer (2), (111) face of silicon top layer medium (1) occurs from stopping, form front side wall (5), front side wall (5) is 54.7 ° with the bottom surface angle, and the height of front side wall (5) is the thickness of silicon top layer medium (1);
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) use the dry etching technology of silicon to etch away the silicon top layer medium (1) that does not have silica front side wall (5) and beak (7) to block, form near normal rear wall (8), the folded zone of silicon rear wall (8) and silicon front side wall (5) is monocrystalline silicon nano line (9);
(g) utilize silica middle dielectric layer (2) below dilute hydrofluoric acid solution removal silica diaphragm (6) and the silicon nanowires (9) after cleaning, promptly form unsettled silicon nanowires (9);
10. press the nano wire manufacture method of the described a kind of based semiconductor material of claim 1, it is characterized in that the described isotropic etch that utilizes silicon combines with dry etching makes the nano-silicon beam, and its manufacture craft can be selected any one in following two kinds of technologies for use:
(A) (a) get appoint between the SOI material in crystal orientation, the thickness of monocrystalline silicon top layer medium (1) cleans the back deposited silicon nitride and forms diaphragm (4) less than 300nm;
(b) photoetching silicon nitride diaphragm (4), the border lines can be any direction;
(c) utilize the dry etching technology of silicon, etch silicon top layer medium (1) stops etching during to silica intermediate medium (2), forms approximately perpendicular front side wall 5;
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) use the isotropic etch liquid of the mixed liquor of hydrofluoric acid, nitric acid, acetic acid as silicon, corrosion does not have the front side wall (5) of silica and the silicon top layer medium (1) that beak (7) blocks, form circular arc rear wall (8), the folded zone of silicon rear wall (8) and silicon front side wall (5) is monocrystalline silicon nano line (9);
(g) utilize silica middle dielectric layer (2) below dilute hydrofluoric acid solution removal silica diaphragm (6) and the silicon nanowires (9) after cleaning, promptly form unsettled silicon nanowires (9);
(B) (a) get appoint between the SOI material in crystal orientation, the thickness of monocrystalline silicon top layer medium (1) cleans the back deposited silicon nitride and forms diaphragm (4) less than 300nm;
(b) photoetching silicon nitride diaphragm (4), the border lines can be any direction;
(c) utilize the isotropic etch liquid of the mixed liquor silicon of hydrofluoric acid, nitric acid, acetic acid, corrosion silicon top layer medium 1 stops corrosion during to silica intermediate medium 2, forms the front side wall (5) of approximate circular arc;
(d) clean back growth one deck silica, form diaphragm (6) and beak (7);
(e) remove silicon nitride diaphragm (4), expose following silicon top layer medium (1) and silica beak (7);
(f) utilize the dry etching technology of use silicon to etch away the silicon top layer medium (1) that does not have silica front side wall (5) and beak (7) to block, form circular arc rear wall (8), the folded zone of silicon rear wall (8) and silicon front side wall (5) is monocrystalline silicon nano line (9);
(g) utilize silica middle dielectric layer (2) below dilute hydrofluoric acid solution removal silica diaphragm (6) and the silicon nanowires (9) after cleaning, promptly form unsettled silicon nanowires (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100164629A CN1326214C (en) | 2004-02-20 | 2004-02-20 | Manufacturing method of nano-line on semiconductor material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100164629A CN1326214C (en) | 2004-02-20 | 2004-02-20 | Manufacturing method of nano-line on semiconductor material |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1560906A true CN1560906A (en) | 2005-01-05 |
| CN1326214C CN1326214C (en) | 2007-07-11 |
Family
ID=34440490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100164629A Expired - Fee Related CN1326214C (en) | 2004-02-20 | 2004-02-20 | Manufacturing method of nano-line on semiconductor material |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1326214C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446194C (en) * | 2005-11-30 | 2008-12-24 | 中国科学院半导体研究所 | Method of aluminium oxide dielectric film silicon ion injection corrosion on semiconductor lining base |
| CN102359837A (en) * | 2011-08-31 | 2012-02-22 | 江苏奥力威传感高科股份有限公司 | Beam film combined sensor structure |
| CN102079503B (en) * | 2009-11-26 | 2012-08-29 | 中芯国际集成电路制造(上海)有限公司 | Etching method of silicon substrate forming MEMS (Micro Electro Mechanical System) device |
| CN102955200A (en) * | 2011-08-30 | 2013-03-06 | 上海华虹Nec电子有限公司 | Dry etching method for mono-crystalline silicon back etching of optical divider |
| CN106611792A (en) * | 2015-10-23 | 2017-05-03 | 三星电子株式会社 | Semiconductor device and manufacturing method therefor |
| CN107102033A (en) * | 2016-02-23 | 2017-08-29 | 延世大学校产协力团 | Hydrogen sensor and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6627511B1 (en) * | 1995-07-28 | 2003-09-30 | Motorola, Inc. | Reduced stress isolation for SOI devices and a method for fabricating |
| CN1215530C (en) * | 2003-07-25 | 2005-08-17 | 中国科学院上海微***与信息技术研究所 | Method for producing silicon nano wire |
-
2004
- 2004-02-20 CN CNB2004100164629A patent/CN1326214C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446194C (en) * | 2005-11-30 | 2008-12-24 | 中国科学院半导体研究所 | Method of aluminium oxide dielectric film silicon ion injection corrosion on semiconductor lining base |
| CN102079503B (en) * | 2009-11-26 | 2012-08-29 | 中芯国际集成电路制造(上海)有限公司 | Etching method of silicon substrate forming MEMS (Micro Electro Mechanical System) device |
| CN102955200A (en) * | 2011-08-30 | 2013-03-06 | 上海华虹Nec电子有限公司 | Dry etching method for mono-crystalline silicon back etching of optical divider |
| CN102359837A (en) * | 2011-08-31 | 2012-02-22 | 江苏奥力威传感高科股份有限公司 | Beam film combined sensor structure |
| CN106611792A (en) * | 2015-10-23 | 2017-05-03 | 三星电子株式会社 | Semiconductor device and manufacturing method therefor |
| CN107102033A (en) * | 2016-02-23 | 2017-08-29 | 延世大学校产协力团 | Hydrogen sensor and preparation method thereof |
| CN107102033B (en) * | 2016-02-23 | 2020-01-03 | 新星C&T | Hydrogen sensor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1326214C (en) | 2007-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1215530C (en) | Method for producing silicon nano wire | |
| TWI646221B (en) | Etching method, method of manufacturing article, and etching solution | |
| JP5375821B2 (en) | Phosphorous paste for diffusion and method for manufacturing solar cell using the same | |
| CN1150631C (en) | Quantum wires formed on substrate, manufacturing method thereof, and device having quantum wires on substrate | |
| KR101465276B1 (en) | Printable medium for etching of oxidic, transparent and conducting layers | |
| TWI472477B (en) | Silicon nanostructures and method for producing the same and application thereof | |
| Hsieh et al. | Nanophotonic switch: gold-in-Ga2O3 peapod nanowires | |
| CN102084467A (en) | Process for fabricating nanowire arrays | |
| US7803698B2 (en) | Methods for controlling catalyst nanoparticle positioning and apparatus for growing a nanowire | |
| TW200807547A (en) | Method for manufacturing semiconductor substrate, semiconductor substrate for solar cell and etching solution | |
| TW200835778A (en) | Particle-containing etching pastes for silicon surfaces and layers | |
| Schlur et al. | Synthesis of zinc oxide nanorods or nanotubes on one side of a microcantilever | |
| CN1558868A (en) | Nano gripper and method of manufacturing thereof | |
| CN102856446B (en) | Epitaxial substrate with nano structure and manufacturing method of light-emitting diode | |
| JP2009532665A (en) | Monolithic high aspect ratio nano-sized scanning probe microscope (SPM) tips formed by nanowire growth | |
| CN102694090A (en) | Manufacturing method for graphical sapphire substrate | |
| Basher et al. | Development of zinc-oxide nanorods on chemically etched zinc plates suitable for high-efficiency photovoltaics solar cells | |
| JP2008019113A (en) | Method for producing silicon particulate-containing liquid and method for producing silicon particulate | |
| CN1560906A (en) | Manufacturing method of nano-line on semiconductor material | |
| US9768331B2 (en) | Screen printing electrical contacts to nanowire areas | |
| CN1749153A (en) | Method for producing MEMS sensor suspension beam structure | |
| CN102157371B (en) | Method for producing monocrystalline silicon nanometer structure | |
| CN104037320A (en) | Large area manufacturing method for zinc oxide nano micro generators | |
| CN1889274A (en) | Silicon nano line homo pn junction diode and producing method thereof | |
| JP5957835B2 (en) | Method for producing solar cell wafer, method for producing solar cell, and method for producing solar cell module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070711 Termination date: 20110220 |