CN1545031A - Data handling method of FIFO memory device - Google Patents
Data handling method of FIFO memory device Download PDFInfo
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- CN1545031A CN1545031A CNA2003101135489A CN200310113548A CN1545031A CN 1545031 A CN1545031 A CN 1545031A CN A2003101135489 A CNA2003101135489 A CN A2003101135489A CN 200310113548 A CN200310113548 A CN 200310113548A CN 1545031 A CN1545031 A CN 1545031A
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Abstract
The invention discloses the data processing method of a FIFO memory, and its kernel ideas: a write module internally buffers write data and address of FIFO, which make the buffered data and address lag the actual ones by a beat, and thus when the overflow occurs, it is able to write the buffered data added with an overflow flag in the position the buffered address points to, accordingly avoiding the data of the current read pointer. It is especially applied to the occasion of using FIFO to store the data with frame structure, able to correct the errors caused by asynchronism and effectively protect the data, furthest enhancing efficiency and utilization ratio of data storage.
Description
Technical field
The present invention relates to field of storage, particularly a kind of fifo queue (First In First Out is hereinafter to be referred as FIFO) storer is to processing method of data.
Background technology
FIFO is a kind of storage component part of being used widely at electronic applications, is generally used for the buffer memory of data and is used to hold the frequency of asynchronous signal or the difference of phase place.Common FIFO storer is by writing control module, reading control module and memory module is formed.The principle of work of FIFO is as follows: with read/write address pointer independently under the control of reading sequentially from/to the memory module read/write data, the read-write pointer is all from first address location, sequential read/write last address location is got back to first address location then again.By comparison, provide the sky of memory module and full judgement to read pointer and write pointer.
The overflowing of FIFO (Overrun) is because reading and writing both sides speed difference is excessive, write at FIFO and attempted again under the full situation to write that new data cause.For the spillover of FIFO, common disposal route is to abandon new data, and overflowing the position that (Overrun) sign is write the write address correspondence, write address does not increase progressively.The weak point of this method is: may cause data degradation like this and bring certain performance waste.This is because the reason that FIFO overflows is because the data that a side of data read can not in time be read away among the FIFO cause, if not contact between the data of each clauses and subclauses among the FIFO, there is not any problem in existing disposal route, if but the data of depositing in FIFO are to have frame structure (as HDLC, the data of Ethernet) data, be several continuous data represented Frames or represent a data structure, in this case, the existing disposal route that FIFO is overflowed will produce aforesaid problem: may cause data degradation and bring certain performance waste.Fig. 1 is the process synoptic diagram that FIFO overflows in the prior art.
As shown in Figure 1, suppose that this FIFO has 5 addresses, at t
0Constantly, data E, A, B, C, D have been write respectively in these 5 addresses; These data of ABCDE all are the data with frame structure, it is the single byte of Frame, each byte of Frame all has an end mark (Last) to indicate whether this byte is last byte of these frame data, also has an overflow indicator (OV) to identify this byte simultaneously whether overflow error has taken place.At t
0Constantly: read pointer points to address 3, and data F writes address 1, write pointers point address 2, and this FIFO differs from data and is just write completely, and the overflow indicator position and the end mark position of data is 0 in each address at this moment, is in disarmed state; At t
1Constantly, read pointer points to address 3, and data G writes address 2, write pointers point address 3, and FIFO is write full, if data G is last data byte of a Frame just, then the end mark position of data G should be effective at this moment, puts 1; At t
2Constantly, read pointer points to address 3, outside have new data H application to write FIFO again, this moment is because read pointer and write pointer all point to address 3, therefore the data spillover takes place, according to existing disposal route, new data H will be abandoned, the overflow indicator position of the data of 3 corresponding clauses and subclauses is changed to effectively in the address simultaneously, i.e. the overflow indicator position 1 of data C in the address 3.In ensuing data read process, the data that read at first are to begin from the address 3 that read pointer points to, at this moment, read control module and will find that the overflow indicator position of data C is effective, existing disposal route can think that beginning to finish (is exactly the data G of address 2 correspondences for this example) to this frame data from this byte all is invalid data and abandoning.But in fact these frame data are intact in fact, and in this case, existing disposal route has just caused the waste of efficient.The disposal route of this moment otherwise be application system with all logic resets that is associated, restart to receive data, but like this with regard to possible loss one frame or the correct data of multiframe; Will remember the practical significance of this overflow indicator position, but do like this and can make under the situation that may take place repeatedly to overflow, the logic of the data read complexity very that becomes.
Summary of the invention
Purpose of the present invention is exactly in order to solve may causing data degradation and bringing the problem of certain performance waste of existing in the prior art, to propose a kind of data processing method of FIFO storer.
Core concept of the present invention is: in order to realize FIFO is overflowed the processing of the situation of (Overrun), write data and the write address to FIFO carries out buffer memory in inside to write control module, the result that buffer memory obtains will be than the bat that lags behind of the write address of reality and write data, like this when overflowing (Overrun), the position that can point to the data cached address that writes buffer memory of having added overflow indicator just, thus avoid destroying the data that current read pointer is pointed to the address.
A kind of data processing method of FIFO storer comprises the following steps:
(1) data storage area to each write address correspondence is provided with the overflow indicator position;
(2) outside application writes data in FIFO;
(3) it is full to judge whether FIFO has write, if do not write full then current write data and the write address of buffer memory;
(4) current write data is write in the current write address;
(5) write address adds 1;
(6) re-execute step (2);
(7) if having write full, FIFO will write in the write address of buffer memory behind the additional overflow indicator of the write data of buffer memory;
(8) re-execute step (2).
Described write data is the data with frame structure.
Thereby the present invention proposes and a kind ofly when overflowing, realize disposal route that FIFO is overflowed being particularly useful for having the data conditions of frame structure with the FIFO storage with the method for data cached replacement current data by write address and write data being carried out buffer memory.The method that the application of the invention proposes can solve because the mistake of asynchronous generation, and effective protected data, has improved the efficient and the utilization ratio of data storage to greatest extent.
Description of drawings
Fig. 1 is the process synoptic diagram that FIFO overflows in the prior art.
Fig. 2 realizes that the FIFO of method of the present invention writes the structural representation of control module.
Fig. 3 is the process flow diagram of the method that proposes of the present invention.
Fig. 4 is the process synoptic diagram of an Application Example of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Fig. 1 had carried out explanation in background technology.
Fig. 2 realizes that the FIFO of method of the present invention writes the structural representation of control module.As shown in Figure 2, for the method that realizes that the present invention proposes, write data and write address are carried out buffer memory, writing control module has increased by two MUX and two registers.Wherein register 1 is used for cache writing data, and register 2 is used for the buffer memory write address, and MUX 1 comes triggering selection to export the write data of buffer memory in current write data and the register 1 by the full signal of FIFO; MUX 2 is come the current write address of triggering selection output and the write address of the buffer memory in the register 2 by the full signal of FIFO.As seen from Figure 2, can realize the middle write address of method proposed by the invention and the buffer memory and the selection output of write data by this structure of writing control module.
Fig. 3 is the process flow diagram of the method that proposes of the present invention.As shown in Figure 3, the method for the present invention's proposition comprises the following steps: that (1) is provided with the overflow indicator position to the data storage area of each write address correspondence; (2) outside application writes data in FIFO; (3) it is full to judge whether FIFO has write, if do not write full then current write data and the write address of buffer memory; (4) current write data is write in the current write address; (5) write address adds 1; (6) re-execute step (2); (7) if having write full, FIFO will write in the write address of buffer memory behind the additional overflow indicator of the write data of buffer memory; (8) re-execute step (2).
Fig. 4 is the process synoptic diagram of an Application Example of the present invention.As shown in Figure 4, in conjunction with Fig. 1, this FIFO has 5 addresses, these data of ABCDE all are the data with frame structure, it is the single byte of Frame, each byte of Frame all has an end mark (Last) to indicate whether this byte is last byte of these frame data, also has an overflow indicator (OV) to identify this byte simultaneously whether overflow error has taken place.According to the proposed method, at t
0Constantly, this FIFO overflows, and is not also promptly write and expires, and therefore, has write data E, A, B, C, D respectively, t in these 5 addresses
0The write data of buffer memory is E constantly, and the write address of buffer memory is 0, becomes 1 after write address adds 1.According to the proposed method:
At t
0Constantly: read pointer points to address 3, current write address is 1, and this moment, outside application write FIFO with data F, judges that this moment, FIFO was not write full, therefore, the write data of buffer memory is F, and the write address of buffer memory is 1, and data F is write address 1, write address adds 1 and becomes 2, this FIFO differs from data and is just write completely, and the overflow indicator position and the end mark position of data is 0 in each address at this moment, is in disarmed state.
At t
1Constantly: read pointer points to address 3; Outside application writes FIFO with data G, and judgement FIFO this moment is not write full, and therefore, the write data of buffer memory is G, and the write address of buffer memory is 2; Data G is write address 2, and write address adds 1 and becomes 3.This moment, FIFO was all write full.If data G is last data byte of a Frame just, then the end mark position of data G should be effective at this moment, put 1.
At t
2Constantly, read pointer points to address 3; Outside application again writes FIFO with new data H, current write address is 3, because read pointer and write pointer all point to same address 3, this moment, FIFO was write full, the data spillover takes place, according to the proposed method, will will write in the write address of buffer memory behind the additional overflow indicator of the write data of buffer memory, this moment, the write data of buffer memory was G, the write address of buffer memory is 2, therefore will write in the address 2 behind the additional overflow indicator of data G, the overflow indicator position 1 that is about to the data G in the raw address 2 gets final product.In ensuing data read process; the data that read at first are to begin from the address 3 that read pointer points to; after using the method for the present invention's proposition; the data that read have been exactly normal data; after having read 4 data, read the data G in the address 2; can find that just overflow indicator and end mark are all effective; and this moment; all data of this Frame are all read; in this case; the processing logic on upper strata just needn't abandon these frame data, thereby has improved the efficient and the utilization ratio of data storage, has also effectively protected data simultaneously.
Claims (3)
1, a kind of data processing method of FIFO storer is characterized in that comprising the following steps:
(1) data storage area to each write address correspondence is provided with the overflow indicator position;
(2) outside application writes data in FIFO;
(3) it is full to judge whether FIFO has write, if do not write full then current write data and the write address of buffer memory;
(4) current write data is write in the current write address;
(5) write address adds 1;
(6) re-execute step (2);
(7) if having write full, FIFO will write in the write address of buffer memory behind the additional overflow indicator of the write data of buffer memory;
(8) re-execute step (2).
2, the data processing method of a kind of FIFO storer according to claim 1 is characterized in that described write data is the data with frame structure.
3, the data processing method of a kind of FIFO storer according to claim 1 is characterized in that described buffer memory to write data and write address realizes by register.
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| CN 200310113548 CN1264096C (en) | 2003-11-17 | 2003-11-17 | Data handling method of FIFO memory device |
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| CN 200310113548 CN1264096C (en) | 2003-11-17 | 2003-11-17 | Data handling method of FIFO memory device |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100485643C (en) * | 2005-02-07 | 2009-05-06 | 国际商业机器公司 | Method and system for detection and recovery of lost writes in storage devices |
| CN101261575B (en) * | 2008-02-26 | 2010-04-21 | 北京天碁科技有限公司 | Asynchronous FIFO memory accomplishing unequal breadth data transmission |
| CN101299204B (en) * | 2008-06-10 | 2010-06-02 | 北京天碁科技有限公司 | Asynchronous FIFO and address conversion method thereof |
| CN101330620B (en) * | 2008-08-05 | 2011-04-13 | 北京海尔集成电路设计有限公司 | Method and apparatus for encoding and decoding audio and video data |
| CN102169420A (en) * | 2011-04-18 | 2011-08-31 | 杭州海康威视***技术有限公司 | Method and device for circularly reading and writing in buffer zone |
| CN101493759B (en) * | 2008-01-22 | 2011-12-21 | 安凯(广州)微电子技术有限公司 | Address control method of random capacity asynchronous first-in/first-out memory |
| CN102402400A (en) * | 2011-11-25 | 2012-04-04 | 福建星网锐捷网络有限公司 | Method and device for sending data frame |
| CN101059783B (en) * | 2006-03-30 | 2013-11-06 | 英特尔公司 | Transactional memory virtualization |
| CN105183665A (en) * | 2015-09-08 | 2015-12-23 | 福州瑞芯微电子股份有限公司 | Data-caching access method and data-caching controller |
| CN103716532B (en) * | 2012-10-02 | 2017-07-18 | 株式会社索思未来 | Data link and method |
| CN108108148A (en) * | 2016-11-24 | 2018-06-01 | 舒尔电子(苏州)有限公司 | A kind of data processing method and device |
| CN109308180A (en) * | 2018-08-16 | 2019-02-05 | 盛科网络（苏州）有限公司 | The processing method and processing unit of cache congestion |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN115481079A (en) * | 2021-06-15 | 2022-12-16 | 珠海一微半导体股份有限公司 | Data scheduling system, reconfigurable processor and data scheduling method |
| CN116743951A (en) * | 2023-08-09 | 2023-09-12 | 山东云海国创云计算装备产业创新中心有限公司 | Video data processing method, system, storage medium and electronic equipment |
-
2003
- 2003-11-17 CN CN 200310113548 patent/CN1264096C/en not_active Expired - Fee Related
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100485643C (en) * | 2005-02-07 | 2009-05-06 | 国际商业机器公司 | Method and system for detection and recovery of lost writes in storage devices |
| CN101059783B (en) * | 2006-03-30 | 2013-11-06 | 英特尔公司 | Transactional memory virtualization |
| CN101493759B (en) * | 2008-01-22 | 2011-12-21 | 安凯(广州)微电子技术有限公司 | Address control method of random capacity asynchronous first-in/first-out memory |
| CN101261575B (en) * | 2008-02-26 | 2010-04-21 | 北京天碁科技有限公司 | Asynchronous FIFO memory accomplishing unequal breadth data transmission |
| CN101299204B (en) * | 2008-06-10 | 2010-06-02 | 北京天碁科技有限公司 | Asynchronous FIFO and address conversion method thereof |
| CN101330620B (en) * | 2008-08-05 | 2011-04-13 | 北京海尔集成电路设计有限公司 | Method and apparatus for encoding and decoding audio and video data |
| CN102169420A (en) * | 2011-04-18 | 2011-08-31 | 杭州海康威视***技术有限公司 | Method and device for circularly reading and writing in buffer zone |
| CN102169420B (en) * | 2011-04-18 | 2013-10-30 | 杭州海康威视***技术有限公司 | Method and device for circularly reading and writing in buffer zone |
| CN102402400A (en) * | 2011-11-25 | 2012-04-04 | 福建星网锐捷网络有限公司 | Method and device for sending data frame |
| CN102402400B (en) * | 2011-11-25 | 2015-02-25 | 福建星网锐捷网络有限公司 | Method and device for sending data frame |
| CN103716532B (en) * | 2012-10-02 | 2017-07-18 | 株式会社索思未来 | Data link and method |
| CN105183665A (en) * | 2015-09-08 | 2015-12-23 | 福州瑞芯微电子股份有限公司 | Data-caching access method and data-caching controller |
| CN105183665B (en) * | 2015-09-08 | 2018-02-13 | 福州瑞芯微电子股份有限公司 | A kind of data cache accesses method and data cache controller |
| CN108108148A (en) * | 2016-11-24 | 2018-06-01 | 舒尔电子(苏州)有限公司 | A kind of data processing method and device |
| CN109308180A (en) * | 2018-08-16 | 2019-02-05 | 盛科网络（苏州）有限公司 | The processing method and processing unit of cache congestion |
| CN109308180B (en) * | 2018-08-16 | 2021-01-26 | 盛科网络（苏州）有限公司 | Processing method and processing device for cache congestion |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN115481079A (en) * | 2021-06-15 | 2022-12-16 | 珠海一微半导体股份有限公司 | Data scheduling system, reconfigurable processor and data scheduling method |
| CN116743951A (en) * | 2023-08-09 | 2023-09-12 | 山东云海国创云计算装备产业创新中心有限公司 | Video data processing method, system, storage medium and electronic equipment |
| CN116743951B (en) * | 2023-08-09 | 2024-01-12 | 山东云海国创云计算装备产业创新中心有限公司 | Video data processing method, system, storage medium and electronic equipment |
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