CN1538540A - Phase change merhory and method with recovery function - Google Patents
Phase change merhory and method with recovery function Download PDFInfo
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- CN1538540A CN1538540A CNA2004100352276A CN200410035227A CN1538540A CN 1538540 A CN1538540 A CN 1538540A CN A2004100352276 A CNA2004100352276 A CN A2004100352276A CN 200410035227 A CN200410035227 A CN 200410035227A CN 1538540 A CN1538540 A CN 1538540A
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
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Abstract
A phase-change memory device includes a phase-change memory cell having a volume of material which is programmable between amorphous and crystalline states. A write current source selectively applies a first write current pulse to program the phase-change memory cell into the amorphous state and a second write current pulse to program the phase-change memory cell into the crystalline state. The phase-change memory device further includes a restore circuit which selectively applies the first current pulse to the phase-change memory cell to restore at least an amorphous state of the phase-change memory cell.
Description
Technical field
The present invention relates to a kind of phase change memory device, in particular, the present invention relates to a kind of phase transition storage and method that comprises the state restoration of phase change cells.
Background technology
Phase change memory cell device depends on the phase-change material such as chalkogenide etc., and this material can be stablized transformation between amorphous phase and crystalline phase.The different resistance values that two kinds of crystalline phases present are used to distinguish the logical value of memory cell.That is to say that amorphous state presents high impedance, crystalline state presents Low ESR.
With reference now to Fig. 1,, this accompanying drawing has schematically been described the crystal transition of phase change cells.Phase change cells constitutes by the heater 103 of top electrode and hearth electrode 101 and 102, resistance such as BEC and such as the phase-change material body 104 of chalcogenide alloy.The phase of the part of phase-change material 104 is determined by the joule's heat energy of the material that the magnitude of current by resistance heater 103 determines.In order to obtain amorphous state (being called " RESET " state), need be with the write current pulse (" RESET pulse ") of high level by phase change cells, with the part of melted material 104 at short notice.Electric current is removed, and the unit is cooled to rapidly under the fusing point, makes part material 104 have amorphous phase.For example, the fusing point of chalkogenide is about 610 ℃.In order to obtain crystalline state (being called " SET " state), low level write current pulse (" SET pulse ") need be applied to phase change cells for a long time, material 104 is heated to a value that is lower than its fusing point.This amorphous fraction that makes material crystallization once more is a crystalline phase, in case electric current removes, the unit cools off rapidly, this crystalline phase just keeps.For example, the recrystallization temperature of chalkogenide is about 450 ℃.
The temperature that Fig. 2 illustrates SET and RESET operating period chalcogenide phase change unit material over time.As shown in the figure, material becomes noncrystal after being heated to above fusion temperature Tm during the rapid cooling (for example a few nanosecond).By long-time (for example smaller or equal to 50 nanoseconds) at heating material under the fusing point Tm and under the temperature on the crystallization temperature Tx, crystallization process can take place.
Fig. 3 is the curve chart that the V-I characteristic of phase-change memory cell is shown.And example has illustrated the situation of chalcogenide alloy phase-change material.In this embodiment, 1.0 to 1.5mA SET Current Zone is used to write the crystalline state of memory cell, and 1.5 to 2.5mA RESET Current Zone is used to write the amorphous state of memory cell.
From Fig. 3, obviously as can be known, during read operation, can be lower than the low easy different resistance values of distinguishing amorphous state and crystalline state of voltage (as less than 0.5 volt) that read of given threshold voltage vt by employing.Threshold voltage vt is such magnitude of voltage, and promptly when being higher than this voltage, the electrorheological of the unit material of amorphous state and crystalline state must equate.
In traditional phase change random access memory (PRAM), phase change cells is operated as nonvolatile memory.That is to say, need to use sufficiently high write current, keep the amorphous state and the crystalline state of phase-change material.
In traditional amorphous write operation (being the RESET operation), the phase transition process of phase-change material is characterised in that the formation of nucleus and growth step are orderly.This growth step has caused the big ratio between RESET impedance and the SET impedance.For example, the RESET impedance is arrived hundred times in the SET impedance for possible tens times.This is unfavorable for providing higher relatively read margining (sensing margin) and data hold time.Yet unfortunately, the formation of nucleus all needs high write current with growth, and its total power consumption is huge.
Therefore be desirable to provide a kind of phase change memory device that can reduce power consumption, for example PRAM.
Summary of the invention
According to an aspect of the present invention, provide a kind of phase change memory device, having comprised: phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state; With the write current source, optionally apply the first write current pulse phase-change memory cell be programmed for amorphous state and apply the second write current pulse so that phase-change memory cell is programmed for crystalline state.Described phase change memory device also comprises restore circuit, with the first write current pulse choice be applied to phase-change memory cell, to recover the amorphous state of phase-change memory cell.
According to a further aspect in the invention, provide a kind of phase change memory device, having comprised: phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state.Described phase change memory device also comprises: the write current source, under low-power mode, operate, optionally to apply the first write current pulse phase-change memory cell be programmed for amorphous state and apply the second write current pulse so that phase-change memory cell is programmed for crystalline state, with under high power, operate, optionally to apply the 3rd write current pulse phase-change memory cell is programmed for amorphous state and apply the 4th write current pulse so that phase-change memory cell is programmed for crystalline state.Described phase change memory device further comprises: restore circuit, under low-power mode, operate, with the first write current pulse choice be applied to phase-change memory cell, to recover the amorphous state of phase-change memory cell.
In accordance with a further aspect of the present invention, provide a kind of phase change memory device that can under non-volatile memories pattern and volatile storage pattern, operate.This phase change memory device comprises: phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state; And restore circuit, under the volatile storage pattern, recover the amorphous state of phase-change memory cell at least.
According to a further aspect in the invention, provide a kind of phase change memory device, having comprised: data wire; Many I/O lines; Multiple bit lines; Many word lines; With a plurality of phase-change memory cells at the intersection point place that is positioned at word line and bit line, wherein, each described phase-change memory cell all is included in programmable material bodies between amorphous state and the crystalline state.Phase change memory device also comprises: the write current source, voltage according to data wire outputs to bit line with the first and second write current pulses, the first write current pulse is used for phase-change memory cell is programmed for amorphous state, and the second write current pulse is used for phase-change memory cell is programmed for crystalline state.Phase change memory device further comprises: a plurality of sense amplifiers, be connected respectively to bit line and I/O line, and it reads each state of phase-change memory cell; And restore circuit, being connected to I/O line and data wire, the voltage of its control data line is to recover the amorphous state of phase-change memory cell at least.
According to a further aspect in the invention, a kind of method to the phase-change memory cell programming is provided, described method comprises: optionally the first and second write current pulses are applied to phase-change memory cell, the first write current pulse is used for phase-change memory cell is programmed for amorphous state, and the second write current pulse is used for phase-change memory cell is programmed for crystalline state.This method also comprises: the state that detects phase-change memory cell; With when phase-change memory cell is detected as amorphous state, carry out first recovery operation by once more the first write current pulse being applied to phase-change memory cell.
Description of drawings
Above-mentioned and others of the present invention and feature will be more obvious by detailed description with the accompanying drawing hereinafter, wherein:
Fig. 1 shows the schematic diagram of the phase-change memory cell that changes between SET and the RESET state;
The temperature that Fig. 2 shows chalcogenide phase change unit in SET and the RESET operating process changes in time;
Fig. 3 is the curve chart of the V-I characteristic of phase-change memory cell;
Fig. 4 is the circuit diagram of two element circuits that is applied to the phase change memory device of the embodiment of the invention;
Fig. 5 is the flow chart of volatile storage pattern according to an embodiment of the invention;
Fig. 6 is the circuit diagram of the phase change memory device in the one embodiment of the invention;
Fig. 7 is the block diagram of current source of the phase change memory device of one embodiment of the invention; With
Fig. 8 (A) and 8 (B) show the curve chart that phase-change memory cell according to an embodiment of the invention is in the V-I characteristic of non-volatile pattern and volatibility pattern respectively.
Embodiment
Embodiment below with reference to several preferred indefinitenesses describes the present invention in detail.
As mentioned above, traditional phase transition storage is non-volatile device, comprises that for amorphous phase transformation transition process orderly nucleus forms and growth step.On the contrary, Partial Feature of the present invention at least is the operation under the volatile storage pattern (or low-power mode), under this pattern, only comprises nucleating process to amorphous transformation.In addition, under the volatibility pattern, amorphous state writes with crystalline state and writes the write current that all produces well below traditional devices.Reduced energy consumption significantly.And, in the combined resistance ratio that has reduced between amorphous state and the crystalline state, also be enough to data are read.
For instance, following table 1 shows the write current under the volatibility of the present invention and non-volatile pattern under the situation that adopts the chalcogenide phase change unit material.
Table 1
| Pattern | Crystalline phase | Write current | Pulse duration |
| Non-volatile | Amorphous state | ????2mA | ????20ns |
| Non-volatile | Crystalline state | ????1.2mA | ????50ns |
| Volatibility | Amorphous state | ????＜0.5mA | ????20ns |
| Volatibility | Crystalline state | ????＜0.3mA | ????50ns |
Shown in the example in the table 1, the write current amperage under the volatibility pattern is significantly less than the amperage under the non-volatile pattern.In addition, under two patterns, the amperage of amorphous state (RESET) write current pulse is greater than the amperage of crystalline state (SET) write current pulse, and the pulse duration of amorphous state write current pulse is less than the pulse duration of crystalline state write current pulse.
Yet under the volatibility pattern, the amperage that RESET writes pulse needn't surpass the amperage of SET pulse.For example, the RESET pulse can have identical amperage with the SET pulse, but can have different pulse durations and different quenching times.
Should be noted that employed wording " amorphous state " has relative implication here, it means that the major part of material is in amorphous state rather than crystalline state, and perhaps amorphous degree of material is higher than the degree of its crystalline state.In either event, particularly under the volatibility pattern, material or part material all needn't be most of or mainly decrystallized.On the contrary, the low write current under the volatibility pattern only needs to change crystal structure to produce enough resistance ratios between amorphous state and crystalline state.
Form owing in the amorphous state ablation process, only carry out nucleus, so data maintenance process shortens.Yet,,, compensated the data hold time that shortens by at least periodically recovering the amorphous state of phase change cells according to the present invention.
Fig. 4 is the circuit diagram that is used for the two element circuits in the phase change memory device of the embodiment of the invention.In this structure, be that amorphous two unit of low resistance crystalline state and high resistance merge by the opposite logic states that has that will write, physics realization a data bit.The occupation mode of each two unit of data bit has enlarged the device operation window, has avoided the error that is caused by distribution of resistance.
In Fig. 4, a data bit is stored among phase change cells PCELLi1 and the PCELLi2, and another data bit is stored among phase change cells PCELLj1 and the PCELLj2.Phase change cells PCELLi1 and transistor PTRi1 connect between reference voltage (being ground connection) and bit line BL, and phase change cells PCELLi2 and transistor PTRi2 connect between reference voltage and anti-phase bit line/BL.Equally, phase change cells PCELLj1 and transistor PTRj1 connect between reference voltage and bit line BL, and phase change cells PCELLj2 and transistor PTRj2 connect between reference voltage and anti-phase bit line/BL.The grid of transistor PTRi1 and transistor PTRi2 is connected to word line Wli, and the grid of transistor PTRj1 and PTRj2 is connected to another word line Wlj.
Current source ISET1 and current source ISET2 respectively the SET current impulse is provided to bit line BL and/BL.Oxide-semiconductor control transistors CTR and/CTR be linked in sequence respectively bit line BL and/end of BL, current source IRESET provides RESET current impulse to it. Clamp circuit 210 and 220 be connected respectively to bit line BL and/other end of BL, sense amplifier S/A is connected to clamp circuit 210 and 220.
To describe the write operation of two element circuits of Fig. 4 now in detail.Here logic of propositions value " 1 " is written to first combination of unit PCELLi1 and PCELLi2.In this case, word line Wli is set at HIGH, data-signal D and/D is respectively HIGH and LOW.Like this, transistor PTRi1, PTRi2 and CTR all connect, and transistor/CTR ends.
Because transistor/CTR for ending, therefore, has only SET current impulse ISET2 by PCELLi2 and transistor PTRi2.SET current impulse ISET2 places SET (crystal) state with PCELLi2.The SET state is a low resistance state, and this state is considered to have logical value " 0 ".
On the other hand, because transistor CTR is connection, therefore, RESET current impulse IRESET is also by PCELLi1 and transistor PTRi1.Though it is not shown among Fig. 4,, current impulse ISET1 is controlled by RESET current impulse IRESET, and synchronous with it, thus the pulse duration of ISET1 is with regularly identical with IRESET.Thus, IRESET and ISET1 are synthesized so that phase change cells to be set, and make it that PCELLi1 is placed RESET (noncrystal) state.The RESET state is a high-impedance state, and this state is considered to have logical value " 1 ".
In read operation, clamp circuit 210 and 220 with bit line BL and/ voltage limit on the BL is less than threshold voltage, minimize with disturbance reading device.In this state, suppose that once more Wli is HIGH, it is low current that the Low ESR of PCELLi2 will cause the electric current on bit line/BL, is high electric current and the high impedance of PCELLi1 will cause the electric current on the bit line BL.Each bit line BL and/these electric currents of BL compare the logical value with first combination of identification phase change cells PCELLi1 and PCELLi2 in sense amplifier S/A.
Fig. 5 is the volatibility model process figure that is used to explain the operation of phase transition storage according to an embodiment of the invention.In first step 310, read the data that are stored in phase transformation (PRAM) unit.For example, in the structure of Fig. 4, in sense amplifier S/A with each bit lines BL and/electric current of BL compares the logical value with identification phase change cells PCELLi1 and PCELLi2.Then, in second step 320, reading of data outwards transmits and is used to recover read the state of PRAM unit.For example, in the structure of Fig. 4, reading of data as data-signal D and/D, rewrite identical data with among the unit PCELLi1 that formerly reads and the PCELLi2.
The recovery of reading the state of phase change cells can occur in each read operation of phase change cells.Perhaps, recovery can take place with each equi-spaced apart, and for example, be more than one hour or one hour blanking time.
Fig. 6 shows phase change memory device according to an embodiment of the invention.As shown in the figure, phase change memory device comprise current source 440, data circuit 420, bit line to BL1 ,/BL1 ... BLm ,/BLm, phase change memory array piece 410, read circuit 430, local I/O line LIO and/LIO, I/O sense amplifier 450, change over switch SWTR and shared I/O line GIO and/GIO.
Phase change memory array piece 410 comprises and is positioned at word line WL1 ... WLn and bit line to BL1 ,/BL1 ... BLm ,/a plurality of phase-change memory cells at the intersection point place of BLm are right.Each memory cell is to connecting as described in Figure 4 all.
Read circuit 430 comprise a plurality of be connected to bit line to BL1 ,/BL1 ... BLm ,/Blm and local I/O line LIO and/read circuit STM1 between the LIO ... STMm.Read circuit STM1 ... STMm comprises each sense amplifier S/A1 ... S/Am and each transistor are to TTR11, TTR12 ... TTRm1, TTRm2.The right grid of transistor is connected to each control signal CD1 ... CDm.And, though not shown,, read circuit 430 can also comprise be connected to bit line BL1 ,/BL1 ... BLm ,/a plurality of clamp circuits (referring to Fig. 4) of Blm.
At last, I/O sense amplifier 450 and change over switch SWTR be connected on local I/O line LIO ,/LIO and shared I/O line GIO ,/GIO between.
Referring now to bit line BL1 ,/BL1 describes the write operation of the phase change memory device of Fig. 6 in detail.Here the logical value of hypothesis " 1 " is written to word line WL1 ... the bit line BL1 of selected word line among the WLn ,/phase change cells of BL1 in.In this case, selected word line is set at HIGH, data-signal D and/D is respectively HIGH and LOW.Like this, transistor CTR1 connects, and transistor/CTR1 ends.
Because transistor/CTR1 ends, therefore, has only SET current impulse ISET2 from the memory cell of bit line/BL1 through selected word line.SET current impulse ISET2 is changed to SET (crystal) state with the memory cell of bit line/BL1.The SET state is a low resistive state, and it is considered to have logical value " 0 ".
On the other hand, because transistor CTR1 connects, therefore, RESET current impulse IRESET and SET current impulse ISET2 pass through the memory cell of selected bit line BL1.Though it is not shown among Fig. 6,, current impulse ISET1 is controlled by RESET current impulse IRESET, and synchronous with it, and thus, the pulse duration of ISET1 is with regularly identical with IRESET.Therefore, IRESET and ISET1 are combined so that phase change cells is changed to RESET (noncrystal) state with PCELLi1.The RESET state is a high-impedance state, and it is considered to have logical value " 1 ".
Shown in the block diagram of Fig. 7, current source 440 can comprise high drive current source 701 and low drive current source 702.High drive current source 701 output IRESET, low drive current source 702 output ISET1 and ISET2.The value of IRSET, ISET1 and ISET2 and pulse duration are still finished drilling in the volatibility pattern in non-volatile pattern by electric current and are made decision.Below table 2 show embodiment under the situation that the storage array piece comprises the chalcogenide phase change memory cell.
Table 2
| Pattern | Data | IRESET+ ISET1 | IRSET+ ISET2 | ISET1 | ISET2 |
| Non-volatile | One writing | 2mA， 20ns | -- | -- | 1.2mA， 50ns |
| Non-volatile | Write " 0 " | -- | 2mA， 20ns | 1.2mA， 50ns | -- |
| Volatibility | One writing | ＜0.5mA 20ns | -- | -- | ＜0.3mA 50ns |
| Volatibility | Write " 0 " | -- | ＜0.5mA 20ns | ＜0.3mA 50ns | -- |
The read operation of the circuit of Fig. 6 can be carried out in conjunction with the described identical mode of Fig. 4 with above-mentioned.
Fig. 8 (A) shows the curve chart that phase-change memory cell is in the V-I characteristic under the non-volatile pattern, and Fig. 8 (B) shows the curve chart that phase-change memory cell is in the V-I characteristic under the volatibility pattern.Example has illustrated the situation of the phase-change material of chalcogenide alloy once more.Shown in Fig. 8 (A), read voltage less than O.5 the volt situation under, non-volatile pattern has presented the high resistance ratio between RSET and IRESET.At the high voltage place more than or equal to threshold voltage vt, the impedance Rdyn of two states is identical.On the other hand, shown in Fig. 8 (B), volatibility pattern threshold voltage vt is less than the threshold voltage of non-volatile pattern.And the volatibility pattern has presented the low resistance ratio between RSET and Rrset.But special under the situation that has adopted the two cell design shown in Fig. 4, this resistance ratio still is enough to be used in reading purpose.
With reference to figure 6, bit line/BL1 ... the data of the selected memory cell of/BLm are at array selecting signal CD1 ... be applied to local I/O line LIO under the control of CDm.And, in this embodiment, bit line/BL1 ... the data of the selected memory cell of/BLm are at array selecting signal CD1 ... be applied to local I/O line/LIO under the control of CDm.Data under the control of signal BAS through I/O sense amplifier 450 and change over switch SWTR be sent to shared I/O line GIO and/GIO.
As mentioned above, the volatibility pattern in the operating process is characterised in that: being stored in data in the phase-change memory cell, particularly to be in retention time of the data under the amorphous state shorter relatively.Therefore, the embodiment of Fig. 6 comprises the circuit that is used for recovery of stored data under the volatibility pattern.That is, under the control of RWCTRL signal, shared I/O line through transistor RTR1 and RTR2 selectively be connected to data wire D and/D.Under this state, be presented on sense data on bridging line GIO and the/GIO to be written in the memory cell array about the identical mode of the data that normally write with above-mentioned.Under the situation of operating under the non-volatile pattern, the RWCTRL signal is LOW at circuit, thus with data wire D and/D and shared I/O line GIO with/GIO is isolated.Under the situation of operating under the volatibility pattern, the RWCTRL signal is HIGH at circuit, thereby data wire D and/D and shared I/O line GIO are linked to each other with/GIO.So, data are resumed under the volatibility pattern.
Should understand, under the volatibility pattern, can with data wire D and/D replace be connected to local I/O line LIO and/LIO.
As mentioned above, the recovery operation under the volatibility pattern can be carried out when reading the data that are stored in the storage array 410 at every turn.Perhaps, recovery operation also can be carried out with equidistant interval, for example, and one hour or more than one hour.
Disclose typical preferred embodiment of the present invention in drawing and description, though set forth specific embodiment, the foregoing description only is for general narrative consideration, and is not used in qualification the present invention.Therefore, should understand, scope of the present invention is limited by additional claim, rather than is limited by exemplary embodiment.
Claims (44)
1. phase change memory device comprises:
Phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state;
The write current source optionally applies the first write current pulse described phase-change memory cell be programmed for amorphous state and apply the second write current pulse so that described phase-change memory cell is programmed for crystalline state; With
Restore circuit, with the described first write current pulse choice be applied to described phase-change memory cell, to recover the amorphous state of described phase-change memory cell.
2. phase change memory device according to claim 1 also comprises the circuit that reads of the programmable state that is used to read described phase-change memory cell, and wherein said restore circuit is by described output control of reading circuit.
3. phase change memory device according to claim 2, wherein when described output of reading circuit showed that described phase-change memory cell is in amorphous state, described restore circuit can be operated and be used for the described first write current pulse is applied to described phase-change memory cell.
4. phase change memory device according to claim 3, the wherein said output that reads circuit are the shared I/O line of memory device.
5. phase change memory device according to claim 3, wherein, the described output that reads circuit is the local I/O line of described phase change memory device.
6. phase change memory device according to claim 1, wherein, described material bodies is a chalcogenide alloy.
7. phase change memory device according to claim 1, the amperage of the wherein said first write current pulse is greater than the amperage of the described second write current pulse, and the pulse duration of the wherein said first write current pulse is less than the pulse duration of the described second write current pulse.
8. phase change memory device according to claim 1, the amperage of the wherein said first write current pulse is identical with the amperage of the described second write current pulse, and the pulse duration of the wherein said first write current pulse is different from the pulse duration of the second write current pulse, and the quenching time of the wherein said first write current pulse is different from the quenching time of the second write current pulse.
9. phase change memory device according to claim 1, wherein said memory device can switch between volatibility pattern and non-volatile pattern, and wherein, during described non-volatile pattern, forbid described restore circuit, during described volatibility pattern, enable described restore circuit.
10. phase change memory device comprises:
Phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state;
Operate under low-power mode in the write current source, optionally to apply the first write current pulse described phase-change memory cell be programmed for amorphous state and apply the second write current pulse so that described phase-change memory cell is programmed for crystalline state; With under high power, operate, optionally to apply the 3rd write current pulse described phase-change memory cell is programmed for amorphous state and apply the 4th write current pulse so that described phase-change memory cell is programmed for crystalline state; With
Restore circuit is operated under low-power mode, with the first write current pulse choice be applied to described phase-change memory cell, recover the amorphous state of described phase-change memory cell.
11. phase change memory device according to claim 10, wherein said low-power mode are the volatibility pattern of memory device, described high-power mode is the non-volatile pattern of memory device.
12. phase change memory device according to claim 10 also comprises the circuit that reads of the programmable state that is used to read described phase-change memory cell, wherein said restore circuit is by described output control of reading circuit.
13. phase change memory device according to claim 12, the wherein said output that reads circuit are the shared I/O line of memory device.
14. phase change memory device according to claim 12, the wherein said output that reads circuit are the local I/O line of phase change memory device.
15. phase change memory device according to claim 12, wherein, when described output of reading circuit shows that described phase-change memory cell is in amorphous state, can under low-power mode, operate restore circuit so that the described first write current pulse is applied to described phase-change memory cell.
16. phase change memory device according to claim 10, wherein said material bodies are chalcogenide alloy.
17. phase change memory device according to claim 10, the amperage of the wherein said first write current pulse is greater than the amperage of the described second write current pulse, and the pulse duration of the wherein said first write current pulse is less than the pulse duration of the described second write current pulse.
18. phase change memory device according to claim 10, the amperage of the wherein said first write current pulse and described second write current pulsion phase amperage together, the pulse duration of the wherein said first write current pulse is different from the pulse duration of the described second write current pulse, and the quenching time of the wherein said first write current pulse is different from the quenching time of the described second write current pulse.
19. phase change memory device according to claim 10, the amperage of the wherein said third and fourth write current pulse is greater than the amperage of the first and second write current pulses.
20, a kind of under non-volatile memories pattern and volatile storage pattern exercisable phase change memory device, comprising: phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state; And restore circuit, be used under the volatile storage pattern, recovering at least the amorphous state of phase-change memory cell.
21. phase change memory device according to claim 20, the state of wherein said phase-change memory cell does not recover under the non-volatile memories pattern.
22. phase change memory device according to claim 20, wherein when described material bodies was programmed to be in amorphous state, the material bodies that is less than under the non-volatile pattern for the part of amorphous of the material bodies under the volatibility pattern was the part of amorphous.
23. phase change memory device according to claim 20, wherein when described material bodies was programmed to be in crystalline state, the part of material bodies was higher than the non-crystallization degree of this part under the volatibility pattern at the non-crystallization degree under the non-volatile pattern.
24. phase change memory device according to claim 20 also comprises the circuit that reads of the programmable state that is used to read phase-change memory cell, wherein said restore circuit is by described output control of reading circuit.
25. phase change memory device according to claim 24, wherein when described output of reading circuit showed that described phase-change memory cell is in amorphous state, described restore circuit can be operated the amorphous state that is used for recovering described phase-change memory cell.
26. phase change memory device according to claim 25, wherein when described output of reading circuit showed that described phase-change memory cell is in crystalline state, described restore circuit can be operated the crystalline state that is used for recovering described phase-change memory cell.
27. phase change memory device according to claim 24, the wherein said output that reads circuit are the shared I/O line of memory device.
28. phase change memory device according to claim 24, the wherein said output that reads circuit are the local I/O line of phase change memory device.
29. phase change memory device according to claim 20, wherein said material bodies are chalcogenide alloy.
30. a phase change memory device comprises:
Data wire;
Many I/O lines;
Multiple bit lines;
Many word lines;
Be positioned at a plurality of phase-change memory cells at described word line and bit line bit line intersection point place, wherein each described phase-change memory cell all is included in programmable material bodies between amorphous state and the crystalline state;
The write current source, voltage according to described data wire outputs to described bit line with the first and second write current pulses, the described first write current pulse is used for phase-change memory cell is programmed for amorphous state, and the described second write current pulse is used for phase-change memory cell is programmed for crystalline state;
A plurality of sense amplifiers are connected respectively to described bit line and described I/O line, are used to read each state of described phase-change memory cell; With
Restore circuit is connected to described I/O line and described data wire, is used to control the voltage of described data wire, to recover the amorphous state of phase-change memory cell at least.
31. phase change memory device according to claim 30, wherein said restore circuit is also controlled the voltage of described data wire, to recover the crystalline state of described phase-change memory cell.
32. phase change memory device according to claim 30, wherein said memory device can switch under volatibility and non-volatile pattern, wherein forbids enabling described restore circuit by described restore circuit under the volatibility pattern under non-volatile pattern.
33. phase change memory device according to claim 32, wherein said write current source outputs to bit line with the first and second write current pulses under the volatile storage pattern, and wherein, the described also output third and fourth write current pulse under non-volatile pattern of write current source.
34. phase change memory device according to claim 33, the amperage of the wherein said first write current pulse are greater than the amperage of the described second write current pulse, the pulse duration of the wherein said first write current pulse is less than the pulse duration of the second write current pulse.
35. phase change memory device according to claim 33, the amperage of the wherein said first write current pulse and described second write current pulsion phase amperage together, the pulse duration of the wherein said first write current pulse is different from the pulse duration of the described second write current pulse, and the quenching time of the wherein said first write current pulse is different from the described second write current pulse quenching time.
36. phase change memory device according to claim 33, the amperage of the wherein said third and fourth write current pulse is greater than the amperage of the first and second write current pulses.
37. phase change memory device according to claim 30, wherein the material bodies of each described phase-change memory cell all is a chalcogenide alloy.
38. the method to the phase-change memory cell programming, described phase-change memory cell is included in programmable material bodies between amorphous state and the crystalline state, and described method comprises:
With the first and second write current pulse choice be applied to described phase-change memory cell, the described first write current pulse is used for phase-change memory cell is programmed for amorphous state, the described second write current pulse is used for phase-change memory cell is programmed for crystalline state;
Detect the state of described phase-change memory cell; With
When described phase-change memory cell is detected as amorphous state, carry out first recovery operation by once more the described first write current pulse being applied to described phase-change memory cell.
39. according to the described method of claim 38, wherein when phase-change memory cell is detected as amorphous state, the status detection step of phase-change memory cell occurs in when reading described phase-change memory cell at every turn, and wherein, first recovery operation occurs in when reading phase-change memory cell at every turn.
40. according to the described method of claim 38, the status detection step of wherein said phase-change memory cell occurs in each described when reading phase-change memory cell, and wherein, described first or second recovery operation occurs in each described when reading phase-change memory cell.
41. according to the described method of claim 38, wherein when described phase-change memory cell was detected as amorphous state, the status detection step of described phase-change memory cell repeated to take place with equidistant interval, and wherein, first recovery operation takes place with equidistant interval.
42. according to the described method of claim 41, wherein said regular intervals was at least 60 minutes.
43. according to the described method of claim 38, wherein, the status detection step of described phase-change memory cell repeats to take place with equidistant interval, and wherein, first or second recovery operation takes place with equidistant interval.
44. according to the described method of claim 43, wherein said equi-spaced apart was at least 60 minutes.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR19257/2003 | 2003-03-27 | ||
| KR1020030019257A KR100546322B1 (en) | 2003-03-27 | 2003-03-27 | Phase-change memory device capable of being operated in both non-volatile memory and volatile memory and method thereof |
| KR19257/03 | 2003-03-27 | ||
| US10/788,407 | 2004-03-01 | ||
| US10/788,407 US7042760B2 (en) | 2003-03-27 | 2004-03-01 | Phase-change memory and method having restore function |
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| Publication Number | Publication Date |
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| CN1538540A true CN1538540A (en) | 2004-10-20 |
| CN100492694C CN100492694C (en) | 2009-05-27 |
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| CNB2004100352276A Expired - Fee Related CN100492694C (en) | 2003-03-27 | 2004-03-29 | Phase change merhory and method with recovery function |
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| JP (1) | JP4481697B2 (en) |
| CN (1) | CN100492694C (en) |
| DE (1) | DE102004016408B4 (en) |
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- 2004-03-29 JP JP2004096312A patent/JP4481697B2/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| DE102004016408B4 (en) | 2008-08-07 |
| CN100492694C (en) | 2009-05-27 |
| JP4481697B2 (en) | 2010-06-16 |
| DE102004016408A1 (en) | 2004-10-21 |
| JP2004296076A (en) | 2004-10-21 |
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