CN101335045B - Write circuit of phase-change memory - Google Patents
Write circuit of phase-change memory Download PDFInfo
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- CN101335045B CN101335045B CN2007101280673A CN200710128067A CN101335045B CN 101335045 B CN101335045 B CN 101335045B CN 2007101280673 A CN2007101280673 A CN 2007101280673A CN 200710128067 A CN200710128067 A CN 200710128067A CN 101335045 B CN101335045 B CN 101335045B
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Abstract
The invention provides a write circuit of a phase-change memory which comprises a drive current generating circuit used for providing the write circuit, a first switching device which is coupled with the drive current generating circuit, a first memory location which is coupled with the first switching device and a second switching device which is coupled with the first memory location and a ground level. When the drive current generating circuit outputs the write circuit to the first memory location, the second switching device is turned on after a first preset time after the first switching device is turned on.
Description
Technical field
The present invention relates to a kind of phase transition storage write circuit, particularly relate to the quick write circuit of the phase transition storage that uses single current source.
Background technology
Growth along with the portable use product, make the demand of nonvolatile memory that the trend that day by day increases be arranged, the phase transition storage technology is owing to have competitive characteristics such as speed, power, capacity, fiduciary level, process integration degree and cost, has been regarded as the non-volatile memory technologies of potentialization of next epoch.
The operation of phase transition storage mainly is to be applied on the phase transition storage by two kinds of different big or small current impulses, make phase transition storage because the effect of Ohmic heating, cause amorphous state (amorphous state) that regional area causes phase-change material because of different temperature changes with crystalline state (crystalline state) but anti-phase change, and reach the purpose of storage data by the different resistance values that this two phase transformations structure is presented.The current impulse synoptic diagram of Fig. 1 for generally phase transition storage being write and reads.When phase transition storage carries out the RESET operation, mainly be to apply the short and higher reset current I of pulse height of a pulse width
RESET, make the temperature of phase transition storage regional area can be higher than the melting temperature (T of phase-change material by applying of this pulse
m) and melt.When the zone of this thawing during in instantaneous temperature reduction, carry out crystallization again owing to have insufficient time to, therefore in the process of solidifying, can form amorphous state, this moment, phase-change material had high value.On the other hand, when phase transition storage carries out the SET operation, then be to utilize a pulse width broad and the lower setting electric current I of pulse height
SET, make the temperature of phase transition storage regional area between the Tc (T of phase-change material by applying of this pulse
c) and melting temperature (T
m) between, so then can be again by crystallization through the noncrystallineization zone after the SET operation.As mentioned above, the RESET of phase transition storage operation and SET operation promptly as writing in the storer (write) with wipe (erase) operation, at last by phase transition storage being operated in the effect that resistance difference between crystalline state and the amorphous state reaches storage.When the data in the reading phase change memories, then utilize a size of current less than I
SETRead electric current I
ReadJudge its resistance value, to learn the data of its storage.
Figure 2 shows that a kind of SET signal schematic representation of known phase transition storage.This SET signal comprises one first crystallization current impulse I
SET1With one second crystallization current impulse I
SET2This first crystallization current impulse I
SET1Has one first current peak I
P1, and this first current peak I
P1To hold time be first t that holds time
1, this second crystallization current impulse I
SET2Has one second current peak I
P2, and the second current peak I
P2To hold time be second t that holds time
2
Known SET signal carries out the operation of crystallization (SET) by the combination of two different current impulses, utilizes first current peak I
P1Higher and first t that holds time
1Short pulse action can make phase-change material finish the crystallization of regional area earlier, then utilizes second the current peak I that follows again
P2Less and second t that holds time
2Long pulse action realizes the crystallization of finishing of phase-change material.Utilize such crystallization method of operating that more stable fiduciary level (reliability) characteristic can be provided, and great help is also arranged for the homogeneity distribution of lifting subassembly.
Fig. 3 is the current generating circuit synoptic diagram of the SET signal of a kind of known generation such as Fig. 2.First current generator 31 and second current generator 32 are coupled to totalizer 35 by one first diode 33 and one second diode 34 respectively, in order to the SET signal of output as Fig. 2.First current generator, 31 outputs, one first current impulse, its size is I
P1-I
P2, second current generator, 32 outputs, one second current impulse, its size is I
P2First current generator 31 and second current generator 32 are exported first current impulse and second current impulse to produce the first crystallization current impulse I simultaneously according to control signal S1 and S2
SET1And keep t
1Time, then control signal S1 forbidden energy (disable) first current generator 31 makes it stop to export first current impulse.Control second current generator, 32 outputs, second current impulse to produce the second crystallization current impulse I by control signal S2 this moment again
SET2And keep t
2Time.Just can produce SET signal thus as Fig. 2.
Summary of the invention
Purpose of the present invention is for providing a kind of quick write circuit of phase transition storage of using single current source, and the available write current of this write circuit can make phase transition storage be melted earlier after crystallization again.
The invention provides a kind of write circuit of phase transition storage, comprise that a drive current produces circuit, in order to a write current to be provided; One first switchgear couples this drive current and produces circuit; One first storage unit couples this first switchgear; And a second switch device, couple this first storage unit and a ground level.When this drive current generation circuit is exported this write current to this first storage unit, the conducting after one first schedule time after this first switchgear conducting of this second switch device.
Description of drawings
Fig. 1 is a kind of current impulse synoptic diagram that phase transition storage is write and reads.
Figure 2 shows that a kind of write signal synoptic diagram of known phase transition storage.
Fig. 3 is the current generating circuit synoptic diagram of the write signal of a kind of known generation such as Fig. 2.
Fig. 4 has the write paths synoptic diagram that a storer of the present invention writes control circuit.
Fig. 5 is the circuit diagram that produces an embodiment of circuit according to a drive current of the present invention.
Fig. 6 has the write paths synoptic diagram that another storer of the present invention writes control circuit.
Fig. 7 is the circuit diagram that produces another embodiment of circuit according to a drive current of the present invention.
The reference numeral explanation
31～the first current generators
32～the second current generators
41～drive current produces circuit
42～the first switchgears
43～transmission gate
44～PCM storage unit
45～second switch device
51～multiplexer
61～drive current produces circuit
62～the first switchgears
63～transmission gate
64～PCM storage unit
65～second switch device
66～electric capacity
71～multiplexer
Embodiment
In order to make phase transition storage when carrying out the crystallization operation, advantages of higher stability can be arranged and the homogeneity of whole phase transition storage to be improved, known crystallization operation elder generation imports after the high current elder generation fusing phase transition storage phase transition storage, exports a reduced-current again and makes the phase transition storage crystallization.For realizing this purpose, known technology utilizes a plurality of current sources or special current generating circuit to realize mostly, this all can increase complicacy on circuit design, therefore the invention provides phase transition storage write circuit, and can realize the purpose that known technology will be realized with single current source.
Fig. 4 has the write paths synoptic diagram that a storer of the present invention writes control circuit.Drive current produces circuit 41 and couples a bias circuit (not drawing on the figure) in order to export a write current.First switchgear 42 couples this drive current and produces circuit 41, and is controlled by a control signal S1, and determines whether conducting according to control signal S1.Transmission gate 43 couples this first switchgear 42, and is controlled by a control signal AP, and determines whether conducting according to control signal AP.In the present embodiment, transmission gate 43 comprises a CMOS transistor.PCM storage unit 44 is coupled between transmission gate 43 and the second switch device 45, and determines its logic state according to the size of current of this write current.Second switch device 45 couples this PCM storage unit 44, and is controlled by a control signal S2, and determines whether conducting according to control signal S2.When drive current produces circuit 41 output write currents, 42 conductings of first switchgear, and second switch device 45 schedule time Δ t after 42 conductings of first switchgear
WLBack conducting utilizes such mode of operation, just can make write current T for some time
PeriodGreater than reset current I
RESET
Table one is according to above-mentioned writing mechanism, is applied in a simulation result that writes control circuit as the storer of Fig. 4.Δ t
WLBe the time of second switch device 45 to the first switchgears 42 late conductings.T
PeriodFor write current greater than reset current I
RESETTime.I
MAXIt then is the peak-peak of write current.Can find by analog result, can utilize and adjust Δ t
WLSize, control T
PeriodLength, make phase transition storage to be melted earlier after crystallization again.And can adjust Δ t
WLThe size degree that decides phase transition storage to be melted.
Table one
| Δt WL | T period | I MAX |
| 0? | 22.8ns? | 378μA? |
| 10ns? | 32.7ns? | 403μA? |
| 20ns? | 42.3ns? | 408μA? |
| 30ns? | 48.7ns? | 409μA? |
| 40ns? | 50.9ns? | 410μA? |
| 50ns? | 51.9ns? | 410μA? |
Fig. 5 is the circuit diagram that produces an embodiment of circuit 41 according to a drive current of the present invention.Drive current produces circuit 41 can couple two write paths, has comprised one or more storage unit on each write paths, and according to control signal I
Con_LWith I
Con_RDecide output write current I
O_LOr I
O_RDo not produce when writing reference current when drive current produces circuit 41, this moment, control signal bp_a was a high-voltage level with bp_b, and transistor T 51 is cut off with T52, and multiplexer 51 is exported a high voltage V
DD, in order to "off" transistor T54 and T55.When producing circuit 41 generations, drive current writes reference current, but when not exporting write current, this moment, control signal bp_a and bp_b were low voltage level, after transistor T 51 is switched on T52, transistor T 58, T59 and T54 also are switched on, and this moment, multiplexer 51 was accepted control signal S
SetControl, drain electrode end (Drain) level of T60 is transmitted and turn-on transistor T55.When producing circuit 41 generations, drive current writes reference current, and during the output write current, this moment, control signal bp_a and bp_b were low voltage level, after transistor T 51 is switched on T52, transistor T 58, T59 and T54 also are switched on, and this moment, multiplexer 51 was accepted control signal S
SetControl, drain electrode end (Drain) level of T60 is transmitted and turn-on transistor T55, and again according to control signal I
Con_LWith I
Con_RDecide output write current I
O_LOr I
O_RIn the present embodiment, can be by oxide-semiconductor control transistors T56 and the time Δ t of T57 than transistor T 55 and the late conducting of T54
SetAdjust write current greater than reset current I
RESETTime.
For more clearly demonstrating, please refer to table two.Table two is according to above-mentioned writing mechanism, is applied in a simulation result that writes control circuit as the storer of Fig. 4.In the present embodiment, the fixing time Δ t of second switch device 45 to the first switchgears 42 late conductings
WLBe 10ns.Δ t
SetFor multiplexer receives control signal S
SetHow long after, transistor T 56 just is switched on T57.Can find by analog result, can be at Δ t
WLUnder the fixing situation, utilize and adjust Δ t
SetSize, control T
PeriodLength, make phase transition storage to be melted earlier after crystallization again.And can adjust Δ t
SetThe size degree that decides phase transition storage to be melted.
Table two
| Δt set | T period | I MAX |
| 60ns? | 151.4ns? | 410μA? |
| 85ns? | 127.1ns? | 410μA? |
| 110ns? | 103.1ns? | 410μA? |
| 135ns? | 79.3ns? | 410μA? |
| 160ns? | 57.8ns? | 410μA? |
| 1000ns? | 32.7ns? | 403μA? |
Fig. 6 has the write paths synoptic diagram that another storer of the present invention writes control circuit.Drive current produces circuit 61 and couples a bias circuit (not drawing on the figure) in order to export a write current.First switchgear 62 couples this drive current and produces circuit 61, and is controlled by a control signal S1, and determines whether conducting according to control signal S1.Transmission gate 63 couples this first switchgear 62, and is controlled by a control signal AP, and determines whether conducting according to control signal AP.In the present embodiment, transmission gate 63 comprises a CMOS transistor.PCM storage unit 64 is coupled between transmission gate 63 and the second switch device 65, and determines its logic state according to the size of current of this write current.Second switch device 65 couples this PCM storage unit 64, and is controlled by a control signal S2, and determines whether conducting according to control signal S2.One end of electric capacity 66 is coupled between this first switchgear 62 and this PCM storage unit 64, and the other end is ground connection then.The 3rd switchgear 67 couples this first switchgear 62, and is controlled by a control signal S3, and determines whether conducting according to control signal S3.In the present embodiment, can control the length of Tperiod by the capacitance size of adjusting electric capacity 66, make phase transition storage to be melted earlier after crystallization again.
For more clearly demonstrating, please refer to table three.Table three is according to above-mentioned writing mechanism, is applied in a simulation result that writes control circuit as the storer of Fig. 6.Under the restriction of the simulated conditions of table three, the fixing time Δ t of second switch device 65 to the first switchgears 62 late conductings
WLBe 10ns.Can find by analog result, can be at Δ t
WLUnder the fixing situation, utilize the size of the capacitance size of adjusting electric capacity 66, control T
PeriodLength, make phase transition storage to be melted earlier after crystallization again.And the degree that the capacitance size that can adjust electric capacity 66 decides phase transition storage to be melted.
Table three
| Capacitance | T period | I MAX |
| 0p? | 32.6ns? | 403μA? |
| 1p? | 39.8ns? | 404μA? |
| 2p? | 47.3ns? | 405μA? |
| 3p? | 55.0ns? | 405μA? |
| 4p? | 62.1ns? | 405μA? |
| 5p? | 69.6ns? | 406μA? |
Fig. 7 is the circuit diagram that produces an embodiment of circuit 61 according to a drive current of the present invention.Drive current produces circuit 61 can couple two write paths, has comprised one or more storage unit on each write paths, and according to control signal I
Con_LWith I
Con_RDecide output write current I
O_LOr I
O_RDo not produce when writing reference current when drive current produces circuit 61, this moment, control signal bp_a was a high-voltage level with bp_b, and transistor T 71 is cut off with T72, and multiplexer 71 is exported a high voltage V
DD, in order to "off" transistor T74 and T75.When producing circuit 61 generations, drive current writes reference current, but when not exporting write current, this moment, control signal bp_a and bp_b were low voltage level, after transistor T 71 is switched on T72, transistor T 78, T79 and T74 also are switched on, and this moment, multiplexer 71 was accepted control signal S
SetControl, drain electrode end (Drain) level of T80 is transmitted and turn-on transistor T75.When producing circuit 61 generations, drive current writes reference current, and during the output write current, this moment, control signal bp_a and bp_b were low voltage level, after transistor T 71 is switched on T72, transistor T 78, T79 and T74 also are switched on, and this moment, multiplexer 71 was accepted control signal S
SetControl, drain electrode end (Drain) level of T80 is transmitted and turn-on transistor T75, and this moment is again according to control signal I
Con_LWith I
Con_RDecide output write current I
O_LOr I
O_ROne end of capacitor C 1 is coupled in the output terminal of transistor T 76, and the other end of capacitor C 1 is ground connection then.One end of capacitor C 2 is coupled in the output terminal of transistor T 77, and the other end of capacitor C 2 is ground connection then.In the present embodiment, can utilize the capacitance size of adjusting capacitor C 1 and capacitor C 2 to adjust T
PeriodTime length.In the present embodiment, though transistor T 71 to T79 is the example explanation with PMOS transistor or nmos pass transistor, but those skilled in the art can be replaced by the PMOS transistor nmos pass transistor or nmos pass transistor is replaced by the PMOS transistor, and circuit is made suitable modification.
Though the present invention discloses as above with specific embodiment; so it is only in order to be easy to illustrate technology contents of the present invention; and be not in order to limit the present invention; those skilled in the art; under the premise without departing from the spirit and scope of the present invention; when can doing some changes and modification, so protection scope of the present invention is as the criterion when the claim with the application.
Claims (8)
1. the write circuit of a phase transition storage comprises:
One drive current produces circuit, in order to a write current to be provided;
One first switchgear couples this drive current and produces circuit;
One first storage unit couples this first switchgear; And
One second switch device, couple this first storage unit and a ground level, when this drive current generation circuit is exported this write current to this first storage unit, the conducting after one first schedule time after this first switchgear conducting of this second switch device, make in a special time this write current greater than a reset current, and this write current read electric current less than this reset current and greater than one after this special time.
2. the write circuit of phase transition storage as claimed in claim 1 wherein also comprises a transmission gate, is coupled between this first switchgear and this first storage unit.
3. the write circuit of phase transition storage as claimed in claim 1, wherein this drive current produces circuit and also comprises:
One current generating unit; And
One output switch, wherein when this current generating unit was exported this write current, this output switch was delayed for one second schedule time and is exported this write current.
4. the write circuit of phase transition storage as claimed in claim 1 wherein also comprises one second storage unit, and has only one in this first storage unit and this second storage unit can receive this write current at one time.
5. the write circuit of phase transition storage as claimed in claim 1, wherein this drive current produces circuit and also comprises:
One output switch couples this first switchgear, has a conduction terminal, and when this conduction terminal received one first voltage, this output switch conduction was also exported this write current; And
One multiplexer receives this first voltage and one second voltage, is controlled by one first control signal, and when this multiplexer received this first control signal, this multiplexer was exported this first voltage and exported switch to this.
6. the write circuit of phase transition storage as claimed in claim 5, wherein when this output switch conduction, this first switchgear is delayed the conducting of one second schedule time and is transmitted this write current to this storage unit.
7. the write circuit of phase transition storage as claimed in claim 1 wherein also comprises an electric capacity, is coupled between this first switchgear and this ground level.
8. the write circuit of phase transition storage as claimed in claim 1 wherein also comprises one the 3rd switchgear, couples this electric capacity and this first switchgear, and when this first switchgear was switched on, the 3rd switchgear was switched on.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101280673A CN101335045B (en) | 2007-06-27 | 2007-06-27 | Write circuit of phase-change memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101280673A CN101335045B (en) | 2007-06-27 | 2007-06-27 | Write circuit of phase-change memory |
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| CN101335045A CN101335045A (en) | 2008-12-31 |
| CN101335045B true CN101335045B (en) | 2011-03-09 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
| TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
| TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
| CN102592671B (en) * | 2012-02-17 | 2015-06-17 | 北京时代全芯科技有限公司 | Write circuit for phase change memories and write method thereof |
| CN104715792B (en) * | 2013-12-11 | 2017-12-15 | 中国科学院上海微***与信息技术研究所 | Phase transition storage with function of initializing, which is write, wipes circuit and its fast literary sketch wiping method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538540A (en) * | 2003-03-27 | 2004-10-20 | 三星电子株式会社 | Phase change merhory and method with recovery function |
| CN1897156A (en) * | 2005-07-13 | 2007-01-17 | 三星电子株式会社 | Phase change random access memory (pram) device having variable drive voltages |
| WO2007034542A1 (en) * | 2005-09-21 | 2007-03-29 | Renesas Technology Corp. | Semiconductor device |
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2007
- 2007-06-27 CN CN2007101280673A patent/CN101335045B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1538540A (en) * | 2003-03-27 | 2004-10-20 | 三星电子株式会社 | Phase change merhory and method with recovery function |
| CN1897156A (en) * | 2005-07-13 | 2007-01-17 | 三星电子株式会社 | Phase change random access memory (pram) device having variable drive voltages |
| WO2007034542A1 (en) * | 2005-09-21 | 2007-03-29 | Renesas Technology Corp. | Semiconductor device |
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