CN1495872A - 直接芯片连接的结构和方法 - Google Patents
直接芯片连接的结构和方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 55
- 238000003466 welding Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000000155 melt Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 10
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000004020 conductor Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241001269238 Data Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
一种半导体封装(101)具有管芯(1)、引线框(4)、键合焊盘(6)、密封体(3)以及线键合球(2)。通过键合键合线(7)的一端在键合焊盘上形成线键合球,并除去键合线的其余部分。参考引线框上的基准(5)记录焊接线键合球的位置(23)。密封体覆盖管芯、熔敷金属以及引线框的管芯焊接标记(24)。在除去密封体处露出线键合球。形成线键合球时,通过记录的坐标确定露出线键合球制成开口(17)的位置。镀覆露出的线键合球,形成电连接到管芯的引出端。
Description
技术领域
本申请一般涉及半导体器件,具体涉及薄外形封装的半导体器件。
背景技术
在半导体器件的制造中,半导体管芯安装在密封的封装内。不导电的密封体环绕管芯保护管芯不受损伤和污染。此外,封装提供了将制备在管芯上的电路连接到如印制电路板的外部电路的引出端***。
常规的管芯具有带一个电极或没有电路的背面以及其上制备有部件或集成电路的上表面。借助位于上表面上的键合焊盘电访问部件,键合焊盘以多种图形排列在管芯的边缘和管芯的中央附近。
通常,封装工艺中的初始步骤为将薄板材制成的引线框固定到管芯的背面。金属线的一端球键合到键合焊盘,金属线的另一端针脚式键合到电连接外部电路的引线框的一个引出端。
现在封装已发展超越了仅使用引线框将管芯上的集成电路连接到外部电路。称做直接芯片焊接(DCA)的封装具有的引线框具有接触管芯一个表面的一个引出端并使用直接形成在相对的管芯表面上的导电焊料突点作为其它引出端。
与DCA有关的缺点之一是需要附加的制造步骤在管芯金属化上形成下阻挡金属结构以防止焊料沾污管芯。
与DCA封装的管芯和引线框的外部连接通常用焊料突点制成。当DCA器件需要与管芯的背面连接时,引线框弯曲由此引线框的突点几乎形成在与管芯突点的相同平面中,以便确保所有的引出端均匀地接触***电路板。然而,以前的DCA器件由于管芯与引线框未对准造成低成品率,导致引线框突点和管芯突点相互未对准造成低成品率。即使管芯正确地放置在引线框上,当回流如焊料等的管芯焊接材料时,由于管芯会相对于对准的引线框“浮动”,因此发生未对准。未对准降低了工艺成品率并增加了DCA器件的成本。
发明内容
因此,在本行业中需要一种半导体器件及提高DCA封装中成品率的方法,以减少器件的制造成本。
根据本发明的一方面,提供一种半导体器件的制造方法,包括以下步骤:将半导体管芯连接到引线框;以及参考引线框上的一点的位置处将线键合球形成在半导体管芯上以制成半导体器件的一个引出端。
根据本发明的另一方面,提供一种半导体器件的制造方法,包括在引线框上一点确定的位置处从半导体器件密封体上选择性除去材料的步骤,以露出半导体管芯表面上的半导体器件的引出端。
根据本发明的又一方面,提供一种半导体器件的制造方法,包括以下步骤:在与引线框对准的位置处在半导体管芯的表面上形成第一熔敷金属以制备半导体器件的第一引出端。
附图说明
图1A示出了半导体器件的剖面图;
图1B示出了半导体器件的俯视图;
图1C示出了备选实施例中的半导体器件的俯视图;
图2示出了第二备选实施例中的半导体器件的剖面图;
图3示出了选定的处理阶段之后的半导体器件的侧视图;
图4示出了定义的处理阶段之后第三备选实施例中的半导体器件的侧视图;
图5示出了第四备选实施例中的半导体器件的剖面图;
图6示出了使用激光的选定处理步骤的半导体器件的剖面图;
图7示出了使用喷水口的处理步骤的半导体器件的剖面图;以及
图8示出了第五备选实施例中的半导体器件的剖面图。
具体实施方式
在图中,具有相同参考数字的元件具有类似的功能。
图1A示出了包括半导体封装101和半导体管芯1的半导体器件100的剖面图。半导体器件100包括形成在半导体管芯1上的多个熔敷金属(deposit)2,起使外部电连接到半导体器件100的引出端的作用。在一个实施例中,熔敷金属2包括以下详细介绍的线键合球。半导体封装101包括引线框4、一个或多个标记(flag)8以及密封体3。
半导体管芯1具有形成将源电极连接到半导体器件100的源引出端26的键合焊盘6的顶面11以及安装在引线框4上的底面12,从而作为通过标记连接到与源引出端26共平面的漏引出端28的漏电极。在一个实施例中,半导体管芯1包括提供了大于约0.5安培漏电流的功率场效应晶体管。
密封体3包括用于保护半导体管芯1不受损伤或沾污的环氧树脂或其它标准的模制化合物。应该注意密封体不覆盖部分引线框4以便制造期间观看基准5。此外,露出熔敷金属2和标记8的一部分以便在半导体管芯1和外部电路之间发送电信号。
引线框4形成有主体24和电及机械地支撑漏引出端28的近似垂直的标记8。部分引线框4从密封体3延伸出并包括用作与引线框4对准的参考点的基准5。在熔敷金属2为用线键合设备设置的线键合球的实施例中,通过封装规格预先确定要放置熔敷金属2的位置23并存储在线键合设备的存储器中。
将管芯1安装在引线框4上之后,使用基准5作为参考在位置23形成熔敷金属2。因此,熔敷金属2与引线框4而不是半导体管芯1对准。熔敷金属2从表面11向上延伸作为半导体器件100的源引出端26并从标记8向上延伸作为漏引出端28。
在一个实施例中,熔敷金属2由使用标准的线键合设备(未示出)用金或铜键合线制成的线键合球形成。在一个实施例中,熔敷金属2使用回流的焊料球形成用于电及机械固定到键合焊盘6。熔敷金属2通常具有超出表面11约75微米到约1500范围内的高度。
熔敷金属2和标记8由称作镀层10的导电材料覆盖,以便于将半导体封装100焊接到母板。在一个实施例中,镀层包括锡铅焊料组合物、镍或类似的导电材料。镀层10包括露出的镀层表面下的任何阻挡金属,例如镍。密封体3具有表面14,平面化熔敷金属2以具有与下面介绍的表面14共平面的表面。由于熔敷金属2和表面共平面,形成镀层10从而伸出表面14以便于焊接到母板。
与半导体管芯1和引线框4的总厚度组合的熔敷金属2的小高度提供了比以前的器件总高度低的半导体器件100,同时维持了低制造成本。
图1B示出了半导体管芯1的边缘30基本平行于引线框4的对应边、半导体管芯1与引线框4理想地对准的半导体器件100的俯视图。栅极引出端27和源引出端26与熔敷金属2形成在所示的标准构图的半导体金属化膜上。漏引出端28通过标记8背面连接到管芯1。
图1C示出了管芯1未理想地对准由此半导体管芯1的边缘30旋转与所示的引线框4的边缘31形成非零角29的半导体器件100的俯视图。这种旋转或未对准由组件制造工艺的变化性造成。应该注意由于熔敷金属2参考基准5设置,因此分别用于源和栅极引出端26和27的位置23相对于基准5与处于图1B的理想对准条件下相同。类似地,分别用于源和栅极引出端26和27的位置23相对于漏引出端28与处于图1B的理想对准条件下相同。管芯旋转的量,即角度29的尺寸可以多达5度或更多。
图2示出了备选实施例中的半导体器件100的剖面图。除了熔敷金属2形成在每个标记8的顶部之外,元件的功能和结构类似于以前介绍的,由此将熔敷金属2提供在标记8和外部电路之间。当镀层10需要相同的结构时,使用形成在标记8上的熔敷金属2。
图3示出了管芯1焊接到引线框4之后选定的处理阶段之后的半导体器件100。线键合设备的毛细管38将键合线7分配到管芯1的键合焊盘6。金属线7熔化形成通常的球形,然后焊接到键合焊盘6作为熔敷金属2。然后除去线7的剩余部分,仅留下键合焊盘6上的熔敷金属2。因此,本实施例的熔敷金属2为标准的线键合,没有任何伸出的线。
图4示出了备选实施例中的半导体器件100的处理。使用分配器21将导电环氧或其它导电材料分配到键合焊盘6上形成熔敷金属2。在键合焊盘6上形成熔敷金属2以提供到外部电路的电连接的低成本措施。
应该注意半导体器件100使用没有键合线和相关连弯曲部分的封装101。由此,半导体器件100提供了薄外形,同时使用了标准的处理设备并避免了需要复杂的处理步骤。熔敷金属2的电流运载截面面积大于形成熔敷金属2使用的键合线7的面积。较大的熔敷金属2的截面面积为半导体器件提供了较低的电阻,因此增加了电流运载能力。此外,较大的截面面积提高了导热性和来自半导体管芯1的热传递。
图5示出了另一备选实施例中的半导体器件100的剖面图。形成密封体3以露出标记8和引线框的管芯焊接标记24。通过露出管芯焊接标记24和8,由半导体管芯1产生的热能更有效地散发,提供了半导体封装101的热传递和功率耗散能力。
图6示出了使用激光器13的选定处理步骤期间半导体器件100的另一备选实施例的剖面图。在本实施例中,形成密封体3使熔敷金属2和镀层10从表面14凹入,因此图中未示出。
如前所述,位置23与熔敷金属2有关并预先记录和存储。对激光器13进行编程以使用基准5作为参考从而引导激光束22指向位置23以从密封体除去材料以在表面14上形成开口17。由于开口17覆盖熔敷金属2,因此束22提供的能量消融了一部分密封体3露出熔敷金属2和标记8。此外,由于载体和管芯之间的突点未对准造成DCA器件的缺陷。熔敷金属2的放置和露出具有记录和储存位置23防止了任何未对准。
在形成引出端26-28的备选方法中,通过将大的焊料球、铜球或其它导电材料放置在顶面11上需要的位置形成熔敷金属2,同时半导体管芯仍然为晶片形式。考虑到管芯1和引线框4之间未对准的最坏情况,焊料球制得大于位置23的尺寸。密封半导体器件之后,借助储存的位置23露出密封体3下面的部分熔敷金属2。由此,当使用激光或类似的设备消融位置23时,熔敷金属2的露出部分作为引出端26-28。因此,采用本方法,形成引出端26-28的最终步骤是参考基准5的位置处,即参考引线框4上的一点处将位置23开口。
熔敷金属2通常用焊料球(未示出)覆盖但仍然凹陷在开口17内。凹陷有利于将焊料球对准安装到电路板。
图7示出了喷水口15从密封体3除去材料的半导体器件100的剖面图。喷水口15将水流30喷洒在密封体3上以从表面14上均匀地除去材料到露出熔敷金属2的虚线32表示的高度。此外,使用摩擦或研磨从表面14除去材料露出熔敷金属2。
图8示出了从密封体3均匀地除去材料以便熔敷金属2和标记8伸出表面14之后半导体器件100的剖面图。除去了部分熔敷金属2和标记8下面的密封体之后,便于DCA安装到***电路板。
总之,本发明提供了一种使用标准的设备实现低制造成本同时提供了低封装高度的半导体器件100。半导体器件具有安装在引线框上的半导体管芯,由线键合球形成的熔敷金属焊接到管芯的键合焊盘形成引出端。参考引线框上的一个点例如基准熔敷金属形成在管芯上。该方法将熔敷金属对准在管芯上,即使由于制造变化性造成管芯稍微旋转仍能保持固定的引出端图形。
Claims (10)
1.一种半导体器件的制造方法,包括以下步骤:
将半导体管芯连接到引线框;以及
参考引线框上的一点的位置处将线键合球形成在半导体管芯上以制成半导体器件的一个引出端。
2.根据权利要求1的方法,其中形成步骤还包括以下步骤:
将线键合到半导体器件上的键合焊盘;以及
除去线以形成线键合球。
3.根据权利要求1的方法,还包括以下步骤:
用密封体包围半导体管芯和引线框;以及
从密封体除去材料以露出线键合球。
4.根据权利要求3的方法,其中除去步骤包括在所述位置选择性消融材料的步骤。
5.根据权利要求1的方法,还包括用焊料或镍覆盖线键合球的步骤。
6.一种半导体器件的制造方法,包括在引线框上一点确定的位置处从半导体器件密封体上选择性除去材料的步骤,以露出半导体管芯表面上的半导体器件的引出端。
7.根据权利要求6的方法,其中选择性除去步骤包括露出熔敷金属形成引出端的步骤,还包括以下步骤:
在半导体管芯上形成熔敷金属;以及
形成熔敷金属之后将半导体管芯焊接到引线框。
8.一种半导体器件的制造方法,包括以下步骤:
在与引线框对准的位置处在半导体管芯的表面上形成第一熔敷金属以制备半导体器件的第一引出端。
9.根据权利要求8的方法,还包括在引线框的标记上形成第二熔敷金属以制备半导体器件的第二引出端的步骤。
10.根据权利要求8的方法,其中形成步骤包括在所述位置处形成线键合球的步骤。
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Country Status (4)
Country | Link |
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US (2) | US6787392B2 (zh) |
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MY (1) | MY126696A (zh) |
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