CN1423450A - Digital frequency regulating method capable of anti-creep clock low-frequency - Google Patents
Digital frequency regulating method capable of anti-creep clock low-frequency Download PDFInfo
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- CN1423450A CN1423450A CN 01139058 CN01139058A CN1423450A CN 1423450 A CN1423450 A CN 1423450A CN 01139058 CN01139058 CN 01139058 CN 01139058 A CN01139058 A CN 01139058A CN 1423450 A CN1423450 A CN 1423450A
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Abstract
This invention relates to a method for digit frequency adjustment capable of suppressing clock low frequency shift field spots combining segment average and sliding average to process input and output clock frequency difference value and compute the control value of each time scale voltage-controlled oscillator having four kinds working ways of arrest, trace, loosing all input signals, providing a high stable circuit clock.
Description
Technical field
The present invention relates to the communication transmission technology, particularly a kind of digital frequency regulating method that needs the anti-creep clock low-frequency occasion that is applied in.
Background technology
The conventional method that suppresses clock drift is to adopt digital phase-locked loop.Digital phase-locked loop is based on the synchronization principles of phase-locked loop, adopt digital form, follow the tracks of an input reference clock source, after output clock and input clock compare through phase place (frequency), draw one and differ (difference on the frequency) value, pass through the low-pass filtering method again, remove to control voltage controlled oscillator (VCXO), final feasible output clock and the strict maintenance of input clock are with frequency.
General digital phase-locked loop all comprises digital phase discriminator, low pass filter and voltage controlled oscillator three parts.Digital phase discriminator detects the phase difference of input clock source and output clock, and low pass filter draws a controlling value according to the testing result of digital phase discriminator through the low-pass filtering method, exports clock behind the control voltage controlled oscillator.The low-pass filtering method, promptly phase-locked loop method generally all adopts several groups of parameters, comprise and catch parameter and tracking parameter, the scope of wherein catching the parameter capture clock is bigger, is reflected in that promptly to approach step-length on the method bigger, the proportionality coefficient that is adopted is bigger, and the corresponding clock shake is also bigger certainly; And the tracking parameter catching range is less, is reflected in that promptly to approach step-length on the method less, and the proportionality coefficient that is adopted is also less, and integral coefficient is bigger, and the corresponding clock shake is less, and (detailed content can be with reference to patent applied for, and number of patent application is: 99117206.X).
Traditional digital phase-locked loop is generally more intense to the inhibition ability of clock high dither, and relatively poor to the low frequency wonder inhibition ability of clock comparatively speaking.At common transmission field, as described in patent 99117206.X, this phase-locked loop can be competent at.But in some practical application, high as the frequency stability of clock is required, and the input clock source be can not guarantee stability because line clock is very poor the time, traditional phase-locked loop is promptly not competent.As the 2M data by after the SDH transmission, will introduce shake and drift, the occasion that amplitude is big has frequency and reaches the drift of 6～7ppm in 0.01HZ, amplitude, and line clock drifts about on so low frequency, is difficult to allow output frequency be stabilized within the native 1ppm with traditional tightly coupled phase-locked loop.
Improvement such as self adaptation modification by contrast phase frequency and the related parameter of digital phase-locked loop, (detailed content can be with reference to patent applied for, and number of patent application is: 00119876.9) to the inhibition ability of low-frequency clock drift thereby the clock phase-locked loop that can realize loose coupling can improve phase-locked loop.But follow-on digital phase-locked loop is suppressing aspect the low-frequency clock drift or inconvenient, is embodied at different application scenarios and selects on suitable this problem of method parameter.
Because clock drift can go to understand and analyze from the angle of frequency, can use digital frequency regulating method to suppress clock drift.This method mainly adopts pulse counter, digital frequency regulating method and voltage controlled oscillator.Pulse counter is regularly measured the frequency of input, output clock, calculates the difference of two frequencies then, and digital frequency regulating method is handled and controlled value frequency-splitting, and the output of control voltage controlled oscillator produces the output clock that meets the demands.
Summary of the invention
Purpose of the present invention just is to provide a kind of new digital frequency regulating method, is used for suppressing the extremely abominable low frequency wonder of clock specially, and the line clock of a high stability can be provided for transmission system.This method is simple and reliable, and the selection of related parameter is also convenient directly perceived, can overcome the difficulty of digital phase-locked loop difficult parameters to select.
Digital frequency regulating method of the present invention combines segmental averaging and the moving average method is handled the frequency-splitting of input, output clock, calculates each controlling value of voltage controlled oscillator constantly.Defined four kinds of working methods in method, be respectively: seizure, tracking, input signal are all lost with input signal and are switched.
The step that method realizes is as follows:
1) situation of judgement input clock.If all lose in used input clock source, change step 5; If the input clock source switches, change step 6;
The frequency-splitting of 2) measurement input, output clock also judges whether to catch success, if step 4 is then changeed in success, otherwise changes step 3;
3) catch processing, catch and successfully then establish corresponding sign, change step 7;
4) follow the tracks of processing, change step 7;
5) input signal is all lost processing, keeps the voltage controlled oscillator controlling value of last time, changes step 7;
6) input signal switches, and switching clock source changes step 7;
7) return.
Four kinds of working methods mentioning in the method are described below.
One, catches
Utilize the method for segmental averaging and moving average that the frequency-splitting (deltf) of input, output clock is handled, the average frequency of output clock and input clock is equated.The step of catching is as follows:
1) establishing seizure segmental averaging time span is L
CAIn the segmental averaging time span, measure the difference (deltf) of input, output clock frequency, calculate their mean value, so just can calculate a controlling value that can make input in this section time span, export the equal voltage controlled oscillator of clock average frequency.
2) in next segmental averaging time span, the sliding average of the voltage controlled oscillator controlling value that the controlling value of the voltage controlled oscillator of actual output calculates in the segmental averaging time period before being.If establishing and catching the moving average length of window is L
CM, so, the controlling value of voltage controlled oscillator is preceding L in the next segmental averaging time span
CMThe mean value of the voltage controlled oscillator controlling value that calculates in the segmental averaging time span.
3) if less than the value of a setting time, show seizure success to the mean value of current input, output clock frequency difference from catching the zero hour.
Two, follow the tracks of
At tracking phase, the average frequency that still needs to keep importing, export clock equates.Moreover, because what this method was handled is the line clock of communication transmission system, in order to avoid circuit to produce slip as far as possible, in following the tracks of processing procedure, also will make the frequency of output clock is the center with input clock frequency mean value, changes adaptively to alleviate the pressure of bit stream data first-in first-out buffer according to predefined Changing Pattern in allowed limits.In order to continue to keep output clock mean value, set the controlling value D of a voltage controlled oscillator
KWrite down the most believable controlling value that keeps output, input clock average frequency to equate.The step of following the tracks of is as follows:
1) establishing tracking segmental averaging time span is L
LA, at L
LAMeasure input, output clock frequency difference in long, refresh the aggregate-value (sum_deltf) of input, output clock frequency difference.Utilize sum_deltf to calculate the average adjustment amount (AD_DA) of the voltage controlled oscillator controlling value in next segmental averaging time.
2) for the variation that guarantees frequency in the next segmental averaging time meets the demands, according to the frequency range (V of average adjustment amount that calculates and requirement
f) calculate the controlling value of each moment voltage controlled oscillator in the next segmental averaging time span and the mean value (AV_DA) of these controlling values with predefined rule.
3) AV_DA that calculates in each segmental averaging time span is got moving average, refresh D with the sliding average that calculates
KIf establishing and following the tracks of the moving average length of window is L
LM, so, the most credible controlling value D of voltage controlled oscillator in the next segmental averaging time span
KBe preceding L
LMThe mean value of each AV_DA that calculates in the individual segmental averaging time span.
4) after tracking time reaches the length of setting, recomputate segmental averaging length of window and the moving average length of window that adapts to the current demand signal clock low frequency wonder cycle most according to the historical record of actual motion, thereby improve the effect of frequency adjustment.
Three, input signal is all lost
When the situation that input signal all loses occurring, use the most credible controlling value D of current voltage controlled oscillator
KThe output of control voltage controlled oscillator produces a fixing frequency, and signalization is caught and successfully is masked as non-ly simultaneously, guarantees directly to enter into when signal reappears the signal capture state.
Four, input signal switches
This method can be handled multiple signals inputs, loses when current demand signal occurring, and during the situation that other several signals also have, reselects wherein one road signal, and signalization is caught and successfully is masked as non-ly simultaneously, guarantees that next step directly enters into the signal capture state.
The present invention will be further described below in conjunction with accompanying drawing and specific embodiment.
Fig. 1 is a digital frequency regulating method hardware schematic diagram;
Fig. 2 is the main flow chart of digital frequency regulating method;
Fig. 3 is that digital frequency regulating method is caught flow chart;
Fig. 4 is digital frequency regulating method trace flow figure;
Fig. 5 is the schematic diagram of digital frequency regulating method specific implementation;
Fig. 6 is the example that the frequency drift of input clock signal changes;
Fig. 7 is that the frequency drift of using the clock signal after this method is handled signal shown in Figure 6 changes.
Accompanying drawing 1 has provided the The hardware design functional block diagram of example.Among the figure, two pulse counters are counted the purpose that realizes frequency measurement to the input and output clock respectively.The frequency values of input and output clock is regularly read in by CPU, can calculate the frequency-splitting of two clocks.The method flow that this difference enters this method just can calculate desired controlling value, the output of control voltage controlled oscillator.
Accompanying drawing 2 is main flow charts of digital frequency regulating method.
Accompanying drawing 3 and accompanying drawing 4 are respectively the flow charts that digital frequency regulating method is caught and followed the tracks of.
Practical methods model such as accompanying drawing 5.
L wherein
CABe to catch segmental averaging time span, L
CMBe to catch the moving average time span;
L
LABe to follow the tracks of segmental averaging time span, L
LMBe to follow the tracks of the moving average time span; V
fThe frequency range that allows when being tracking.
At different application scenarios, according to the deterioration degree of clock low frequency wonder, promptly the roughly situation in the cycle of low frequency wonder can be selected suitable value to each parameter easily.In order to resist the low frequency wonder of clock, use segmental averaging that input clock frequency is handled, consider the frequency characteristic of voltage controlled oscillator, the segmental averaging time span can not obtain oversize, so add a processing of the segmental averaging value being got moving average to strengthen the inhibit feature to the low-frequency clock drift.Such as, the opposing cycle reaches 30 minutes low-frequency clock drift, and can select the segmental averaging time span is 60 seconds, and the moving average time span is 1800 seconds a parameter.
In the application scenario of a reality, the line clock in input clock source is after SDH worsens, and performance is poor, and as shown in Figure 6, among the figure, transverse axis is the time, and unit is second; The longitudinal axis is a frequency variation, and unit is ppm.The concrete index that accompanying drawing 6 medium frequencys change is: input clock frequency drift excursion is ± 3.060903ppm.And system requirements wants the output frequency range of drift should be less than ± 1ppm.
When method is implemented, at first get L
CA=60; L
CM=30; V
f=± 1ppm catches processing to input signal, about 600 seconds, catches the merit of just accomplishing, the frequency drift excursion of output clock is controlled at ± 0.116868ppm within, can satisfy the requirement of system.
After catching successfully, just enter into tracing process.Get L
LA=60; L
LM=30, continue input clock is handled, the frequency drift excursion of output clock still is controlled at ± 0.116868ppm within.Follow the tracks of after 30 minutes when following the tracks of, the historical data of input signal is analyzed, find that input signal has some cycles, as calculated, the cycle is 300 seconds, so adjust L
LA=60; L
LM=10, continue input signal is followed the tracks of processing, the frequency drift excursion of output clock still is being controlled in the ensuing time ± 0.116868ppm within.
Enter and follow the tracks of to handle that output signal frequency changes as shown in Figure 7 after 24 hours.
Claims (6)
1. the digital frequency regulating method of an energy anti-creep clock low-frequency occasion comprises segmental averaging and moving average method, it is characterized in that, the frequency-splitting of input, output clock is handled, and calculates each controlling value of voltage controlled oscillator constantly; And have that seizure, tracking, input signal are all lost and input signal switches four kinds of working methods.
2. according to the digital frequency regulating method of the described energy of claim 1 anti-creep clock low-frequency occasion, it is characterized in that the step that this method realizes is as follows:
1) situation of judgement input clock.If all lose in used input clock source, change step 5; If the input clock source switches, change step 6;
The frequency-splitting of 2) measurement input, output clock also judges whether to catch success, if step 4 is then changeed in success, otherwise changes step 3;
3) catch processing, catch and successfully then establish corresponding sign, change step 7;
4) follow the tracks of processing, change step 7;
5) input signal is all lost processing, keeps the voltage controlled oscillator controlling value of last time, changes step 7;
6) input signal switches, and switching clock source changes step 7;
7) return.
According to claim 1 described can anti-creep clock low-frequency the digital frequency regulating method of occasion, it is characterized in that, the working method of catching is to utilize the method for segmental averaging and moving average that the frequency-splitting (deltf) of input, output clock is handled, make the average frequency of output clock and input clock equate that the step of seizure is as follows:
1) establishing seizure segmental averaging time span is L
C4In the segmental averaging time span, measure the difference (deltf) of input, output clock frequency, calculate their mean value, so just can calculate a controlling value that can make input in this section time span, export the equal voltage controlled oscillator of clock average frequency
2) in next segmental averaging time span, the sliding average of the voltage controlled oscillator controlling value that the controlling value of the voltage controlled oscillator of actual output calculates in the segmental averaging time period before being, to catch the moving average length of window be L if establish
CM, so, the controlling value of voltage controlled oscillator is preceding L in the next segmental averaging time span
CMThe mean value of the voltage controlled oscillator controlling value that calculates in the individual segmental averaging time span,
3) if less than the value of a setting time, show seizure success to the mean value of current input, output clock frequency difference from catching the zero hour.
4. according to the digital frequency regulating method of the described energy of claim 1 anti-creep clock low-frequency occasion, it is characterized in that the working method of tracking is for continuing to keep output clock mean value, the controlling value D of a voltage controlled oscillator of setting
KWrite down the most believable controlling value that keeps output, input clock average frequency to equate, the step of tracking is as follows:
1) establishing tracking segmental averaging time span is L
LA, at L
LAMeasure input, output clock frequency difference in the duration, refresh the aggregate-value (sum_deltf) of input, output clock frequency difference.Utilize sum_deltf to calculate the average adjustment amount (AD_DA) of the voltage controlled oscillator controlling value in next segmental averaging time,
2) according to the average adjustment amount that calculates and the frequency range (V of requirement
f) calculate the controlling value of each moment voltage controlled oscillator in the next segmental averaging time span and the mean value (AV_DA) of these controlling values with predefined rule,
3) AV_DA that calculates in each segmental averaging time span is got moving average, refresh D with the sliding average that calculates
KIf establishing and following the tracks of the moving average length of window is L
LM, so, the most credible controlling value D of voltage controlled oscillator in the next segmental averaging time span
KBe preceding L
LMThe mean value of each AV_DA that calculates in the individual segmental averaging time span.
4) after tracking time reaches the length of setting, recomputate segmental averaging length of window and the moving average length of window that adapts to the current demand signal clock low frequency wonder cycle most according to the historical record of actual motion.
According to claim 1 described can anti-creep clock low-frequency the digital frequency regulating method of occasion, it is characterized in that, input signal is all lost working method for when the situation that input signal all loses occurring, use the output of the most credible controlling value control voltage controlled oscillator of current voltage controlled oscillator to produce a fixing frequency, simultaneously signalization is caught and successfully is masked as non-ly, guarantees directly to enter into when signal reappears the signal capture state.
According to claim 1 described can anti-creep clock low-frequency the digital frequency regulating method of occasion, it is characterized in that, input signal switch operating mode is for losing when current demand signal occurring, and during the situation that other several signals also have, reselect wherein one road signal, simultaneously signalization is caught and successfully is masked as non-ly, guarantees that next step directly enters into the signal capture state.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01139058 CN1423450A (en) | 2001-12-03 | 2001-12-03 | Digital frequency regulating method capable of anti-creep clock low-frequency |
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| CN 01139058 CN1423450A (en) | 2001-12-03 | 2001-12-03 | Digital frequency regulating method capable of anti-creep clock low-frequency |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281062A (en) * | 2010-06-12 | 2011-12-14 | 大唐移动通信设备有限公司 | Method and equipment for outputting clock signals |
| CN102959861A (en) * | 2010-06-28 | 2013-03-06 | 松下电器产业株式会社 | Reference frequency generating circuit, semiconductor integrated circuit and electronic apparatus |
| CN104485925A (en) * | 2014-12-10 | 2015-04-01 | 中国电子科技集团公司第二十研究所 | Method for generating random filling pulses of TACAN (Tactical Air Navigation System) beacons |
-
2001
- 2001-12-03 CN CN 01139058 patent/CN1423450A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281062A (en) * | 2010-06-12 | 2011-12-14 | 大唐移动通信设备有限公司 | Method and equipment for outputting clock signals |
| CN102281062B (en) * | 2010-06-12 | 2014-03-12 | 大唐移动通信设备有限公司 | Method and equipment for outputting clock signals |
| CN102959861A (en) * | 2010-06-28 | 2013-03-06 | 松下电器产业株式会社 | Reference frequency generating circuit, semiconductor integrated circuit and electronic apparatus |
| CN104485925A (en) * | 2014-12-10 | 2015-04-01 | 中国电子科技集团公司第二十研究所 | Method for generating random filling pulses of TACAN (Tactical Air Navigation System) beacons |
| CN104485925B (en) * | 2014-12-10 | 2017-03-29 | 中国电子科技集团公司第二十研究所 | The random filler pulse production method of tacan beacon |
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