CN1249924C - Shake-removing circuit based on digital lock phase loop - Google Patents

Abstract

The present invention discloses a flutter removing circuit based on a digital phase locked loop (100), which comprises FIFO and a digital phase locked loop (100), wherein the digital phase locked loop (100) comprises a 32 frequency doubling circuit, an input clock edge detection circuit (202), a phase detector (200), an upward counter, a downward counter, an adding pulse circuit, a subtracting pulse circuit, a two dividing circuit, a sixteen dividing circuit (201) and an output clock edge detection circuit (203). The 32 frequency doubling of an external input low-frequency system clock is carried out by the 32 frequency doubling circuit, and the external input low-frequency system clock is used as a reference clock. The input of the input clock edge detection circuit (202) is a writing clock signal, the output of the input clock edge detection circuit (202) is a signal after the writing clock phase detection, the input of the output clock edge detection circuit (203) is a reading clock signal, the output of the output clock edge detection circuit is a signal after the reading clock phase detection, the input of the phase detector (200) is edge detection signals of a reading clock and a writing clock, and the output of the phase detector (200) is an advance lag admission signal. The present invention has the advantages of flutter removing realization, good low-frequency flutter removing effect, high stability of a corresponding simulation method, good locking property and tracking property, high circuit reliability and convenient integration.

Description

De-twitter circuit based on digital phase-locked loop

Technical field

The present invention relates to the border E1 branch road of SDH transmission network and how on the E1 branch road, remove and reduce low-frequency jitter that the SDH side brings and the circuit of drift, particularly related to the de-twitter circuit in the E1 line interface chip that a kind of modulus mixes.

Background technology

Low-frequency jitter of bringing owing to the pointer adjustment in the SDH transmission network and drift have become the obstacle of SDH transmission network and other transmission networks realization intercommunications.For using SDH system and PDH system simultaneously, adopt de-twitter circuit can solve shake and the drift that brings by the pointer adjustment at the border of SDH system E1 tributary interface place.Go to tremble the technical literature introduction of aspect according to the present relevant E1 circuit in SDH aspect, mainly be mixed into the master with modulus, such as, the patent No. is 4941156 United States Patent (USP), exercise question is: linear Jitter Attenuation device (Linear jitterattenuator).This de-twitter circuit is made up of push-up storage (FIFO memory) and phase-locked loop, and its phase-locked loop has partly adopted analog phase-locked look, the implementation structure more complicated; Though high frequency characteristics is good, effect is bad under low frequency, and the removal effect of drifting about for long-term shake is not so good as digital phase-locked loop.Analog phase-locked look stability and antijamming capability are also poor in addition.

Summary of the invention

The technical problem to be solved in the present invention is in order to overcome not easy of integration and low frequency characteristic of analog phase-locked look in the de-twitter circuit of the prior art and the tracking lock performance shortcoming not as digital phase-locked loop, a kind of de-twitter circuit based on digital phase-locked loop of specialized designs goes to tremble the relatively poor relatively problem of characteristic to solve the low frequency that exists in the prior art.

Technical scheme of the present invention is achieved in that

A kind of de-twitter circuit based on digital phase-locked loop comprises, the FIFO memory: its input signal is the clock of writing of outside input, the data of outside input and phase-locked loop output read clock, from the FIFO memory, export after removing the signal of shake; The FIFO memory is also exported two control signals and is reported its store status promptly fast full and fast dummy status to digital phase-locked loop; It is characterized in that also comprise digital phase-locked loop, described digital phase-locked loop comprises 32 frequency multiplier circuits, input clock is along testing circuit, phase discriminator, and the up/down register adds/the subtract pulse circuit, removes 2 circuit, removes 16 circuit and output clock along testing circuit;

Described 32 frequency multiplier circuits carry out 32 frequencys multiplication with the low frequency system clock of outside input, and with the high-frequency clock that the obtains reference clock as digital phase-locked loop inside;

Described input clock is output as the signal of writing after clock phase detects along the write clock signal that is input as of testing circuit;

Described output clock is output as the signal of reading after clock phase detects along the read clock signal that is input as of testing circuit;

Described phase discriminator be input as the reading and writing clock along detection signal, be output as lead-lag and allow signal, write clock with sign and be ahead of and read clock or lag behind to read clock;

The lead-lag that is input as of described up/down counter allows signal, reads clock and reference clock, is output as the plus-minus pulse control signal;

Output adds pulse signal and subtract pulse signal to described adding/subtract pulse circuit according to the add-subtract control signal, and is input to the output of regulating frequency-halving circuit in the frequency-halving circuit;

Described frequency-halving circuit be input as reference clock, add pulse and subtract pulse signal, be output as controlled two divided-frequency clock; Described two divided-frequency clock is input to and carries out frequency division in 16 frequency dividing circuits to obtain the needed clock of writing;

Above-mentioned digital phase-locked loop is used to provide narrow-band filtering, and is cleaner to obtain one, shakes very little clock; Described digital phase-locked loop be input as the external write clock, be output as and read clock; Described digital phase-locked loop is by reading the phase place that clock and the bit comparison adjustment mutually of writing clock are read clock, make it and write clock synchronization, like this through phase-locked loop output read clock again with the taking-up from the FIFO memory of the data of input the time, will obtain the signal that the shake of clock and data all reduces greatly.

The present invention proposes to adopt digital methods to realize the removal of shaking, except that the FIFO memory adopts digital method, phase-locked loop also adopts digital phase-lock mode, the de-twitter circuit that obtains like this, though that high frequency goes to tremble effect is poorer slightly than analogy method, it is very good that low frequency goes to tremble effect, and relative analogy method good stability, locking and tracking characteristics are good, and the circuit reliability height is convenient to integrated.

Description of drawings

Further specify the present invention below in conjunction with accompanying drawing.

Fig. 1 is a de-twitter circuit structured flowchart of the present invention.

Fig. 2 is the structured flowchart of digital phase-locked loop.

Fig. 3 reads and writes the structured flowchart of clock along testing circuit and phase discriminator in the digital phase-locked loop.

Fig. 4 is the input and output waveform schematic diagram of Fig. 3 circuit.

Fig. 5 is the waveform schematic diagram of plus-minus circuit output.

Embodiment

Because on the SDH transmission network, low-frequency jitter and filtering drift are very important problems, must conscientiously solve.

Shown in Figure 1 is the structured flowchart of the present invention's numeral de-twitter circuit, the present invention adopts push-up storage FIFO memory and digital phase-locked loop to finish the removal of shake, the signal that is input in the FIFO memory is the clock of writing of outside input, the data of outside input and phase-locked loop output read clock, remove the signal of shake and from the FIFO memory, export.The FIFO memory is also exported the promptly fast full and fast spacing wave of two control signals in digital phase-locked loop, and this situation usually occurs in input signal and clock jitter very large the time.Digital phase-locked loop be input as the external write clock, be output as and read clock, phase-locked loop the effect here is by reading the phase place that clock and the bit comparison adjustment mutually of writing clock are read clock, make it and write clock synchronization, like this through phase-locked loop output read clock again with the taking-up from the FIFO memory of the data of input the time, will obtain the signal that the shake of clock and data reduces greatly.

De-twitter circuit of the present invention can be regarded the phase-locked loop of a band buffer as.The clock that has shake is as writing clock, this clock writes input signal in the FIFO memory, digital phase-locked loop should be exported a comparison is clean, shake is the very little clock clock of reading as the FIFO memory, reads and obtains the signal that jittering component significantly reduces thereby this clock will deposit the signal of FIFO memory in.In order to guarantee the synchronous of input/output signal and to prevent dropout, reading clock will follow the tracks of with phase-locked the phase place of writing clock within the specific limits by phase-locked loop, the phase place of the output clock by the narrow-band digital phase-locked loop and the phase place of writing clock and the frequency that frequency is locked in input all the time like this, here the effect of FIFO memory is an elastic store, can absorb shake to greatest extent by the FIFO memory, it is relevant with the degree of depth of FIFO memory that the FIFO memory absorbs the ability of shaking.

FIFO memory in the de-twitter circuit of the present invention is that a degree of depth is 64, width is 2 dual port RAM, during initialization, write pointer refers in the centre of FIFO memory (100000), read pointer refers in the bottom of FIFO memory (000000), clock with shake is as writing clock, read clock through the clock conduct that phase-locked loop is level and smooth, when writing the clock arrival data are write the position of FIFO memory write pointer indication at every turn, write pointer adds one simultaneously, read equally from corresponding read pointer data to be read when clock arrives, read pointer adds one simultaneously.If read clock fully and write clock synchronization, then phase-locked loop does not need to do any adjustment, and the state of FIFO memory still remains on half-full state.If write clock and to read clock asynchronous, then read clock and adjust the phase place of output and the variation that frequency is followed the tracks of input clock by phase-locked loop.In the FIFO memory, thereby the difference that has a counter to write down write pointer and read pointer is specially measured the size of shake, under the little situation of input clock shake, because the effect of phase-locked loop, thereby the FIFO memory can not take place because of writing phenomenon full or that get the sky obliterated data, the value of this counter can remain near 32, but when input clock is shaken under the very large situation, will cause overflowing or reading sky of FIFO memory, at this moment we establish two states by this counter, promptly fast state and the fast dummy status of expiring, when counter records when writing clock and clock correction is 5 when reading, for reading dummy status soon, when counter records clock correction when writing clock and read is 58, for writing full state soon, the output clock frequency of these two State Control phase-locked loops, when fast dummy status took place the FIFO memory, phase-locked loop made the clock of output slow down, become 16.5 frequency divisions by 16 frequency divisions, disappear up to fast dummy status.Otherwise when the output of FIFO memory was expired state soon, the output clock of phase-locked loop was accelerated, and becomes 15.5 frequency divisions by 16 frequency divisions, up to expiring the state disappearance soon.When fast full and fast dummy status occurring, the corresponding adjustment of the phase place of read pointer 0.3UI.

When fast full and fast dummy status took place, shake was not by filtering and reduce, but data can be held, thereby can not cause the generation of system's error code.

Digital phase-locked loop in the de-twitter circuit of the present invention can be followed the tracks of the variation of writing clock phase well, obtains and write clock basic synchronization and the very little output clock of shake.

Further specify the structure and the principle of digital phase-locked loop in conjunction with Fig. 2, as shown in Figure 2, this phase-locked loop belongs in advance-the retarded type digital phase-locked loop, whole phase-locked loop circuit is by 32 frequency multiplier circuits, and input clock is along testing circuit 202, phase discriminator 200, the up/down counter, add/the subtract pulse circuit, remove 2 circuit, remove 16 circuit 201 and output clock along testing circuit 203 compositions.32 frequency multiplier circuits are 2.048M low frequency system clock 32 frequencys multiplication of outside input, and with the high-frequency clock that the obtains reference clock as digital phase-locked loop inside.The frequency of this reference clock is 65.536M.Input clock is along the write clock signal that is input as of testing circuit 202, be output as the signal of writing after clock phase detects, the output clock is along the read clock signal that is input as of testing circuit 203, be output as the signal of reading after clock phase detects, phase discriminator 200 be input as the read-write clock along detection signal, be output as lead-lag and allow signal, write clock with sign and be ahead of and read clock or lag behind to read clock.The lead-lag that is input as of up/down counter allows signal, reads clock and reference clock, is output as the plus-minus pulse control signal.Add/output adds pulse signal and subtract pulse signal to the subtract pulse circuit according to the add-subtract control signal, and be input to the output of regulating frequency-halving circuit in the frequency-halving circuit.Frequency-halving circuit be input as reference clock, add pulse and subtract pulse signal, be output as controlled two divided-frequency clock.This two divided-frequency clock be input to carry out in 16 frequency dividing circuits frequency division with obtain required for the present invention want write clock.

The operation principle of digital phase-locked loop 100 is: 32 frequency multiplier circuits with 2.048M low frequency system clock 32 frequencys multiplication of outside input, obtain the reference clock of the high-frequency clock of 65.536MHz as digital phase-locked loop inside earlier.Because the frequency of the reference clock of outside input equals the frequency of input signal, so this frequency need be carried out 32 frequencys multiplication to produce the reference clock of high-frequency clock as digital phase-locked loop, the frequency of output clock is when lock-out state like this, be 32 frequency divisions of this reference clock, when asynchronous, select for use the reason of 32 frequency multiplier circuits to be at input clock and output clock: thus the output clock by digital phase-locked loop constantly adjust phase place and frequency keep with input clock synchronously.The each step-length of adjusting of output clock is relevant with the clock cycle, so the clock frequency that digital phase-locked loop adopts is high more.The bandwidth of the digital phase-locked loop that obtains is wide more, and it is high more to adjust precision, and the shake of output clock is also more little.And that very important index of de-twitter circuit is the shake of requirement output clock and signal is very little.Here adopt 32 frequency multiplier circuits can satisfy the requirement of system fully to the de-twitter circuit output jitter.In addition, the reason of selecting 32 frequency multiplier circuits for use also because: if adopt the low circuit of Clock Multiplier Factor, then be difficult to obtain more satisfactory lockout feature, and the shake of output clock and signal is still bigger.Why do not have to adopt the circuit of higher Clock Multiplier Factor,, follow the tracks of relative long shortcoming but brought, and the frequency multiplier circuit cost of employing higher frequency is also than higher with locking time though be because the meeting of the output jitter characteristic of digital phase-locked loop is better.So the reference clock that the present invention adopts 32 frequency multiplier circuits to be used as digital phase-locked loop is suitable consideration.

Input clock detects the phase place of writing clock along testing circuit 202, the output clock detects the phase place of write-read clock along testing circuit 203, input clock is reference frequency 65.536MHz along the sample frequency of testing circuit 202, output write clock along detection signal for synchronous pulse duration is the narrow pulse signal of 15ns with writing rising edge clock, read clock along the result who detects for being that the window signal width at center is the narrow pulse signal of 60ns to read rising edge clock.Phase discriminator 200 is relatively read the phase place that clock and local reference clock are write clock one by one periodically, correspondingly exports a lead and lag pulse according to the lead and lag of read-write clock phase, reads the phase place of clock with adjusting.Add/subtract circuit the signal bell output sequence is implemented to add subtract pulse.Accurately synchronous as if reading clock and writing clock, then need not to add subtract pulse output, the phase place that adds to the bit synchronization signal of phase discriminator 200 remains unchanged.If the writing clock and lag behind of input with respect to reading clock, then the up/down counter is exported the subtract pulse control signal, add/subtract circuit and in reference clock XCLK two divided-frequency clock sequence, subtract a high-speed pulse, again after removing 16 circuit 201, then read the clock phase 15ns that will lag behind, if input to write clock leading with respect to reading clock, then one of up/down counter output adds pulse control signal, add/the subtract pulse circuit adds a high-speed pulse in reference clock XCLK two divided-frequency clock sequence, read clock reach 7.5ns, write the variation of clock with tracking, the process of phase bit comparison and adjustment is ongoing, in the phase place of writing clock, phase-locked loop just enters stable state up to the phase locking of reading clock.Here the system clock that is adopted is 65.536MHZ, is 32 times of frequency input signal.Then the step-length of each maximal regulated is 1/65.536=15ns.

The inner concrete module operation principle of the circuit of digital phase-locked loop 100 is as follows, introduces respectively below.

As shown in Figure 3, phase detector circuit adopts the phase bit comparison in the digital phase-locked loop 100, reach the purpose of phase demodulation by the rising edge clock phase place of relatively writing clock and read clock, under the normal condition, read clock and be the signal that system clock obtains after through 32 frequency divisions, when reading clock and writing clock synchronization, do not need to carry out any adjustment.Input is write clock and is made up of shift register and AND circuit along testing circuit 202, write clock obtain through displacement and oppositely one with write clock oppositely and delay time and be the signal of 15ns, this signal with write clock with the result obtain one with write clock synchronization and pulse duration be 15ns write clock along detection signal WR_TRAS.That reads clock produces a detection window by one except that 16 circuit along testing circuit, and the pulse duration of this detection window is 60ns.If writing the edge of clock drops in this detection window, show that then output clock and input clock are synchronous, it is 0 that the output lead-lag of phase discriminator 200 allows signal, the output clock does not need to carry out the phase place adjustment, if the edge of input clock is dropped on outside this window, show that then the output clock is asynchronous with the input clock phase place, the lead-lag of the output of phase discriminator 200 allows signal to compare and judge that reading clock is ahead of and writes clock or lag behind write clock signal with reading clock, thereby controls the state of up/down counter.

Fig. 4 is the schematic diagram of Fig. 3 circuit input and output waveform, write clock along detection signal WR_TRAS with read clock be lead-lag permission signal EN_CONNTER along coefficient result, allow signal EN_CONNTER to be ahead of the phase place of reading clock as lead-lag, show that then to write clock leading; Otherwise, write clock and lag behind.The up/down counter can add reducing accordingly according to lead and lag information.

The up/down counter by three upwards counter and three downward counters constituted, counting clock is a system clock, the output of up/down counter adds pulse control signal and subtract pulse control signal to being added/the subtract pulse control circuit.The up/down counter detects the state of phase discriminator, when the output lead-lag of phase discriminator allows signal to be ahead of to read clock, then the state of counter is to count downwards, the up/down counter is counted downwards by 111, when counting down to 100, up/down counter output increase control signal, adding/the subtract pulse circuit in, add pulse control signal and in the signal that enters 16 frequency dividing circuits, increase a high-speed pulse, make the corresponding 7.5ns that moved forward of the phase place read clock write the phase place of clock like this, dwindle the phase difference of writing clock and reading clock with tracking.Otherwise, when the output lead-lag of phase discriminator allows signal lag when reading clock, the up/down counter is the count status that makes progress, the up/down counter is upwards counted by 000, when counting down to 011, the signal that output subtract pulse control signal will enter 16 frequency dividing circuits reduces by a high-speed pulse, has moved 15ns after the feasible like this phase place of reading clock is corresponding.After aforesaid operations was whenever finished a phase place adjustment, the up/down counter all resetted.

The plus-minus pulse control circuit adds pulse and subtract pulse signal according to up/down counter output, adds among the XCLK2D or detains a high-frequency impulse, reaches the purpose in control signal cycle, realizes phase-locked function behind frequency dividing circuit.XCLK2D is the high frequency clock that is subjected to the ADD/SUB signal controlling, is the clock signal behind the XCLK two divided-frequency.

Fig. 5 is for adding and subtracting the situation that pulse control circuit adds pulse and subtract pulse, and XCLK is a reference clock, and the frequency of XCLK is 32 times of input signal centre frequency.Add/the subtract pulse control circuit in fact also is a counter, this counter carries out two divided-frequency to high frequency reference clock XCLK at ordinary times, when a subtract pulse occurring, just detain in this counter output sequence and remove a high-frequency impulse, when one of appearance added pulse, output sequence just added a high-speed pulse.The cycle of the clock signal that the output of this counter obtains after 16 frequency divisions are handled and phase place are adjusted and control, and frequency and phase place final and input signal are locking relation.

Lockout feature for loop is analyzed as follows, and reference clock XCLK of the present invention is 65.536MHz, and the up/down counter is three.The clock frequency of up/down counter is XCLK, and wherein fc is 2.048MHz for exporting the centre frequency of reading clock, the free oscillation frequency of phase-locked loop under promptly non-locking (or synchronously) state.And the upwards counting of 3 up/down counters and downwards the counting control impuls determine by phase discriminator output, the therefore cycle of add-subtract control pulse and the phase difference of phase discriminator as can be known, system clock is relevant with the count value of up/down counter.System clock cycle is low more, the count value of counter is big more, then add pulse and subtract pulse regulating impulse repetition rate is low, it is long that loop enters the synchronous time, lock-in range is narrow, so it is 000 that the present invention sets the initial value of up/down counter, the rolling counters forward device remembers 100 by 111 downwards, output control signal subtract pulse is set the counter that makes progress and is remembered 011 by 000, and the output control signal adds pulse, the count value of this counter is 3, add pulse and subtract pulse regulating impulse repetition rate height, it is short that loop enters the synchronous time, and lock-in range is wide.

Add/clock frequency of the input of subtract pulse circuit is XCLK, loop center frequency f c is:

$\begin{array}{cc}\mathrm{fc}=\frac{\mathrm{XCLK}}{2N}& N=16\end{array}$

The clock frequency of the output of plus-minus pulse control circuit is:

$\begin{array}{ccc}\mathrm{Fadd}/\mathrm{sub}=\frac{\mathrm{Kd\θeMfc}}{2K}& K=3,& M=32\end{array}$

The frequency of the read clock signal of the output of phase-locked loop is:

$\mathrm{RD}\_\mathrm{CLK}=\mathrm{fc}+\frac{\mathrm{Kd\θe}*\mathrm{Mfc}}{2\mathrm{NK}}$

$\mathrm{RD}\_\mathrm{CLK}=2.048\mathrm{MHz}+\frac{\mathrm{Kd\θe}*65.536\mathrm{MHz}}{2*16*3}$

Wherein, Kd is the linear gain of phase discriminator, and θ e is the phase difference of input signal and output signal, and N is 16, and K is the count value 3 of up/down counter, and fc is 32 frequency divisions of system clock, and system clock is 65.536MHz.

The maximum of Kd θ e is ± 1, and then the lock-in range of loop is:

$\frac{2}{3}\≤\frac{\mathrm{RD}\_\mathrm{CLK}}{\mathrm{fc}}\≤\frac{4}{3}$

In sum, adopt the present invention, be easy to realize going to tremble function, thereby can generally be suitable for.Simultaneously, circuit structure of the present invention is easy to integrated and low frequency to go to tremble effect fine, the tolerable system clock is shake and drift for a long time, low frequency goes to tremble characteristic and high frequency goes to tremble the requirement that characteristic can both satisfy ITU.TG.823.

Claims (5)

1, a kind of de-twitter circuit based on digital phase-locked loop (100) comprises, the FIFO memory: its input signal is the clock of writing of outside input, the data of outside input and phase-locked loop output read clock, from the FIFO memory, export after removing the signal of shake; The FIFO memory is also exported two control signals and is reported its store status promptly fast full and fast dummy status to digital phase-locked loop (100); It is characterized in that, also comprise digital phase-locked loop (100), described digital phase-locked loop (100) comprises 32 frequency multiplier circuits, input clock is along testing circuit (202), phase discriminator (200), the up/down register adds/the subtract pulse circuit, remove 2 circuit, remove 16 circuit (201) and output clock along testing circuit (203);

Described 32 frequency multiplier circuits carry out 32 frequencys multiplication with the low frequency system clock of outside input, and with the high-frequency clock that obtains as the inner reference clock of digital phase-locked loop (100);

Described input clock is output as the signal of writing after clock phase detects along the write clock signal that is input as of testing circuit (202);

Described output clock is output as the signal of reading after clock phase detects along the read clock signal that is input as of testing circuit (203);

Described phase discriminator (200) be input as the reading and writing clock along detection signal, be output as lead-lag and allow signal, write clock with sign and be ahead of and read clock or lag behind to read clock;

The lead-lag that is input as of described up/down counter allows signal, reads clock and reference clock, is output as the plus-minus pulse control signal;

Output adds pulse signal and subtract pulse signal to described adding/subtract pulse circuit according to the add-subtract control signal, and is input to the output of regulating frequency-halving circuit in the frequency-halving circuit;

Described frequency-halving circuit be input as reference clock, add pulse and subtract pulse signal, be output as controlled two divided-frequency clock; Described two divided-frequency clock is input to and carries out frequency division in 16 frequency dividing circuits to obtain the needed clock of writing;

Above-mentioned digital phase-locked loop (100) is used to provide narrow-band filtering, to obtain a clock that shake is very little; Described digital phase-locked loop (100) be input as the external write clock, be output as and read clock; Described digital phase-locked loop (100) is by reading the phase place that clock and the bit comparison adjustment mutually of writing clock are read clock, make it and write clock synchronization, like this through phase-locked loop output read clock again with the taking-up from the FIFO memory of the data of input the time, will obtain the signal that the shake of clock and data all reduces greatly.

2, de-twitter circuit as claimed in claim 1 is characterized in that: the frequency of this reference clock of high-frequency clock that obtains by described 32 frequency multiplier circuits is 65.536M.

3, de-twitter circuit as claimed in claim 1 or 2, it is characterized in that: described input clock comprises shift register and AND circuit along testing circuit (202), write clock under the sampling of reference clock, the signal of its displacement output is through after reverse, with write clock and send into AND circuit respectively, through with computing after, what output signal was promptly write clock delivers to the input of phase discriminator (200) along detection signal.

4, de-twitter circuit as claimed in claim 1 or 2 is characterized in that: described output clock comprising along testing circuit (203): first with door, second with door and or door, first receives from removing the Q that 16 circuit are exported with door ₁, Q ₂, Q ₃Signal and Q ₄Reverse signal; Second receives from the Q that removes 16 circuit with door ₁, Q ₂, Q ₃Output reverse signal and Q ₄Signal; These two with the output of door by or door carry out exclusive disjunction, what resulting output result promptly read clock delivers to the input of phase discriminator (200) along detection signal.

5, de-twitter circuit as claimed in claim 1 or 2 is characterized in that: described phase discriminator (200) is by constituting with door.

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