CN1423270A - System for detecting signal dither and its correcting method - Google Patents
System for detecting signal dither and its correcting method Download PDFInfo
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- CN1423270A CN1423270A CN 01139890 CN01139890A CN1423270A CN 1423270 A CN1423270 A CN 1423270A CN 01139890 CN01139890 CN 01139890 CN 01139890 A CN01139890 A CN 01139890A CN 1423270 A CN1423270 A CN 1423270A
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Abstract
The system is utilized to detect the time interval between the upper edge, the lower edge of the high-speed data stream read out by the optical drive and the referent pulse (so called signal dithering). The radio frequency signal read out by the optical head is near the central standard position of the analog radio frequency signal. It is the approximate the proportional relation between the amplitude variation and the image variation. The dithering value is calculated out by equalizing the difference of the voltage to the difference of the time.
Description
Technical field
The invention belongs to the system and the bearing calibration thereof of the shake of a kind of detection signal, is the signal jitter that is applied to detect the data stream of digital display circuit at a high speed, particularly relates to the apparatus and method that a kind of utilization turns to voltage differences the detection signal shake of time difference.
Background technology
In the past few years, " signal jitter " (jitter) become a kind of characteristics of signals that many engineering staffs pay much attention to, this is because in digital display circuit at a high speed, " rise time " of signal, (rise times) became more and more very briefer, therefore as long as the arithmetic speed of system increases a megabits per second number (Mbps), signal rising edge or the slight variations of drop edge all can produce bigger influence." skew " of signal waveform (skew) or " phase error " (data jitter) not only can influence data " integrality " (integrity) with " time is set " (setup time) and " retention time " (hold time) of signal voltage, also can allow more difficult transfer rate and the transmitting range of taking into account signal of system, finally allow the design engineer can only make the product of a low usefulness.
Therefore, signal jitter not only is used for estimating the CD-ROM drive quality, it also is the important evidence that servo-drive system is adjusted its controlled variable, and the application of CD-ROM drive (including DVD, VCD, CD) becomes the synonym on the audio-visual multimedia already, many electronic games be equipped with DVD-ROM and in this field fast the development in the middle of, just like CD-ROM drive can't deviate from the storage area and the memory speed at a high speed of high power capacity, yet begin the optical disc that adopts certainly so far, the CD-ROM drive survey instrument that in the industry cycle possesses specialty is very few, so just more apparent quite important of the measurement of signal jitter.
And the existing detection mode that is used for the CD-ROM drive signal jitter can be divided into: (1) pulse wave counting mode, and directly utilization metering pulses is more at a high speed counted the time interval between two signal pulse waves, and the metering pulses number of this variation is identified as signal jitter.(2) integral way utilizes the quick point circuit to convert the time interval between two signal pulse waves the variation of voltage to, and signal jitter is used as in the variation that utilizes analog/digital converter to get its voltage then.(3) radio frequency (RF) signal pulse wave is inputed to oscillograph, watch the sharpness of " ocular form figure " (eye pattern) by oscillograph.
But for the CD-ROM drive data stream of high power speed, the frequency of its data stream is quite high, and the pulse wave counting mode needs metering pulses more at a high speed can detect signal jitter, and the resolution of signal jitter is subject to the frequency of metering pulses.And the quick point mode needs bigger frequency range equally, and influenced by the saturated or drift of circuit.So servo-drive system adjustment for high power speed CD-ROM drive, generally all adopt the third detection mode, directly watch signal jitter, signal jitter can't be quantized, and the servo-drive system that provides that can't be real-time is adjusted the reference of controlled variable but only rely on watching also of naked eyes by oscillograph.
Summary of the invention
Technical matters to be solved by this invention provides the system and the bearing calibration thereof of a kind of detection signal shake, can detect the signal jitter that data stream that the high speed CD-ROM drive read produces, and can provide servo-drive system to adjust the reference of controlled variable in real time.
To achieve these goals, the invention provides the system and the bearing calibration thereof of the shake of a kind of detection signal, be used for separately measuring digital slicing signal upper limb and the time interval of lower edge change and near the variation of the RF voltage of the reference pulse of the accurate signal in center; It includes a data slicer, one data phase-locked loop, one logic control, one internal memory, one counter and a microprocessor, data slicer provides the centre bit calibration signal of analog radio-frequency signal and utilizes the centre bit calibration signal to convert analog radio-frequency signal to digital slicing signal, and the data phase-locked loop is used to produce a stable reference pulse, two analog/digital converters can be respectively to analog radio-frequency signal and the sampling of centre bit calibration signal, logic control can be accepted the triggering of digital slicing signal, take a sample and drive analog/digital converter, and export the direction signal of the trigger position of a latch-up signal and the digital slicing signal of a record, internal memory can store the sampling and the direction signal of analog radio-frequency signal and centre bit calibration signal, but counter then receive logic control latch-up signal and to its counting and exported the address that becomes internal memory, microprocessor is in order to control counter, the input of internal memory and analog/digital converter, output and start.
Down along further specifying purpose of the present invention, structural attitude and function thereof in conjunction with the accompanying drawings.
Description of drawings
Fig. 1 is the schematic representation of apparatus of detection signal shake of the present invention;
Fig. 2 is the synoptic diagram of signal waveform of the present invention;
Fig. 3 is the synoptic diagram of data slicer of the present invention;
Fig. 4 is the synoptic diagram of data of the present invention phase-locked loop;
Fig. 5 is the synoptic diagram of the change in voltage of the analog radio-frequency signal in the witness mark recurrence interval of the present invention;
Fig. 6 is the waveform synoptic diagram of the present invention the 5th figure;
The synoptic diagram that Fig. 7 postpones for sample signal of the present invention; And
The flow chart of steps that Fig. 8 proofreaies and correct for signal jitter of the present invention.
Embodiment
The system and the bearing calibration thereof of disclosed detection signal shake according to the present invention, at first, after according to the DVD specifications signal jitter (jitter) being defined as disc data that the CD-ROM drive read head reads and amplifying through prime, produce an analog radio frequency (RF) signal, and after by cutter (Slicer) analog radio-frequency signal being encoded to binary signal (Binary signal), become a slicing signal (Sliced_RF), the time interval of the upper limb of slicing signal and lower edge change is with respect to reference pulse (PLL clock signal; PLCK) cycle.And know radio frequency (RadioFrequency according to the characteristic of optics; RF) near the accurate position of the heart, amplitude of vibration changes with the time and changes the approximate ratio relation signal therein, therefore this kind voltage differences etc. can be turned to a kind of time difference.When data stream had signal jitter to produce, the voltage of radiofrequency signal also can and then change.Therefore, detection signal when shake, separately measure near the variation of voltage of radiofrequency signal in an accurate reference pulse cycle of the time interval and analog radio-frequency signal center of slicing signal upper limb and lower edge change.
In Fig. 1, after at first the disc data that is read by the CD-ROM drive read head is amplified through prime, produce an analog radio-frequency signal RF ', input to pick-up unit provided by the present invention then.Because be subjected to that servo-drive system departure, signal interfere with each other, the influence of factors such as the error of disc player assembling tolerance, disc defective, optical channel model and noise, this analog radio-frequency signal RF ' has high-frequency signal jitter.The analog radio-frequency signal RF ' of this shake produces a digital slicing signal Sliced_RF ' through data slicer 1 (Data Slicer), after then digital slicing signal Sliced_RF ' being adjusted through data phase-locked loop 2, then can produce a stable reference pulse PLCK '.If with respect to reference pulse PLCK ', the upper limb of this digital slicing signal Sliced_RF ' triggers with lower edge and triggers and can signal jitter (Jitter) occur in small time interval.The present invention mainly is that the time and the analog radio-frequency signal RF ' that utilize digital slicing signal Sliced_RF ' upper limb or lower edge to trigger appearance change an approximate linear relationship, calculates this small time interval.
The at first output of data slicer 1 numeral slicing signal Sliced_RF ' and data phase-locked loop 2 (phase-locked loop; PLL) output reference pulse PLCK ' inputs to logic control 3 (Logic Control), through producing sample signal Sample after the logical operation, direction signal Dir and latch-up signal Latch_1, wherein sample signal Sample allows accurate position, the center signal Slice level ' of analog/digital converter 5 sampling simulation radiofrequency signal RF ' and analog/digital converter 4 sampling simulation radiofrequency signal RF ', and latch-up signal Latch_1 only triggers or lower edge triggers when occurring at the upper limb of digital slicing signal Sliced_RF ', the Fang Huiyou pulse occurs, and its purpose is at the input signal of being used as counter 7 and permission analog/ digital converter 4,5 output data is sent to internal memory 8 via impact damper 6.It is that upper limb or lower edge trigger that direction signal Dir is writing down digital slicing signal Sliced_RF ', and exports impact damper 6 to.The output of counter 7 is then as the position control of internal memory 8.
When the signal jitter that detects is wanted to pass internal memory 8, microprocessor 9 is sent clear signal Clear earlier and is removed counter 7, (address) makes zero with the core position, Shu Chu Enable then, WR, the RD signal is all noble potential, Enable wherein, WR signal latch enable signal Latch_1 enters counter 7, the RD signal allows analog/ digital converter 4,5 output data and direction signal Dir are sent to internal memory 8, when the upper limb of digital slicing signal Sliced_RF ' triggers (or lower edge triggering) when occurring, sample signal Sample can trigger analog/ digital converter 4,5 read accurate position, center signal Slice level ' and analog radio-frequency signal RF ' respectively, latch-up signal Latch_1 sends sampling value in the internal memory 8 to then, and counter 7 is added one.
On the other hand, want to read internal memory 8 data when microprocessor 9 and come signal calculated when shake, can allow the Enable signal be electronegative potential, then latch-up signal Latch_1 can't input to counter 7 by AND logic lock 10, and send the RD signal of an electronegative potential to give impact damper 6, do not allow analog/ digital converter 4,5 data that read input to internal memory 8, then by changing the output that the WR signal changes counter 7, the value that is stored in internal memory 8 is inputed to microprocessor 9 computings one by one, and this moment, digital slicing signal Sliced_RF ' big young pathbreaker of shake and ratio cut accurate position, center signal Slice level ' in the analog radio-frequency signal RF ' of sampling.
In Fig. 2, the cycle of hypothetical reference pulse PLCK ' is T, and output Enable, the WR of microprocessor 9, RD signal are all noble potential, and analog/digital converter the 4, the 5th, trigger with the upper limb of sample signal Sample, and analog radio-frequency signal RF ' has the signal jitter of 0.25T.All do not have the upper and lower edge of digital slicing signal Sliced_RF ' signal jitter to occur near the first sampling spot P1 the positive and negative 0.5T, then allow sample signal Sample along with reference pulse PLCK ' change, and latch-up signal Latch_1 still remains in electronegative potential.At second sampling spot P2, because the lower edge (or upper limb) of the interior digital slicing signal Sliced_RF ' signal of positive and negative 0.5T occurs signal jitter near the sampling spot, allow this moment sample signal Sample keep the noble potential of 1.5T, the pulse signal of 0.5T then appears keeping in latch-up signal Latch_1 in the place of the distance second sampling spot P20.5T.The voltage of accurate position, analog/digital converter 4 sampling centers this moment signal Slice level ' sampling spot A ' and the signal of analog/digital converter 5 sampling simulation radiofrequency signal RF ' sampling spot B ', latch-up signal Latch_1 is when lower edge then, the output data of analog/ digital converter 4,5 can be sent to internal memory 8 and flip-flop number 7 countings, the position of internal memory 8 is added one.Do not have near the 3rd sampling spot P3 the positive and negative 0.5T signal jitter to occur at upper limb or the lower edge of digital slicing signal Sliced_RF ' yet, thus allow sample signal Sample along with reference pulse PLCK ' change, and latch-up signal Latch_1 still keeps electronegative potential.
And data slicer 1 is made up of with the accurate correction 13 of the centre bit of numeral Hi-pass filter 11 (High Pass Filter), comparer 12 (Comparator).In Fig. 3, the accurate correction 13 of the centre bit of numeral is made up of with low-pass filter 132 (Low PassFilter) counter 131, digital/analog converter 133, its purpose allows comparer 12 convert analog radio-frequency signal RF ' to digital slicing signal Sliced_RF ' according to accurate position, center signal Slice level ' at accurate position, the center that an analog radio-frequency signal RF ' is provided signal Slicelevel '.
In Fig. 4, data phase-locked loop 2 includes phase detectors 22, frequency detector 21, low-pass filter 23, voltage control oscillator 24 and frequency eliminator 25, its purpose is according to the digital slicing signal Sliced_RF ' of input, produces stable reference pulse PLCK '.
And near the variation of the analog radio-frequency signal voltage of a reference pulse accurate position, detection analog radio-frequency signal center, in Fig. 5, hypothetical simulation/digital quantizer 54 and 55 all triggers sampling with upper limb, reference pulse PLCK with 52 generations of data phase-locked loop " through two xor logic locks 58; 59 produce reference pulse PLCK_d ;-PLCK_d; its phase differential 180 degree; please be simultaneously with reference to Fig. 6; this two reference pulse PLCK_d,-PLCK_d triggers analog/digital converter 54 respectively, 55 sampling simulation radiofrequency signal RF ", allow analog/digital converter 54; the analog radio-frequency signal RF of 55 samplings " at a distance of 1/2 reference pulse PLCK " and cycle (1/2T just).With reference pulse PLCK " with digital slicing signal Sliced_RF " input to logic control 53, as digital slicing signal Sliced_RF " when shake appears in upper limb or lower edge; logic control 53 can be at next reference pulse PLCK " go up or after lower edge occurs, a latch-up signal Latch_2 is with analog/digital converter 54 in d output time delay, 55 output data (data of sampling spot E ' and F ') is locked in the impact damper 56, and the data in the notice microprocessor 57 processing impact dampers 56, and wherein, as the digital slicing signal Sliced_RF of logic control 53 detecting " lower edge when shake occurring; latch-up signal Latch_2 of 0.25T output time delay, and the noble potential of latch-up signal Latch_2 also is to keep 0.25T.And d time delay of latch-up signal Latch_2 need allow analog/digital converter 54,55 convert, and before next sampling spot G ' takes place.Though the value that both read all has drift amount (Offset) to exist, but both subtract each other 1/2 reference pulse PLCK that the back produces " analog radio-frequency signal RF " change in voltage then can eliminate this drift amount, is the analog radio-frequency signal RF that wants if the result is taken advantage of 2 times " near the reference pulse PLCK accurate position, center " analog radio-frequency signal RF " change in voltage.Therefore, according to the shake of the digital slicing signal Sliced_RF that measures with detect a reference pulse PLCK " analog radio-frequency signal RF " variation of voltage, microprocessor just can calculate the signal jitter amount.
On the other hand, though can utilize analog radio-frequency signal RF ' to change the time interval of the signal jitter of knowing digital slicing signal Sliced_RF ', but, comparer 12 needs a period of time with logic control 3 computing sample signal Sample because converting analog radio-frequency signal RF ' to digital slicing signal Sliced_RF ', so having the time, the sample signal Sample that produces postpones, and utilize this sample signal Sample to remove to trigger analog/ digital converter 4,5 read analog radio-frequency signal RF ' and accurate position, center signal Slice level ', there is a fixing drift value to exist the numerical value that causes the analog radio-frequency signal RF ' of detection, see also Fig. 7, suppose that comparer 12 is Delay_1 with the time delay that analog radio-frequency signal RF ' converts digital slicing signal Sliced_RF ' to, the time delay of logic control 3 computing sample signal Sample ' is Delay_2, then the sampling spot of analog radio-frequency signal RF ' will be by original C ' point drifts to D ' point, and the drift direction is that lower edge or upper limb triggering are relevant with digital slicing signal Sliced_RF ', when digital slicing signal Sliced_RF ' is the upper limb triggering, this moment, the analog radio-frequency signal RF ' of sampling was bigger, and digital slicing signal Sliced_RF ' signal is when to be lower edge trigger, and this moment, the analog radio-frequency signal RF ' of sampling was less.Based on this cause, so need the time delay be compensated to this.
As shown in Figure 8, the step that signal jitter of the present invention is proofreaied and correct is as follows: step 801, at first set initial value; Step 802, the scope (delta), number of times scope (range), drift value (offset) and the number of times (counter) that include the drift compensation, then make drift value (offset) equal the scope (delta) that former drift value adds the drift compensation, and number of times (counter) add one; Step 803, and the position of judgement signal jitter; Step 805 just utilizes direction signal Dir to judge that signal jitter is to occur in upper limb or lower edge, is to be triggered by the upper limb of digital slicing signal Sliced_RF ' to cause as judgement, and then the value RF ' that will read deducts drift value (offset); Step 804 triggers when causing if direction signal Dir is expressed as lower edge, and then RF ' the value of the value that will read adds the drift value; Step 806 is calculated signal jitter at this moment in the mode of statistics; Step 807, and judge whether to be positioned at the number of times scope; Step 808,809 is found out a drift value that allows the signal jitter minimum in compensation range, be used as the RF ' that causes because of circuit delay and change, and so, can finish the action of correction.
The present invention is the system and the bearing calibration thereof of detection signal shake, came the detection signal shake owing to utilize the mode of integration or counting in the past, it all is the phase differential that directly compares between two high-speed pulses, only amplification mode of difference is the mode with integration or counting, so the operating frequency of detection system needs the operating frequency much larger than CD-ROM system.
The present invention then knows RF (Radio Frequency) signal therein near the accurate position of the heart from the characteristic of optics, and amplitude of vibration changes with the time and changes the approximate ratio relation, and this kind voltage differences etc. is turned to a kind of time difference.When data stream had signal jitter to produce, the measured RF voltage of analog/digital converter also can and then change.
For at a high speed or for the disc player of following high power capacity, the present invention only needs come the detection signal shake at the upper and lower edge of the signal of data stream, so the required operating frequency of testing circuit is lower, feasibility is also higher.And the signal jitter that detects can quantize, if this detection module is incorporated among the servo DSP, allows the deviser adjust needed servo parameter automatically directly according to the signal jitter size.
Foregoing is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; All equivalent variations and modifications of being done according to inventive concept hand spirit are all contained by scope of patent protection of the present invention.
Claims (9)
1. the system of a detection signal shake is used to detect the shake of an analog radio frequency (RF) signal, includes:
One data slicer provides a centre bit calibration signal of described analog radio-frequency signal and utilizes described centre bit calibration signal to convert described analog radio-frequency signal to a digital slicing signal;
One data phase-locked loop is used to produce a reference pulse;
Two analog/digital converters are respectively to described analog radio-frequency signal and the sampling of described centre bit calibration signal;
One logic control can be accepted the triggering of described digital slicing signal, drives described analog/digital converter sampling, and exports the direction signal of the trigger position of a latch-up signal and the described digital slicing signal of a record;
One internal memory can store the sampling and the direction signal of described analog radio-frequency signal and described centre bit calibration signal;
One counter receives the latch-up signal of described logic control and its counting is also exported the address that becomes described internal memory; And
One microprocessor is used to control input, output and the start of described counter, internal memory and analog/digital converter.
2. the system of detection signal shake as claimed in claim 1, it is characterized in that: the trigger position of described digital slicing signal is the upper limb of described digital slicing signal.
3. the system of described detection signal shake as claimed in claim 1, it is characterized in that: the trigger position of described digital slicing signal is the lower edge of described digital slicing signal.
4. the system of detection signal shake as claimed in claim 1, it is characterized in that: also include an impact damper, the signal that can transmit according to described microprocessor and described logic control is sent to described internal memory with described analog radio-frequency signal and the sampling of described centre bit calibration signal and direction signal.
5. the system of a detection signal shake is used to utilize a pick-up unit to detect the variation of the voltage of the analog radio-frequency signal in the reference pulse cycle, it is characterized in that described pick-up unit includes:
One data slicer provides a centre bit calibration signal of an analog radio-frequency signal and utilizes described centre bit calibration signal to convert described analog radio-frequency signal to a digital slicing signal;
One data phase-locked loop is used to produce a reference pulse;
Two analog/digital converters, respectively to described analog radio-frequency signal sampling, and sampling spot is respectively before and after the triggering of digital slicing signal;
One logic control detects described digital slicing signal when triggering is arranged, and can postpone latch-up signal of time output after the described reference pulse of the next one occurs; And
One microprocessor is accepted described latch-up signal and the sampling in the described analog/digital converter is handled.
6. the system of detection signal shake as claimed in claim 5 is characterized in that described two sampling spots are the cycle at a distance of described reference pulse.
7. the system of detection signal as claimed in claim 5 shake is characterized in that described two sampling spots are at a distance of half of cycle of this reference pulse.
8. the system of detection signal shake as claimed in claim 5 is characterized in that described two sampling spots are the twice at a distance of the cycle of this reference pulse.
9. bearing calibration that is used for signal jitter includes the following step:
Set the initial value of scope, number of times scope, drift value and the number of times of drift compensation;
Judge the signal jitter occurrence positions;
Utilize the mode of statistics to calculate signal jitter at this moment; And
Getting one in described compensation range allows the drift value of signal jitter minimum be change in voltage.
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| CN 01139890 CN1423270A (en) | 2001-12-04 | 2001-12-04 | System for detecting signal dither and its correcting method |
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| CN 01139890 CN1423270A (en) | 2001-12-04 | 2001-12-04 | System for detecting signal dither and its correcting method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100426250C (en) * | 2005-07-18 | 2008-10-15 | 鸿富锦精密工业（深圳）有限公司 | Device and method for detecting system main board receiving signal sensitivity |
| CN100501691C (en) * | 2005-06-10 | 2009-06-17 | 鸿富锦精密工业（深圳）有限公司 | Device and method for measuring receiving signal sensitivity of adapter card |
| CN100517493C (en) * | 2005-03-10 | 2009-07-22 | 松下电器产业株式会社 | Jitter detection apparatus |
| CN1870159B (en) * | 2005-05-25 | 2010-05-05 | 联咏科技股份有限公司 | Digit document cutting circuit and cutting method |
| CN101079298B (en) * | 2006-05-22 | 2010-05-12 | 广明光电股份有限公司 | Optical drive signal processing method |
| CN1963936B (en) * | 2005-11-08 | 2010-05-12 | 凌阳科技股份有限公司 | Correction system for error of block code and correction method |
| CN101349717B (en) * | 2007-07-16 | 2011-09-28 | 奇景光电股份有限公司 | Jitter measuring device and method |
| CN102413286A (en) * | 2011-12-07 | 2012-04-11 | 大道计算机技术(上海)有限公司 | Unsteady signal self-adaptive processing method based on round-robin |
| CN107271890A (en) * | 2017-06-14 | 2017-10-20 | 电子科技大学 | A kind of jittered device of train pulse part trailing edge |
| CN111190089A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method and device for determining jitter time, storage medium and electronic equipment |
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- 2001-12-04 CN CN 01139890 patent/CN1423270A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100517493C (en) * | 2005-03-10 | 2009-07-22 | 松下电器产业株式会社 | Jitter detection apparatus |
| CN1870159B (en) * | 2005-05-25 | 2010-05-05 | 联咏科技股份有限公司 | Digit document cutting circuit and cutting method |
| CN100501691C (en) * | 2005-06-10 | 2009-06-17 | 鸿富锦精密工业（深圳）有限公司 | Device and method for measuring receiving signal sensitivity of adapter card |
| CN100426250C (en) * | 2005-07-18 | 2008-10-15 | 鸿富锦精密工业（深圳）有限公司 | Device and method for detecting system main board receiving signal sensitivity |
| CN1963936B (en) * | 2005-11-08 | 2010-05-12 | 凌阳科技股份有限公司 | Correction system for error of block code and correction method |
| CN101079298B (en) * | 2006-05-22 | 2010-05-12 | 广明光电股份有限公司 | Optical drive signal processing method |
| CN101349717B (en) * | 2007-07-16 | 2011-09-28 | 奇景光电股份有限公司 | Jitter measuring device and method |
| CN102413286A (en) * | 2011-12-07 | 2012-04-11 | 大道计算机技术(上海)有限公司 | Unsteady signal self-adaptive processing method based on round-robin |
| CN102413286B (en) * | 2011-12-07 | 2013-08-14 | 大道计算机技术(上海)有限公司 | Unsteady signal self-adaptive processing method based on round-robin |
| CN107271890A (en) * | 2017-06-14 | 2017-10-20 | 电子科技大学 | A kind of jittered device of train pulse part trailing edge |
| CN107271890B (en) * | 2017-06-14 | 2019-07-12 | 电子科技大学 | A kind of jittered device of train pulse part failing edge |
| CN111190089A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method and device for determining jitter time, storage medium and electronic equipment |
| CN111190089B (en) * | 2018-11-14 | 2022-01-11 | 长鑫存储技术有限公司 | Method and device for determining jitter time, storage medium and electronic equipment |
| US11733293B2 (en) | 2018-11-14 | 2023-08-22 | Changxin Memory Technologies, Inc. | Method and apparatus for determining jitter, storage medium and electronic device |
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