CN1402881A - 半导体电路布置及其生产方法 - Google Patents
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Abstract
本发明涉及半导体电路布置，在第一导电类型的基底(1)中具有整体形成的电路元件，其中包括至少一个控制电极(G1，G2)及第一(D)和第二(S)电极连接。根据本发明，在所述半导体基底主表面的背侧，至少一个控制电极至少部分硅化。
Description
技术领域
本发明涉及半导体电路布置，在第一导电类型的基底中具有整体形成的电路元件，其中至少包括一个控制电极及第一和第二电极连接，并且涉及这样的半导体电路布置的生产方法。
背景技术
例如，对于这样的半导体电路布置，已知具有多个控制电极的MOS四极管和MOS五极管，特别是具有两个栅极连接，也就是一个高频栅极和至少一个控制栅极；在半导体基底上，半导体电路布置或者作为分离元件或者以高度集成形式，通过VLSI(超大规模集成)技术制造。特别是在汽车领域，通过使用这样的MOS四极管，需要适应12V和更高电源电压的能力。现代的CMOS制造过程通常只被设计用于生产适应＜＝5V电源电压的半导体电路布置，而由此并不表示毫不困难就能生产适应更高电源电压的半导体电路。对此，在生产半导体电路布置的现代标准CMOS工艺过程中，基于工艺条件上的考虑，难点在于太小的栅极氧化体，以及太低的漏极击穿电压，因此，并非轻而易举就能够生产适应12V或更高电源电压的MOS四极管和MOS五极管。
进一步，重要的是这样的MOS四极管和MOS五极管的高频性能，由此，首先，栅极连接的总电阻，并且特别是高频栅极的总电阻的问题是，四极管中高频栅极的阻抗噪扰增强，由此确定元件的噪声特性。除此之外，伴随栅极电阻升高，可达到的高频峰值降低。对于MOS四极管生产过程，为了得到尽可能小的栅极电阻，由此全部使用了金属栅极，其典型值为大约RS＝40mΩ/□大致量级的膜电阻，小于在CMOS过程通常使用的栅极聚合体，它具有典型膜电阻大约RS＝20m到150Ω/□。
发明内容
本发明基于这样的任务给出：半导体电路布置，特别是具有多个控制电极的半导体电路布置，也就是至少两个栅极电极，其中的一个是高频栅极，通过使用四极管或五极管来调整，控制电极的栅极电阻，通常通过采用金属栅极，来实现控制电极的栅极电阻相对较小的量级，以及制造这样的半导体电路布置的容易执行的过程。
通过权利要求1限定的方法和权利要求11限定的半导体电路布置，来实现本发明任务的方案。
根据本发明，在半导体基底主表面背向一侧，至少一个最好由多晶硅制成的控制电极部分硅化。由此在前面，对于膜电阻的减小，本发明加入了多晶硅上控制电极的硅化，由此在与前述的金属栅极技术的比较中，可以实现更可比的噪声值。实验已经显示，在多晶硅上的控制电极或栅极不硅化的情况下，噪声本质上更低。对于硅化通过利用TiSi工艺，可以实现大约3Ω/□的膜电路
从后面本发明的描述中可以看到，从硅化物中留下了第一电极连接或漏极连接。理论上，通过根据本发明的自调整硅化过程，栅极区、源极区、中间区和漏极区同时硅化。然而，暴露了硅化的漏极连接具有更差的抵抗静电放电的强度(ESD强度；ESD＝静电放电)。特别是在这样的应用中，通过这个创造性的半导体电路布置，特别是作为分离元件的四极管或五极管，或者在集成电路中，实现作为所谓的I/O晶体管的应用，在这种情况下，使用了具有不足强度的硅化的漏极，应该从硅化物中留下漏极区。
通过本发明的优选实施例可以看到，至少一个控制电极部分硅化。在整个控制电极剩余的硅化区，是具有足够低的总阻抗的控制电极。在控制电极最小长度为大约0.6到大约3.0um，特别是大约1.4um的情况下，控制电极没有硅化的部分能够具有0.2到大约0.8um，特别是0.4um的延伸。
进一步需要规则的栅极一般不被硅化，并且靠近漏极电路的栅极与由此紧邻的栅极之间的中间区域部分硅化。
另一方面，当第一电极连接或漏极连接之一只被部分硅化，并且电极连接(漏极连接)的硅化区域与所属触点之间的距离选择得足够大时，同样根据本发明的原理，能够得到足够的ESD强度。
从进一步的从属权利要求中显示了本发明的优选实施方案。
附图说明
本发明的进一步的特点、优点和用途可以结合附图从后面本发明优选实施例的描述中表现出来。图示显示了：
图1 本发明优选实施例的示意性剖视图；
图2 本发明实施例的示意性剖视图，其中两个栅极部分硅化；
图3 本发明实施例的示意性剖视图，其中不包括通过硅化产生的两个完整的栅极；
图4 本发明实施例的示意性剖视图，其中漏极被部分硅化。
具体实施方式
根据本发明的优选实施例，图1中显示的半导体电路布置包括一个高频MOS四极管，作为集成半导体电路的开关元件。它根据标准CMOS过程生产，已知在p导体类型(根据这些定义，p掺杂＝第一导电类型)的硅化物上提供有半导体基底1，其中整体形成的电路元件显示了在栅极绝缘体12上至少两个多晶硅6的控制电极，即具有沟槽区VT1的高频栅极G1，和经过中间区具有沟槽区VT1的分离的控制栅极G2，以及第一电极连接，即漏极连接D，和第二电极连接，即源极连接S(包括源极So和基底电路Su)。在栅极聚合体G1和G2中，通过沟槽掺杂，沟槽区VT1和VT2可以不同地掺杂，这样，同样分别会n掺杂或p掺杂。在基底1中，通过掺杂形成的p区2作为p阱，而漏极嵌入p+区作为基底电极。参考数字3、4和5指示分别在源极区、漏极区和中间区的低掺杂n-LDD区(LDD＝低掺杂漏极)。特点是栅极G1和G2横向旁边的衬垫7(所谓“衬垫”)上形成绝缘体，参考数字7、8和9指示源极连接S、漏极连接D，以及两个栅极之间的中间区的n+掺杂区，其中，如前述中，通过上述栅极或沟槽和漏极电路中衬垫7，源极S和中间区的每个中的触点8、9和11明显分离。通过容易地放置掩模，调整栅极G2或通道与漏极连接D之间的主要距离。部分或者也会完全使用n+掺杂，将栅极G1和G2掺杂。p阱2在漏极电路D的栅极G2与n+掺杂触点11之间的区域结束。R指示高阻值的电阻。
为了实现绝缘(FOX＝氧化区)、p阱、沟槽区、栅极、LDD电路区、栅极管脚的一侧上的衬垫区、由已知生产过程形成的n+和p+区(例如参见Widmann的“高度集成开关的技术”，Springer出版社，第2版，第5页)，使用了自调整的硅化过程。由此，形成了LPCVD过程(LPCVD＝低压气相沉积)中的TEOS-SiO2膜14(TEOS＝四-乙烯基硅)，并且通过漆包掩模和蚀刻构成。其中确定了连续硅化过程的区域。为了通过将第一硅化物快速热退火(RTA＝快速热退火)，由溅射(阴极射线原子溅射)产生薄的钛膜，也就是提供钛和硅转化成钛化硅TiSi10，并且钛与硅化物接触。通过另外的腐蚀过程，来去掉剩余物，例如没有转化的钛。通过进一步的RTA步骤(两步硅化)，在低阻相(C54)中，高阻相的钛化硅膜(C49)被转化。对于硅化过程需要两个膜，第一膜中不允许使用过高的温度，而需要最佳温度附近的适当温度，例如变成低阻硅化钛的温度。使用高温会存在危险，钛已经与SiO2中的硅反应，并且这导致了在绝缘的硅化区之间导电。由此，过程不只自调整。在2中，硅化过程允许高温，然后发现SiO2上没有钛。通过标准CMOS过程的现有反应步骤，保证了预金属—绝缘物的沉积，及进一步的过程。
进一步，需要所述控制栅极不被硅化，并且靠近漏极连接的栅极与由此紧邻的栅极之间的中间区域部分硅化。
另一方面，当第一电极连接或漏极连接之一只被部分硅化，并且电极连接(漏极连接)的硅化区域与所属触点之间的距离选择得足够大时，同样根据本发明的原理，可以得到足够的ESD强度
在图2、3和4中，再次用放大的剖视图表示了根据本发明的栅极硅化物的原理性改变，其中在图2、3和4中，在更好描述的基础上，只显示了硅化区10、栅极绝缘体12、栅极聚合体13和衬垫7。
图2的实施例符合根据图1具体描述的例子，从而能够在那个描述中被引用。这里至少一个控制电极G2部分硅化。在整个控制电极剩余的硅化区，是具有足够低的总阻抗的控制电极G2。在控制电极最小长度为大约0.6到大约3.0um，特别是大约1.4um的情况下，控制电极没有硅化的部分能够具有0.2到大约0.8um，特别是0.4um的延伸。
通过图3的特定实施例，G1与G2之间彼此分离的区域部分硅化，控制电极G2和漏极不硅化。然而，这一实施例的效果不比图2的特定优选实施例更差
通过图4的特定实施例，漏极区部分硅化。当漏极连接的硅化区与漏极触点之间的距离选择得足够大时，那么在这种情况下能够得到足够的ESD强度。
参考符号列表
1 半导体基底
2 P区
3、4、5 低掺杂nLDD区
6 多晶硅
7 衬垫
8、9、11 n+掺杂触点区
10 硅化区
12 栅极绝缘体
13 栅极聚合体
14 TEOS-SiO2膜
G1 高频栅极
G2 控制栅极
D 漏极连接
S 源极连接
VT1、VT2 沟槽区
Claims (20)
1.一种制造半导体电路布置的方法，在第一导电类型的半导体基底(1)上具有整体形成的电路元件，其中包括至少一个控制电极(G1、G2)及第一(D)和第二(S)电极连接，
其特征在于，
在其半导体基底主表面的背侧，至少一个控制电极至少部分硅化。
2.根据权利要求1的方法，
其特征在于，
通过硅化形成的第一电极连接(D)被保留。
3.根据权利要求1和2的方法，
其特征在于，
至少第一电极连接(D)根据需要被部分硅化。
4.根据权利要求1到3的方法，
其特征在于，
至少控制电极(G2)只被部分硅化。
5.根据权利要求1到4的方法，
其特征在于，
所述半导体电路布置包括相邻布置的两个控制电极(G1、G2)，并且电极连接的一个完全硅化，而另一个控制电极不硅化，或者只部分硅化。
6.根据权利要求1到5的方法，
其特征在于，
通过自调整的硅化方法，进行至少一个控制电极和/或至少一个电极连接的硅化。
7.根据权利要求1到6的方法，
其特征在于，
通过硅化钛(TiSi)、硅化钨(WSi)或其它相应的高温稳定性含金属硅化合物的硅化被执行。
8.根据权利要求1到7的方法，
其特征在于，
至少一个控制电极包括多晶硅。
9.根据权利要求1到8的方法，
其特征在于，
所述半导体电路布置具有至少两个控制电极的分离元件。
10.根据权利要求1到9的方法，
其特征在于，
所述半导体电路布置具有至少两个控制电极的高频晶体管。
11.半导体电路布置，在第一导电类型的半导体基底(1)上具有至少整体形成的开关元件，其中包括至少一个控制电极(G1、G2)以及第一(D)和第二电极连接(S)，
其特征在于，
在所述半导体基底主表面的背侧，至少一个控制电极至少部分硅化
12.根据权利要求11的半导体电路布置，
其特征在于，
通过硅化形成的第一电极连接(D)被保留。
13.根据权利要求11或12的半导体电路布置，
其特征在于，
至少第一电极连接(D)根据需要被部分硅化。
14.根据权利要求11到13的半导体电路布置，
其特征在于，
至少控制电极(G2)只被部分硅化。
15.根据权利要求1 1到14的半导体电路布置，
其特征在于，
所述半导体电路布置包括相邻布置的两个控制电极(G1、G2)，并且电路连接的一个完全硅化，而另一个控制电极不硅化，或者只部分硅化。
16.根据权利要求11到15的半导体电路布置，
其特征在于，
通过自调整的硅化方法，进行至少一个控制电极和/或至少一个电极连接的硅化。
17.根据权利要求11到16的半导体电路布置，
其特征在于，
通过硅化钛(TiSi)、硅化钨(WSi)或其它相应的高温稳定性含金属硅化合物的硅化被执行。
18.根据权利要求11到17的半导体电路布置，
其特征在于，
至少一个控制电极包括多晶硅。
19.根据权利要求11到18的半导体电路布置，
其特征在于，
所述半导体电路布置具有至少两个控制电路的分离元件。
20.根据权利要求11到19的半导体电路布置，
其特征在于，
所述半导体电路布置具有至少两个控制电路的高频晶体管。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19957533A DE19957533A1 (de) | 1999-11-30 | 1999-11-30 | Halbleiterschaltungsanordnung und Verfahren zur Herstellung |
| DE19957533.9 | 1999-11-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1402881A true CN1402881A (zh) | 2003-03-12 |
| CN1200462C CN1200462C (zh) | 2005-05-04 |
Family
ID=7930817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008163898A Expired - Fee Related CN1200462C (zh) | 1999-11-30 | 2000-11-30 | 半导体电路装置及其生产方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20030164523A1 (zh) |
| EP (1) | EP1234337B1 (zh) |
| JP (1) | JP2003515948A (zh) |
| CN (1) | CN1200462C (zh) |
| DE (2) | DE19957533A1 (zh) |
| TW (1) | TW494539B (zh) |
| WO (1) | WO2001041194A2 (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105157170A (zh) * | 2015-08-31 | 2015-12-16 | 青岛海尔空调器有限总公司 | 变频空调控制方法 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4836427B2 (ja) * | 2004-09-28 | 2011-12-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
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| JPS5870572A (ja) * | 1981-10-23 | 1983-04-27 | Hitachi Ltd | 半導体装置とその製造法 |
| US4753897A (en) * | 1986-03-14 | 1988-06-28 | Motorola Inc. | Method for providing contact separation in silicided devices using false gate |
| JPH0555251A (ja) * | 1991-08-23 | 1993-03-05 | Nec Corp | Ｍｏｓトランジスタ |
| GB9201004D0 (en) * | 1992-01-17 | 1992-03-11 | Philips Electronic Associated | A semiconductor device comprising an insulated gate field effect device |
| JPH07142589A (ja) * | 1993-11-22 | 1995-06-02 | Nec Corp | 半導体集積回路装置およびその製造方法 |
| JPH087834A (ja) * | 1994-06-24 | 1996-01-12 | New Japan Radio Co Ltd | 光源用放電管 |
| DE19510777C1 (de) * | 1995-03-24 | 1996-06-05 | Itt Ind Gmbh Deutsche | Verfahren zum Herstellen einer CMOS-Struktur mit ESD-Schutz |
| KR100206878B1 (ko) * | 1995-12-29 | 1999-07-01 | 구본준 | 반도체소자 제조방법 |
| JPH10125913A (ja) * | 1996-10-23 | 1998-05-15 | Sony Corp | 半導体装置および半導体装置の製造方法 |
| JPH10189483A (ja) * | 1996-12-26 | 1998-07-21 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置 |
| JP3379376B2 (ja) * | 1997-03-14 | 2003-02-24 | 松下電器産業株式会社 | 電界効果トランジスタおよびそれを用いた電力増幅器 |
| TW359886B (en) * | 1997-09-02 | 1999-06-01 | United Microelectronics Corp | Electrostatic discharge protection device and production process therefor |
| US5910673A (en) * | 1997-12-04 | 1999-06-08 | Sharp Microelectronics Technology, Inc. | Locos MOS device for ESD protection |
| KR100263480B1 (ko) * | 1998-01-13 | 2000-09-01 | 김영환 | 이에스디 보호회로 및 그 제조방법 |
| US5920774A (en) * | 1998-02-17 | 1999-07-06 | Texas Instruments - Acer Incorporate | Method to fabricate short-channel MOSFETS with an improvement in ESD resistance |
| US6025267A (en) * | 1998-07-15 | 2000-02-15 | Chartered Semiconductor Manufacturing, Ltd. | Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices |
| EP1011137A1 (en) * | 1998-12-16 | 2000-06-21 | STMicroelectronics S.r.l. | Method for integrating resistors and ESD self-protected transistors with memory matrix |
-
1999
- 1999-11-30 DE DE19957533A patent/DE19957533A1/de not_active Withdrawn
-
2000
- 2000-11-30 DE DE50015714T patent/DE50015714D1/de not_active Expired - Lifetime
- 2000-11-30 EP EP00993290A patent/EP1234337B1/de not_active Expired - Lifetime
- 2000-11-30 US US10/148,240 patent/US20030164523A1/en not_active Abandoned
- 2000-11-30 CN CNB008163898A patent/CN1200462C/zh not_active Expired - Fee Related
- 2000-11-30 WO PCT/EP2000/012050 patent/WO2001041194A2/de active Application Filing
- 2000-11-30 JP JP2001542369A patent/JP2003515948A/ja not_active Abandoned
- 2000-12-22 TW TW089125316A patent/TW494539B/zh active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105157170A (zh) * | 2015-08-31 | 2015-12-16 | 青岛海尔空调器有限总公司 | 变频空调控制方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE50015714D1 (de) | 2009-09-24 |
| US20030164523A1 (en) | 2003-09-04 |
| TW494539B (en) | 2002-07-11 |
| WO2001041194A2 (de) | 2001-06-07 |
| EP1234337B1 (de) | 2009-08-12 |
| DE19957533A1 (de) | 2001-06-07 |
| JP2003515948A (ja) | 2003-05-07 |
| WO2001041194A3 (de) | 2001-12-06 |
| EP1234337A2 (de) | 2002-08-28 |
| CN1200462C (zh) | 2005-05-04 |
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