CN1323446A - Low temperature formation of backside ohmic contacts of vertical devices - Google Patents
Low temperature formation of backside ohmic contacts of vertical devices Download PDFInfo
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- CN1323446A CN1323446A CN99812021A CN99812021A CN1323446A CN 1323446 A CN1323446 A CN 1323446A CN 99812021 A CN99812021 A CN 99812021A CN 99812021 A CN99812021 A CN 99812021A CN 1323446 A CN1323446 A CN 1323446A
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- 230000015572 biosynthetic process Effects 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 112
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims description 92
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 70
- 239000002019 doping agent Substances 0.000 claims description 58
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 51
- 238000000137 annealing Methods 0.000 claims description 46
- 238000002347 injection Methods 0.000 claims description 29
- 239000007924 injection Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- 239000004411 aluminium Substances 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- 229910002601 GaN Inorganic materials 0.000 claims description 13
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052733 gallium Inorganic materials 0.000 claims description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 150000002739 metals Chemical class 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims 2
- 229910001195 gallium oxide Inorganic materials 0.000 claims 2
- 229910003437 indium oxide Inorganic materials 0.000 claims 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 2
- 230000008021 deposition Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000000203 mixture Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000002156 mixing Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- -1 nitrogen ions Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention comprises a method for forming a metal-semiconductor ohmic contact (18) for use in a semiconductor device (10) having a plurality of epitaxial layers (14a-c) wherein the ohmic contact (18) is preferably formed after deposition of the epitaxial layers (14a-c). The invention also comprises a semiconductor device comprising a plurality of epitaxial layers and an ohmic contact.
Description
Invention field
The present invention relates to a kind of ohm contact that is used for semi-conducting material.Particularly, the present invention relates to the method for the ohm contact in a kind of device that is formed for comprising multiple semi-conducting material.
Background of invention
In microelectronic, circuit is made by the semiconductor device that is linked in sequence.Generally speaking, semiconductor device moves by means of the electric current in the particular electrical circuit, and is used to control this electric current to finish concrete task.In order in circuit, to connect semiconductor device, be necessary for semiconductor device and make suitable contact.Owing to have high conductivity and other chemical characteristic, metal is a material of making the most effective and most convenient of contact in this type of device.
Hard contact between semiconductor device and the circuit should be the interference minimum to device or circuit operation, perhaps preferably, not interferes.And, hard contact must with by this hard contact semi-conducting material that make or that this hard contact links to each other compatibility physically and chemically.Contact types with these desirable characteristics is well-known " ohm contact ".
Ohm contact is normally defined has the metal-semiconductor contact of comparing negligible contact resistance with semi-conductive volume resistance or diffusion resistance, sees Sze, Physics ofSemiconductor Devices, second edition, 1981, the 304 pages.Further narration in this article, suitable ohm contact can significantly not change the performance of the device that ohm contact therewith links to each other, and this ohm contact can provide any required electric current, and its voltage drop is compared quite little with the voltage drop of device active region.
Ohm contact and manufacture method thereof are well-known in the art.For example, people's such as Glass United States Patent (USP) 5409859 and 5323022 (" Glass patent ") is discussed a kind of ohm contact structure that is formed by platinum and p type carborundum and the method for making this ohm configuration, and the full content of these patents is hereby incorporated by reference.Although ohm contact and manufacture method thereof are well-known, even the correct application of method that known production ohm contact especially adopts silicon carbide substrate to produce ohm contact also is difficult to carry out.
The problem relevant with forming ohm contact very more than and also increase gradually.Because of the low semi-conductive limited conductance that causes of hole concentration or electron concentration can hinder or even stops the formation of ohm contact.Equally, relatively poor hole flow or electronics are mobile in the semiconductor can hinder or even stop the formation of ohm contact.As what discuss in the Glass patent, the work function missionary society between contact metal and the semiconductor produces final (non-ohm) electric current with correction and the potential barrier that applies the contact of voltage relationship of forming.Even very different electronics-hole concentrations is arranged between the semi-conducting material of two kinds of identical tight contacts, also there is potential barrier (inner potential energy), thereby forms the rectification contact but not ohm contact.In the Glass patent, relate to these problems by between p type SiC substrate and contact metal, inserting the SiC layer that contains different p type dopants.
When being formed for the ohm contact of gallium indium based semiconductor device of new generation, run into more difficult problem.Need the correctly fusion on its interface of semiconductor and contact metal at formation ohm contact between semiconductor and the metal.As everyone knows, to increase hole/electron concentration on the interface of ohmic contact metal selectively be a kind of effective means that the contact technology that forms ohm contact strengthens that is used in being deposited with.This technology is generally injected by ion and is realized that the ion injection is considered to a kind of and carries out selective technology of mixing up at silicon and carborundum.Yet under the situation of carborundum, ion injects and carries out under high temperature (generally greater than 600 ℃) usually, so that make the infringement minimum that the carborundum lattice is caused.Often require in the silicon overvoltage and surpassing " activation " injected under 1600 ℃ the annealing temperature ion to reach required high carrier concentration.The equipment that is used for this ion implantation technique is specialty and expensive equipment.
The high temperature ion inject and subsequent anneal after, contact metal deposit and annealing on through the surface of the substrate that injects above under 900 ℃ the temperature.This kind forms the contact on the semiconductor device that contains gallium nitride or InGaN method is impracticable, because these compounds at high temperature decompose.
The theoretical answer of a head it off is to finish the necessary rapid wear epitaxial loayer of semiconductor device (as gallium nitride layer) in growth and form ohm contact before on substrate.Yet this kind approach is undesirable, because it is unwanted impurity that contact metal is inserted in the epitaxial growth system.By disturb lattice growth, mix up, reaction speed or all of these factors taken together, foreign metal can influence epitaxial growth.In addition, metal impurities can make the optics and the electrical characteristic variation of epitaxial loayer.
Similarly, many semiconductor device, for example metal-oxide semiconductor fieldeffect transistor (" MOSFET ") needs conductor oxidate (as silicon dioxide) layer.The high temperature relevant with the annealing process of conventional ion injection technique and infusion or contact metal produces heavily stressed on oxide skin(coating), and this stress can damage oxide skin(coating), semiconductor-oxide interface and device itself.Scheme as an alternative, it is unpractical forming ohm contact before producing oxide skin(coating), because be used to form the oxidation environment of oxide skin(coating) ohm contact is had adverse effect.
Therefore, need a kind of economical and practical method, do not have above-mentioned manufacturing issue to be formed for the ohm contact that links to each other with semiconductor device.Also need a kind of comprise ohm contact and lower-cost semiconductor device.
Goal of the invention and general introduction
An object of the present invention is to provide a kind of semiconductor device that comprises ohm contact.
Another object of the present invention provides a kind of semiconductor device that comprises silicon nitride and ohm contact.
A further object of the present invention provides a kind of semiconductor device that comprises low manufacturing cost ohm contact.
Another purpose of the present invention provides the method that a kind of formation comprises the semiconductor device of ohm contact.
For realizing these purposes, the invention provides a kind of method that is formed for the metal-semiconductor ohm contact in the semiconductor device.This method comprises the dopant material through selecting is injected in the surface of the semiconductor chip with initial conduction type.The dopant that is injected into provides the conduction type identical with semiconductor chip.After dopant injected, to carry out first annealing at a certain temperature through the semiconductor chip that injects, annealing time was enough to activate the dopant atom that is injected into and increases efficient carrier concentration.After first annealing, depositing metal on the injection surface of semi-conducting material.Subsequently, carry out second annealing to described metal with through the semi-conducting material that injects.Second annealing temperature is lower than the temperature when formed any epitaxial loayer takes place significantly to degrade on the substrate, but the temperature when being high enough between through the semi-conducting material that injects and depositing metal, form ohm contact.
For realizing these purposes, the present invention also provides a kind of semiconductor device that comprises semiconductor chip, and this semiconductor chip has first surface, second surface and first conduction type.This device also is included at least one epitaxial loayer of growing or forming on the first surface of semiconductor chip.Further determine semiconductor chip: having carrier concentration in substrate increases the zone, and this zone extends to first surface from second surface (with the epitaxial loayer opposite surfaces).This device is included in metals deposited layer on the second surface of substrate again, and the interface that increases the zone in metal and carrier concentration forms ohm contact.
Accompanying drawing below in conjunction with exemplary embodiments is shown describes the present invention, and is easier to understand aforesaid and other purpose, benefit and characteristics and the implementation thereof of the present invention in view of the above.
The accompanying drawing summary
Fig. 1 is the cross sectional representation of semiconductor device according to the invention.
Fig. 2 is the cross sectional representation that applied in the method according to the invention alloy injects.
Detailed Description Of The Invention
The present invention is a kind of semiconductor device and a kind of method that forms ohm contact that comprises ohm contact.
For the professional of the semiconductor device of being familiar with wide band gap semiconducter such as carborundum and forming thus, easy to understand the present invention is the most effective for utilizing n type or p type carborundum (" SiC ") making ohm contact and semiconductor device.Therefore, for ease of explaining, below will carry out based on the embodiment of the invention of using SiC the description of the present invention and example.Yet this area professional is easy to recognize that the present invention also can use other semi-conducting material easily, as silicon, gallium nitride, aluminium gallium nitride alloy and InGaN.Aluminium gallium nitride alloy as used herein and InGaN comprise the compound that the mole percent of aluminium plus gallium wherein or indium and gallium equals 1.
Of the present invention one main aspect, the present invention is the semiconductor device that comprises semiconductor chip, this substrate has the dopant and the initial conduction type of initial concentration.Semiconductor chip can be n type or p type.This device comprises that also at least one is positioned at the epitaxial loayer of a near surface of semiconductor chip.
Described semiconductor device is characterised in that semiconductor chip increases the zone by carrier concentration and determines that this zone extends to the surface adjacent with epitaxial loayer from substrate with the epitaxial loayer opposite surfaces always.Metal level increases deposit on the zone in the carrier concentration of substrate, thereby forms ohm contact on the interface of metal and substrate.
Referring now to Fig. 1, the schematic diagram of semiconductor device according to the invention 10 is described.Device 10 comprises semiconductor chip 12, for ease of explaining that substrate 12 can be thought SiC.Yet should be appreciated that, can be used as substrate in the present invention's practice such as other semi-conducting material of silicon.SiC substrate 12 can be p type or n type.
Adjacent with SiC substrate 12 is to finish the necessary auxiliary element 14 of semiconductor device.For example, with reference to Fig. 1, semiconductor device can be light emitting diode (" LED "), and this LED has order epitaxial loayer 14a, 14b and the 14c of p type and n N-type semiconductor N material.In a preferred embodiment, the present invention is the vertical semiconductor device, for example is to comprise several LED, metal-oxide semiconductor fieldeffect transistor (" MOSFET "), laser or Schottky rectifiers that are positioned near the epitaxial loayer of semiconductor chip.To discuss in the back, device according to the present invention is particularly useful for comprising the vertical semiconductor device of the material with low melting point or low decomposition temperature.This kind material comprises gallium nitride, InGaN and aluminium gallium nitride alloy.
The feature of described device is that also having carrier concentration on the back side of semiconductor chip increases zone 16.In other words, under the situation of SiC, be higher than carrier concentration in the substrate other parts near the carrier concentration with the epitaxial loayer opposite surfaces of semiconductor chip.
The border that carrier concentration increases zone 16 dots, and makes with dashed lines show that when substrate 12 variations suddenly carrier concentration does not have obvious limit herein.Carrier concentration equals initial carrier concentration along with to the increase of substrate back distance and reduce up to carrier concentration.Just as will be discussed, by using the room-temperature ion injection technique of general relevant with n N-type semiconductor N material dopant, form carrier concentration and increase the zone with the p type.
As shown in Figure 1, the preferred embodiment of described device comprises mixing up the n of nitrogen type SiC substrate.Should be appreciated that,, also can together use the n type SiC that forms by other n type dopant with various p type SiC according to the present invention.SiC substrate 12 preferably from the low concentration to the high concentration ground mix up and initial carrier concentration about 1 * 10
15-1 * 10
19Cm
-3Between.Term " low concentration " and " high concentration " are coarse, and deliberately to adopt it be in order to show that initial carrier concentration can have very big variation.Although initial carrier concentration can great changes have taken place, test shows to be carried out from what be initially intermediate concentration providing optimal results to mixing up of high concentration to substrate.By with epitaxial loayer 14 opposite surfaces on ion inject dopant material (as nitrogen) through selecting, produce its carrier concentration zone 16 higher than substrate 12 other parts.Preferably, be infused on a kind of like this degree at the ion that produces carrier concentration on the substrate back and increase zone 16 and carry out, make this zone 16 have about 1 * 10
18-1 * 10
20Cm
-3Carrier concentration and always than initial carrier concentration height.
This area professional can recognize that above-mentioned carrier concentration increases the zone and also can form in the substrate growth course.Yet general and that growing method the is relevant difficulty with other of the difficulty relevant with the variable feeding speed of required dopant makes that this kind method is unrealistic.
The preferred n type dopant that is used to form carrier concentration increase zone 16 is nitrogen, arsenic and phosphorus.The preferred p type dopant that is used to form carrier concentration increase zone 16 is aluminium, boron and gallium.
Although the applicant does not wish to be subjected to concrete theoretical constraint, evidence shows that carrier concentration increases zone 16 and allows to produce the hard contact with ohm property.In a preferred embodiment, increase in the carrier concentration of SiC substrate that deposit has fusing point, steam pressure and physics and the contact metal 18 chemical property, through selecting of the entire semiconductor device of being applicable on regional 16 surfaces, thereby between metal and substrate, form interface 20.Preferred metals is drawn together nickel, palladium, platinum, aluminium and titanium, wherein nickel most preferably.The device that comprises metal and substrate is then annealed at a certain temperature, this temperature when avoiding the especially any epitaxial loayer of device caused damage temperature but be higher than temperature when on the interface of metal and substrate, being enough to form ohm contact.
And as if although the applicant does not wish to be subjected to the constraint of any concrete theory, producing carrier concentration increase zone is useful with the acceptor (receptor) as contact metal.Thereby, in another embodiment, the present invention includes the method that is formed for the ohm contact in the above-mentioned semiconductor device.
On wideer meaning, the present invention is a kind of method that is formed for the metal-semiconductor contact in the semiconductor device.This method comprises the dopant material that injects through selecting in the semiconductor chip with first conduction type, the dopant that wherein is injected into provides the conduction type identical with substrate.For ease of discussing, suppose that semiconductor chip is that SiC substrate and dopant deposition of materials are in the surface of SiC substrate.Yet,, recognize that easily the present invention can use other semi-conducting material easily for this area professional.After the dopant material that injects through selecting, carry out annealing steps.In this annealing steps, to anneal at a certain temperature the sufficiently long time through the SiC substrate that injects, the dopant atom that activation is injected into is to increase the carrier concentration of the dopant atom that is injected in the SiC substrate effectively.Contact metal is deposit on the injection surface of SiC substrate then.Then the contact metal of deposit and the injection surface of SiC substrate are annealed.Temperature when this second annealing temperature is lower than any epitaxial loayer experience that forms and significantly degrades on substrate also is higher than temperature when being enough to form ohm contact between through the SiC substrate that injects and depositing metal.
In a preferred embodiment, semiconductor chip can comprise the n type or the p type substrate of the initial dopant with low concentration, intermediate concentration or high concentration.For example, under the situation of n type SiC substrate, the SiC substrate can have from about 1 * 10
15Cm
-3(low concentration mixes up) is to 1 * 10
19Cm
-3Initial dopant concentration between (high concentration is mixed up).Term " low concentration ", " intermediate concentration " or " high concentration " are coarse, and the initial dopant concentration that is used for being illustrated in substrate material is transformable.Test shows that the process intermediate concentration can reach optimum efficiency of the present invention to the substrate that mixes up of high concentration.
Then, semi-conducting material is injected in the dopant material of selection, and is annealed.Preferably, dopant injects and at room temperature to carry out and subsequent annealing is carried out under the temperature between 800 ℃-1300 ℃.Usually the dopant relevant with the substrate conduction type can be used as the dopant that uses in implantation step.For example, when mixing up at first when the n of nitrogen type SiC is arranged as substrate, nitrogen can be used as the dopant of injection.Equally, when mixing up at first when the p of aluminium type SiC is arranged as substrate, aluminium can be used as the dopant of injection.Other possible n type dopant is arsenic and phosphorus.And boron and gallium can be used as alternative p type dopant.
For this area professional, recognize that easily the injection of dopant material can at high temperature be finished.In fact, under the SiC situation, for the infringement that reduces the SiC lattice structure is caused, it generally is preferred that high temperature injects.Yet under the SiC situation, the high temperature ion injects restriction commercial Application of the present invention.The ion implantation device that can heat the SiC substrate in injection process is unconventional, expensive and is used to research and develop purpose, and can not carry out cheaply, large batch of application.Moreover when the SiC substrate was heated to high temperature, the speed of their heating and cooling should be as the criterion not produce fragment, thereby slows down production technology.
Therefore, the room temperature injection is the preferred method for implanting that uses in the present invention.Have been found that after the room-temperature ion of dopant injects, can reach 1300 ℃ and can hold the annealing steps that carries out in the simple draft furnace of more than 100 substrate wafer and can obtain satisfied result and increase output greatly.
Preferably carry out the room temperature of dopant and inject, so that produce carrier concentration increase zone at the injection near surface of semiconductor chip.Fig. 2 is the schematic diagram according to injection technology of the present invention.In this example, have about 1 * 10
18Cm
-3The n type SiC substrate 22 of initial dopant concentration is with 1 * 10
13Cm
-2Or bigger dosage injects with Nitrogen Atom or diatomic nitrogen 24 under the 10-60keV energy.In some cases, can be used for the more slow carrier concentration profile that changes more than a kind of injection energy.Injection technology is in the zone 26 that the injection near surface of SiC substrate produces about 1000 dusts of the degree of depth, and zone 26 has about 1 * 10
19-1 * 10
20Cm
-3Whole chemical dopant concentration and the dopant concentration of injection along with reducing to the increase of injecting surface distance.The dopant concentration that carrier concentration increases regional 26 outsides keeps identical with initial dopant concentration substantially.The border that carrier concentration increases zone 26 dots, and shows that the carrier concentration variation between zone 26 and substrate other parts is slow and unconspicuous.This area the professional know, can change injection energy or dosage easily to reach the required concentration and the degree of depth.
As mentioned above, must be to annealing through the substrate that injects.Require annealing to be because some dopant ions that are injected into are not " activity " when just finishing injection.Term " activity " is used to describe the ion pair that is injected into and injects the validity that total carrier concentration of substrate exerts an influence.
In injection process, the lattice of SiC substrate generally can be subjected to the impact of dopant ion.These ions break the lattice at place, their places.This kind impact can not make the dopant ion be inserted in good condition in the existing lattice.The initial alignment of many dopant ions prevents that this ion from becoming " activity " composition in the lattice, and itself is also damaged this composition by impact.Can provide a kind of mechanism to anneal through the SiC substrate that injects (i.e. heating), by this mechanism, the damage that the ion that is injected into and the lattice of substrate rearrange and recover to take place in the dopant injection process in more orderly mode.
Injection technology is as described below, only uses integer for ease of explaining.Have in the n type SiC substrate that initial concentration is an x nitrogen-atoms if 100 nitrogen ions are injected into, substrate just only has and the relevant characteristic of substrate that contains " x+10 " individual nitrogen ion when just having finished injection.Yet if then substrate annealing and the ion that allows to be injected into are located in lattice, substrate has and the relevant characteristic of substrate that comprises " x+90 " individual nitrogen ion.
Test shows that the SiC substrate that between about 1000 ℃-1300 ℃ temperature the process room temperature is injected was annealed about 2 hours or the shorter time can obtain satisfied result.For realizing that the dosage that injects is activated more completely, can easily adjust annealing temperature and time.
The semiconductor device that comprises the substrate that above-mentioned process is injected has at least one epitaxial loayer.Can use the known method grown epitaxial layer of any this area professional.In a preferred embodiment of the invention, deposit epitaxial loayer before substrate being carried out the dopant injection.Yet the device of required epitaxial loayer or follow-up making can be made by the material (as gallium nitride or silica) that can not bear the substrate high annealing that process is injected, and the device of perhaps required epitaxial loayer or follow-up making can comprise this kind material.In this case, epitaxial loayer can form after dopant injects.
Be injected into and set up after the dopant concentration of abundant annealing increases the zone and form any epitaxial loayer on substrate at semiconductor chip, the metal function that is used to form ohm contact through selecting increases region surface to the carrier concentration of substrate.This metal can be any metal that generally is used to form electric contact, and these metals have suitable high-melting-point and steam pressure and with substrate material disadvantageous interaction do not take place.Preferred metals is drawn together nickel, palladium, platinum, titanium and aluminium, wherein nickel most preferably.
Preferably, contact metal is deposited on the substrate surface, forms the right thick layer of 300 Izods.After deposit, carry out the annealing second time.Yet this annealing is not high temperature and annealing for a long time.The temperature of this annealing is preferably less than about 1000 ℃ and most preferably less than about 800 ℃, and this annealing time is preferably no longer than 20 minutes and most preferably no longer than 5 minutes.These temperature and time cycles are enough low to avoid damaging on-chip any epitaxial loayer.The annealing that contact metal on the semiconductor chip is carried out produces ohm contact on the interface of metal and substrate.
In the present invention more specifically among the embodiment, by using n type SiC substrate with 50keV energy and 3 * 10
14Cm
-2The Nitrogen Atom of dosage is carried out the first time and is injected subsequently with 25keV and 5 * 10
14Cm
-2Carry out the second time and inject, and produce according to metal semiconductor of the present invention.After injecting, in stove, in argon gas atmosphere, under 1300 ℃ of temperature, activate annealing 60-90 minute.Then, injecting deposit contact metal nickel on the surface, thickness is 2500 dusts.In hydrogen, under 800 ℃ of temperature, carry out contact annealing 2 minutes then.Resulting ohm contact has satisfied ohm performance.
This area professional it should be understood that also can carry out contact annealing in situ when epitaxial growth.
The present invention provides substantial benefit for following device, and these devices are: such as the vertical devices of photodetector, light emitting diode (LED), laser; Power supply apparatus such as metal-oxide semiconductor fieldeffect transistor (MOSFET), insulated door bipolar transistor (IGBT), pn knot and Schottky rectifier; And such as the microwave device of SIT (static induction transistor).Under the situation of detector, LED and laser, epitaxially grown gallium nitride and gallium indium nitride layer are not annealed under the temperature of these layers of meeting grievous injury.Under the situation of InGaN, along with the increase of indium composition in the alloy, at high temperature the time of Ting Liuing becomes more dangerous.Reduce the b contact annealing temperature, also be reduced in the potential possibility of indium in the distortion heteroepitaxial film of growing on the SiC substrate or pyrolysis of gallium composition or decomposition.
Under the situation of power supply apparatus, the homoepitaxy film of growth SiC and heat growth or hot regrowth on substrate (reoxidize or anneal), oxide plays whole effect in device performance and lower annealing temperature is good.The back metal contact can not experience oxidation environment, this oxidation environment SiC-silicon dioxide interface that is used for growing, and therefore, backside ohmic contacts must carry out deposit and annealing afterwards silicon dioxide growth (reoxidizing or regrowth).Unfortunately, in the prior art, annealing temperature (more typically being 900-1050 ℃) the follow-up contact that is used for forming substrate back, that be not less than 850 ℃ can not produce defective because of thermal expansion speed matches at SiC-silicon dioxide interface.This is especially unfavorable for MOSFET and IGBT.
The SiC technology is in its initial stage, and the device of many proposals and material structure also need check or exploitation.Further exploitation for this technology can cause annealing temperature even lower, finally causes deposit formation ohm contact (promptly need not anneal) between metal and semiconductor.
For making the reader just can realize the present invention, describe the present invention in detail in conjunction with certain preferred embodiment without undue experimentation.Yet, only it will be readily appreciated by those skilled in the art that otherwise depart from the scope of the present invention and spirit, can be to a certain extent make and changing or change many compositions of the present invention and parameter.And exercise question or title etc. is used to deepen the understanding of reader to this paper, should not be considered as limitation of the scope of the invention.Have only following claim and its reasonably to extend and the just definite intellectual property of the present invention of equivalent.
Claims (27)
1. method that is formed for the metal-semiconductor ohm contact of semiconductor device may further comprise the steps:
Dopant material through selecting is injected in the first surface of the semiconductor chip with first conduction type, and wherein, the dopant that is injected provides the conduction type identical with semiconductor chip;
The semiconductor chip that is injected into is carried out first annealing at a certain temperature, and annealing time is enough to activate the dopant atom of injection and increases efficient carrier concentration;
Depositing metal on the injection surface of semi-conducting material; And subsequently
Carry out second annealing at a certain temperature to described metal with through the semi-conducting material that injects, annealing temperature is lower than the temperature when formed any epitaxial loayer takes place significantly to degrade on the substrate but is high enough to form ohm contact between through the semi-conducting material that injects and depositing metal.
2. the method for claim 1, wherein at room temperature inject dopant material through selecting.
3. the method for claim 1, wherein semiconductor chip comprises carborundum.
4. method as claimed in claim 3 wherein, is selected from the group that comprises nitrogen, aluminium, arsenic, phosphorus, boron and gallium through the dopant material of selecting.
5. the method for claim 1, wherein under the temperature between about 1000-1300 ℃, implement first annealing.
6. the method for claim 1, wherein described metal is selected from the group that comprises nickel, palladium, platinum, aluminium and titanium.
7. the method for claim 1, wherein be lower than enforcement second annealing under about 850 ℃ temperature.
8. method that is formed for the ohm contact of carborundum in the semiconductor device, comprising following steps:
At room temperature the dopant material through selecting is injected in the silicon carbide substrate surface, on silicon carbide substrate, forms the dopant material concentration thus and increase layer;
Silicon carbide substrate after injecting is carried out first annealing;
Silicon carbide substrate with the surface of injecting surface opposite at least one epitaxial loayer of growth;
Deposited metal on the injection surface of silicon carbide substrate; And subsequently
To described metal and the silicon carbide substrate after injecting carry out second annealing at a certain temperature, the temperature when annealing temperature is lower than described epitaxial loayer and takes place significantly to degrade but be high enough between through the carborundum that injects and depositing metal, form ohm contact.
9. method as claimed in claim 8 wherein, is being implemented before first annealing carrying out through the silicon carbide substrate that injects in the step of silicon carbide substrate growing epitaxial layers.
10. method as claimed in claim 8 wherein, is being implemented after first annealing carrying out through the silicon carbide substrate that injects in the step of silicon carbide substrate growing epitaxial layers.
11. method as claimed in claim 8 wherein, is selected from the group that comprises nitrogen, aluminium, arsenic, phosphorus, boron and gallium through the dopant material of selecting.
12. method as claimed in claim 8 wherein, is approximately being implemented under the temperature between 1000-1300 ℃ first annealing of carrying out through the silicon carbide substrate that injects.
13. method as claimed in claim 8, wherein, described metal is selected from the group that comprises nickel, palladium, platinum, aluminium and titanium.
14. method as claimed in claim 8, wherein, the annealing steps that silicon carbide substrate and described depositing metal are carried out is implemented being lower than under about 850 ℃ temperature.
15. a semiconductor device, comprising:
Semiconductor chip with first surface, second surface and first conduction type;
At least one epitaxial loayer on the described first surface of described semiconductor chip;
Carrier concentration in described semiconductor chip increases the zone, and this zone extends to described first surface from the described second surface of described semi-conducting material; And
Metals deposited layer on the described second surface of described semiconductor chip, it increases the interface formation ohm contact in zone in described metal and described carrier concentration.
16. semiconductor device as claimed in claim 15, wherein, described semiconductor chip is a carborundum.
17. semiconductor device as claimed in claim 15, wherein, the dopant material of injection is selected from the group that comprises nitrogen, aluminium, arsenic, phosphorus, boron and gallium.
18. semiconductor device as claimed in claim 16, wherein, the initial carrier concentration of carborundum is about 1 * 10
15-1 * 10
19Cm
-3Between.
19. semiconductor device as claimed in claim 18, wherein, the carrier concentration in the carrier concentration increase zone is about 1 * 10
18-1 * 10
20Cm
-3Between, and greater than the initial carrier concentration in the carborundum.
20. semiconductor device as claimed in claim 15, wherein, described epitaxial loayer is selected from the group that comprises gallium nitride, aluminium gallium nitride alloy, InGaN and Si oxide, gallium oxide, aluminum oxide and indium oxide.
21. semiconductor device as claimed in claim 16, wherein, described metal is selected from the group that comprises nickel, palladium, platinum, aluminium and titanium.
22. a semiconductor device, comprising:
Semiconductor chip with first surface, second surface, it has the dopant of initial concentration, and is endowed the initial conduction type;
At least one epitaxial loayer on the described first surface of silicon carbide substrate;
Carrier concentration in described silicon carbide substrate increases the zone, this zone extends to described first surface from the described second surface of described silicon carbide substrate, and described dopant material area is characterised in that dopant concentration reduces to described first surface gradually from described second surface; And
Nickel ohm contact on the described second surface of described silicon carbide substrate.
23. semiconductor device as claimed in claim 22, wherein, the dopant material of injection is selected from the group that comprises nitrogen, aluminium, arsenic, phosphorus, boron and gallium.
24. semiconductor device as claimed in claim 22, wherein, the initial carrier concentration in the carborundum is about 1 * 10
15-1 * 10
19Cm
-3Between.
25. semiconductor device as claimed in claim 24, wherein, the carrier concentration in the carrier concentration increase zone is about 1 * 10
18-1 * 10
20Cm
-3Between, and greater than the initial carrier concentration in the carborundum.
26. semiconductor device as claimed in claim 22, wherein, described epitaxial loayer is selected from the group that comprises gallium nitride, aluminium gallium nitride alloy, InGaN and Si oxide, gallium oxide, aluminum oxide and indium oxide.
27. semiconductor device as claimed in claim 22, wherein, semiconductor device is a vertical devices.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10054698P | 1998-09-16 | 1998-09-16 | |
| US60/100,546 | 1998-09-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1323446A true CN1323446A (en) | 2001-11-21 |
| CN1178277C CN1178277C (en) | 2004-12-01 |
Family
ID=22280313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB998120219A Expired - Lifetime CN1178277C (en) | 1998-09-16 | 1999-09-16 | Low temperature formation of backside ohmic contacts of vertical devices |
Country Status (9)
| Country | Link |
|---|---|
| EP (1) | EP1125320A1 (en) |
| JP (2) | JP4785249B2 (en) |
| KR (1) | KR100694681B1 (en) |
| CN (1) | CN1178277C (en) |
| AU (1) | AU6391699A (en) |
| CA (1) | CA2343416A1 (en) |
| MX (1) | MXPA01002751A (en) |
| TW (1) | TW449932B (en) |
| WO (1) | WO2000016382A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6803243B2 (en) | 2001-03-15 | 2004-10-12 | Cree, Inc. | Low temperature formation of backside ohmic contacts for vertical devices |
| US6884644B1 (en) | 1998-09-16 | 2005-04-26 | Cree, Inc. | Low temperature formation of backside ohmic contacts for vertical devices |
| US6909119B2 (en) | 2001-03-15 | 2005-06-21 | Cree, Inc. | Low temperature formation of backside ohmic contacts for vertical devices |
| US7138291B2 (en) | 2003-01-30 | 2006-11-21 | Cree, Inc. | Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices |
| US7262434B2 (en) | 2002-03-28 | 2007-08-28 | Rohm Co., Ltd. | Semiconductor device with a silicon carbide substrate and ohmic metal layer |
| US7473929B2 (en) | 2003-07-02 | 2009-01-06 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
| JP2006086361A (en) * | 2004-09-16 | 2006-03-30 | Stanley Electric Co Ltd | Semiconductor light-emitting element and its manufacturing method |
| US8367510B2 (en) * | 2005-09-14 | 2013-02-05 | Central Research Institute Of Electric Power Industry | Process for producing silicon carbide semiconductor device |
| US20100237385A1 (en) * | 2008-06-26 | 2010-09-23 | Sanken Electric Co., Ltd. | Semiconductor device and method of fabricating the same |
| KR101220407B1 (en) | 2010-12-14 | 2013-01-21 | (재)한국나노기술원 | Semiconductor light emitting device |
| JP5811829B2 (en) | 2011-12-22 | 2015-11-11 | 住友電気工業株式会社 | Manufacturing method of semiconductor device |
| JP5742712B2 (en) | 2011-12-29 | 2015-07-01 | 住友電気工業株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP6253133B2 (en) * | 2012-04-27 | 2017-12-27 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| EP2905806B1 (en) | 2013-10-08 | 2016-08-24 | Shindengen Electric Manufacturing Co., Ltd. | Method for manufacturing a silicon carbide semiconductor device. |
| JP7135443B2 (en) * | 2018-05-29 | 2022-09-13 | 富士電機株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5323022A (en) * | 1992-09-10 | 1994-06-21 | North Carolina State University | Platinum ohmic contact to p-type silicon carbide |
| JP3303530B2 (en) * | 1994-06-23 | 2002-07-22 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JPH08139053A (en) * | 1994-11-04 | 1996-05-31 | New Japan Radio Co Ltd | Method of forming electrode for sic |
| JP3333896B2 (en) * | 1995-09-13 | 2002-10-15 | 富士電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| WO1998037584A1 (en) * | 1997-02-20 | 1998-08-27 | The Board Of Trustees Of The University Of Illinois | Solid state power-control device using group iii nitrides |
-
1999
- 1999-09-16 TW TW088116007A patent/TW449932B/en not_active IP Right Cessation
- 1999-09-16 CN CNB998120219A patent/CN1178277C/en not_active Expired - Lifetime
- 1999-09-16 WO PCT/US1999/021475 patent/WO2000016382A1/en not_active Application Discontinuation
- 1999-09-16 EP EP99951484A patent/EP1125320A1/en not_active Ceased
- 1999-09-16 AU AU63916/99A patent/AU6391699A/en not_active Abandoned
- 1999-09-16 CA CA002343416A patent/CA2343416A1/en not_active Abandoned
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- 1999-09-16 MX MXPA01002751A patent/MXPA01002751A/en active IP Right Grant
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Also Published As
| Publication number | Publication date |
|---|---|
| KR20010079759A (en) | 2001-08-22 |
| MXPA01002751A (en) | 2002-04-08 |
| JP2002525849A (en) | 2002-08-13 |
| CN1178277C (en) | 2004-12-01 |
| TW449932B (en) | 2001-08-11 |
| CA2343416A1 (en) | 2000-03-23 |
| WO2000016382A1 (en) | 2000-03-23 |
| KR100694681B1 (en) | 2007-03-13 |
| JP2011151428A (en) | 2011-08-04 |
| JP4785249B2 (en) | 2011-10-05 |
| EP1125320A1 (en) | 2001-08-22 |
| AU6391699A (en) | 2000-04-03 |
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