CN1321382C

CN1321382C - Serial/parallel data converting module and relative computer system

Info

Publication number: CN1321382C
Application number: CNB2004100028747A
Authority: CN
Inventors: 陈仁鹏; 刘万贤
Original assignee: High Tech Computer Corp
Current assignee: HTC Corp
Priority date: 2004-01-20
Filing date: 2004-01-20
Publication date: 2007-06-13
Anticipated expiration: 2024-01-20
Also published as: CN1648887A

Abstract

The present invention relates to a serial/parallel data converting module which comprises a first serial/parallel data converter internally containing one parallel port/one serial port, a second serial/parallel data converter internally containing one parallel port/one serial port and a control unit. The present invention is used for electrically connecting the parallel port of the first serial/parallel data converter with the parallel port of the second serial/parallel data converter or the serial port of the first serial/parallel data converter with the serial port of the second serial/parallel data converter in a selective mode.

Description

Serial and relative computer system

Technical field

The present invention relates to a kind of as UART Universal Asynchronous Receiver Transmitter (universal asynchronousreceiver/transmitter, UART) serial converter, be particularly related to a kind of serial that comprises a plurality of serial converters and a control module, this this serial of control module may command optionally operates on different patterns.

Background technology

Compared to the transmission of running simultaneously (synchronous parallel transmission), it is little that asynchronous serial (asynchronous serial) transmission has a volume, advantages such as cheap and long transmission distance.For instance, UART Universal Asynchronous Receiver Transmitter (universal asynchronous receiver/transmitter, UART) be a kind of include be used for controlling a computing machine (or a processor) and with serial line unit (serial device) that this computing machine (this processor) is connected between a kind of asynchronous serial/parallel data converter of microchip (microchip) of data transmission.More particularly, the function of this computing machine that UART provides is similar in appearance to data terminal equipment (the data terminal equipment such as RS-232, DTE) data exchanging function that is provided, so that should calculate function by as USB (universal serial bus) (universal serialbus, universal serial bus USB) and as the mutual swap data of serial line unit of (modem) such as modulator-demodular units.

See also Fig. 1, Fig. 1 is the functional block diagram of a known UART system 10.UART system 10 comprises one and allows parallel data (parallel data) transmission system bus (system bus) 26 thereon, one is electrically connected on system bus 26 and is used for sending and receiving the processor 20 of a parallel data, one is used for UART 22 that a parallel data and serial datum (serial data) are exchanged, one allows serial data transmission USB (universal serial bus) 28 thereon, and one be electrically connected on USB (universal serial bus) 28 and be used for sending and receiving the serial line unit 24 of serial datum.

UART 22 comprises six eight buffers 12 that are used for storing control and status information (control and statusinformation), one usefulness decides the transfer rate generator (baud rate generator) 16 of the transfer rate of the data that are transmitted in 24 of processor 20 and serial line units, one is electrically connected on the bus interface (bus interface) 14 of system bus 26, and one be electrically connected on serial line unit 24 and be used for receiving and send the transceiver (transceiver) 18 of character frame (frame) type data.Generally speaking, in UART 22, bus interface 14 be with eight parallel pins via the data in the system bus 26 access processors 20, transceiver 18 then is via the data in the USB (universal serial bus) 28 access serial line units 24 with two pins (RxD is used for input, TxD then be used for output).These character picture format data comprise together beginning position (space, logic " 0 ") and a stop bit (mark, logic " 1 "), and these character picture format data also can comprise a parity bit (parity bit) that is used as the bug check sign indicating number in addition.

UART 22 be according to controls stored in the buffer 12 and status information with processor 20 via 26 parallel datas that send concurrently of system bus, convert character picture format data by an additional start bit and a stop bit (or in addition additional parity bit) earlier in the mode of this parallel data, again these character picture format data are sent to serial line unit 24 via USB (universal serial bus) 28 in by turn mode, or with serial line unit 24 via USB (universal serial bus) 28 with by turn character picture format data that mode was sent, by identification (check) back and give up start bit in parity bit in (discard) these character picture format data (if the words that have) and deletion (strip) these character picture format data and the mode of stop bit converts a parallel data earlier to, be sent to processor 20 concurrently via system bus 26 again.

In recent years, polygamy is equipped with the processor of (as two) more than in the computer system, with the processing of expedited data, accordingly, also need be equipped with two UART in this computer system, to carry out the exchanges data between this two processor and other serial line unit.Yet two processors in this computer system only can be electrically connected on this two UART respectively, and carry out exchanges data by this two UART with other serial line unit.

Summary of the invention

Therefore fundamental purpose of the present invention is to provide a kind of serial, and the serial converter that is comprised in it can be controlled by a control module, with to carrying out exchanges data between different processors or between processor and serial line unit.

According to claim of the present invention, the present invention discloses a kind of serial, it comprises first a serial converter that includes a parallel port and a serial port, one includes the second serial converter of a parallel port and a serial port, and a control module, be used for optionally parallel port that parallel port with this first serial converter is electrically connected on this second serial converter maybe the serial port of this first serial converter to be electrically connected on the serial port of this second serial converter.

Thus, once first serial line unit of the serial port that is connected in this first serial converter can with second a serial line unit swap data that is connected in the serial port of this second serial converter, if this control module is electrically connected on the parallel port of this first serial converter the parallel port of this second serial converter, perhaps once the first processor of the parallel port that is connected in this first serial converter can with second a processor swap data that is connected in the parallel port of this second serial converter, if this control module is electrically connected on the serial port of this first serial converter the serial port of this second serial converter.

Because the control module in the serial of the present invention is optionally controlled this first processor, this second processor, this first serial converter, this second serial converter, this first serial line unit, is reached the electric connection mode between this second serial line unit, therefore, serial of the present invention has sizable use elasticity.

The accompanying drawing summary

Fig. 1 is the functional block diagram of a known UART system 10.

Fig. 2 is the functional block diagram of a UART ASIC in the preferred embodiment of the present invention.

Fig. 3 is first constitutional diagram that comprises the computer system of the shown UART ASIC of Fig. 2 in the second embodiment of the present invention.

Fig. 4 is for being shown in second constitutional diagram of the computer system of Fig. 3 in the third embodiment of the present invention.

Fig. 5 is for being shown in the third state figure of the computer system of Fig. 3 in the fourth embodiment of the present invention.

Fig. 6 is the connection status figure of each assembly in the shown computer system of Fig. 5.

Fig. 7 is for being shown in the four condition figure of the computer system of Fig. 3 in the fifth embodiment of the present invention.

Fig. 8 is the constitutional diagram of a computer system in the sixth embodiment of the present invention.

The reference numeral explanation

10 UART systems, 12 buffers

14 bus interface, 16 transfer rate generators

18 transceivers, 20 processors

22 UART modules, 24 serial line units

26 system buss, 28 USB (universal serial bus)

30,90 UART ASIC 32 a UART module

34 the 2nd UART modules, 36,96 control modules

38,42 parallel ports, 40,44 serial ports

50,80 computer systems, 52 first processors

53 first system buss, 54 second processors

55 second system buss, 56 first serial line units

58 second serial line units 82 the 3rd processor

84 four-processor, 98 electric potential transducers

Embodiment

Except mentioned before UART (RS232 is a kind of of UART), the serial converter still comprises I ²C (inter-IC) and USB (IEEE1394) etc.I ²C as its name suggests, is to be connected between two IC, and can by two two-way (send and receive) transmission line (serial data line SDA and serial clock pulse line SCL) with data transmission between this two IC.

Serial of the present invention can comprise at least two identical serial converters, because I ²The principle of conversion such as C and USB serial data and parallel data is the principle similar in appearance to UART conversion serial data and parallel data, so, below sincerely be that example illustrates serial of the present invention with UART.

See also Fig. 2, Fig. 2 is the functional block diagram of a UART module 30 in the preferred embodiment of the present invention, UART 30 can be an Application Specific Integrated Circuit (application specifi cintegrated.circuit, ASIC), that is the assembly that comprised of UART 30 all be to be integrated in this ASIC.UART ASIC30 comprises one the one UART 32, one the 2nd UART 34, and one is used for controlling a UART 32 and reaches as the control module that is connected 36 between the serial line unit of modulator-demodular unit each other or with other parallel device as processor with the 2nd UART 34.The one UART 32 comprises one first parallel port (being electrically connected to the bus interface 14 among the UART 22 as shown in Figure 1), 38 and 1 first serial port (being electrically connected to the transceiver 18 among the UART 22 as shown in Figure 1) 40, and the 2nd UART 34 comprises one second parallel end 42 and 1 second serial port 44.About control module 36 how to control a UART 32 and the 2nd UART 34 each other or with other parallel device and serial line unit between be connected and wait until aftermentioned.

Before sayed it, comprise six eight buffers 12 that are used for storing control and status information in the shown UART 22 of Fig. 1, UART 22 can receive or send data according to control stored in these buffers 12 and status information.These six buffers are respectively: an XMITDT buffer that is used for the eight bit data that stored row will be sent via transceiver 18, one is used for storing the RECVDT buffer of 18 eight bit data of just having received of transceiver, two are used for storage one jointly for the DIVMSB and the DIVLSB buffer of sixteen bit (eight+eight) transfer rate of the usefulness of transfer rate generator 16, one is used for storing the STATUS buffer of the existing operating mode important informations such as (sending or receive data) about UART 22, and one be used for indicating the transmission of UART 22 and receive the CLRINT buffer of whether finishing of data.And preceding four low levels in this STATUS buffer are one to send the XMIT position of (or claiming to be in the state that sends data) character picture format data in order to expression UART 22 (bit 0, LSB), one be used for representing that the DONE_XMIT position (bit2) and that RECV position (bit1), that UART 22 is receiving (or claiming to be in the state that receives data) character picture format data is used for representing that UART 22 has sent these character picture format data that finish is used for representing that UART 22 has received the DONE_RECV position (bit3) of these character picture format data in regular turn.The disclosed serial of the present invention (is example with UART) is exactly by stored control and status information in the buffer that changes a UART 32 and the 2nd UART module, with change a UART 32 with the 2nd UART 34 mutual or and other parallel device and serial line unit between data transmission state.

See also Fig. 2, Fig. 3 is first constitutional diagram that comprises the computer system 50 of UART ASIC 30 in the second embodiment of the present invention.Computer system 50 comprises a first processor 52 in addition, first system bus 53, one second processor 54, that first processor 52 is electrically connected on UART ASIC 30 is electrically connected on second system bus 55, one first serial line unit 56, and one second serial line unit 58 of UART ASIC 30 with second processor 54.In a second embodiment, the switch SW in the control module 36 ₁, SW ₂, SW ₃, SW ₄, SW ₅, SW ₆, and SW ₇Be respectively with node a and c, a and e, b and d ₂, b and d ₂, A and C, B and E and c and f link together.That is to say that first processor 52 can be via UART ASIC 30 simultaneously and first serial line unit 56 and second serial line unit, 58 swap datas, and second processor 54 is to be in idle state (idle).When first processor 52 will be sent to first serial line unit 56 and second serial line unit 58 with an eight bit data, lowest order (XMIT position) in the UART 32 of UART ASIC 30 and six buffers of the 2nd UART 34 in this STATUS buffer can be configured to " 1 ", certainly, this eight bit data is still needed by an additional start bit and a stop bit with after converting character picture format data to, can be transferred into first serial line unit 56 and second serial line unit 58; Otherwise when first processor 52 will receive the character picture format data that first serial line unit 56 and second serial line unit 58 transmitted, the RECV position (bit1) in this STATUS buffer can be configured to " 1 ".

In computer system 50, the first processor 52 and second processor 54 also can be respectively and first serial line unit 56 and second serial line unit, 58 swap datas.See also Fig. 4, Fig. 4 is second constitutional diagram of computer system 50 in the third embodiment of the present invention.In Fig. 4, the switch SW in the control module 36 ₁, SW ₂, SW ₃, SW ₄, SW ₅, SW ₆, and SW ₇Be respectively with node a and c, a and d ₁, b and d ₂, b and e, A and C, B and E and c and f link together.That is to say, can a UART 32 and first serial line unit, 56 swap datas except first processor 52 via UART ASIC 30, second processor 54 also can be via the 2nd UART 34 and second serial line unit, 58 swap datas of UART ASIC 30.By setting a corresponding UART 32 and the STATUS buffer among the 2nd UART 34 respectively, the first processor 52 and second processor 54 can individually carry out the reception and the transmission of data respectively with first serial line unit 56 and second serial line unit 58.

In the above-mentioned computer system 50, processor (first processor 52 and second processor 54) is and serial line unit (first serial line unit 56 and second serial line unit 58) swap data, yet, also essential sometimes swap data between the processor.See also Fig. 5, Fig. 5 is the third state figure of computer system 50 in the fourth embodiment of the present invention.In the shown computer system 50 of Fig. 5, the switch SW in the control module 36 ₁, SW ₂, SW ₃, SW ₄, SW ₅, SW ₆, and SW ₇Be respectively with node a and c, a and d ₁, b and d ₂, b and e, A and D, B and D and c and f link together.Thus, first processor 52 can be via a UART 32 and the 2nd UART 34 and second processor, 54 swap datas of UART ASIC 30.When first processor 52 will be sent to second processor 54 with an eight bit data, the lowest order (XMIT position) of this STATUS buffer can be configured in six buffers of the one UART 32 " 1 ", with with this eight bit data converted character picture format data send, and the RECV position (bit1) in this STATUS buffer can be configured in six buffers of the 2nd UART 34 " 1 ", to receive the character picture format data that transmitted by a UART 32 (in the equivalence, also being about among the UART 32 to be connected) in order to hold in order to the Rx that receives data among the Tx end that sends data and the 2nd UART 34; Otherwise, when second processor 54 will be sent to first processor 52 with an eight bit data, the lowest order (XMIT position) of this STATUS buffer can be configured in six buffers of the 2nd UART 34 " 1 ", with with this eight bit data converted character picture format data send, and the RECV position (bit 1) in this STATUS buffer can be configured in six buffers of a UART 32 " 1 ", to receive the character picture format data that transmitted by the 2nd UART 34.

See also Fig. 6, Fig. 6 is among the third state figure of computer system 50 shown among Fig. 5, the connection status figure of first processor 52, second processor 54, a UART 32 and the 2nd UART 34.As shown in Figure 6, the one UART 32 is the Be Controlled TX, the RX that are connected to the 2nd UART 34, CTS, RTS, DSR, and DTR, that is to say, when first processor 52 will be sent to second processor 54 with an eight bit data, a UART 32 controlledly played the part of a transmitter and the 2nd UART 34 is the controlled receivers of playing the part of; When second processor 54 will be sent to first processor 52 with an eight bit data, a UART 32 controlledly played the part of a receiver and the 2nd UART 34 is the controlled transmitters of playing the part of.

First serial line unit 56 in the computer system 50 and second serial line unit 58 also can be in swap datas to each other.See also Fig. 7, Fig. 7 is the four condition figure of computer system 50 in the fifth embodiment of the present invention.In the shown computer system 50 of Fig. 7, the switch SW in the control module 36 ₁, SW ₂, SW ₃, SW ₄, SW ₅, SW ₆, and SW ₇System is respectively with node a and d ₂, b and d ₂, A and C, B and E and c and e link together.Thus, first serial line unit 56 can be via a UART 32 and the 2nd UART 34 and second serial line unit, 58 swap datas of UART ASIC 30.When first serial line unit (host) 56 will be sent to second serial line unit 58 with character picture format data, RECV position (bit1) in six buffers of the one UART 32 in this STATUS buffer can be configured to " 1 ", to receive the character picture format data that transmitted by first serial line unit 56, and the lowest order (XMIT position) of this STATUS buffer can be configured in six buffers of the 2nd UART 34 " 1 ", so that (it is that conversion is from an eight bit data with character picture format data, this eight bit data then is to be got by a UART 32 these character picture format data of conversion) be sent to second serial line unit 58, vice versa, repeats no more in this.

In the shown computer system 50 of Fig. 5, the first processor 52 and second processor 54 are that supposition has an identical operating voltage.Yet, including in the computer system of dual processor at some, the operating voltage of this two processor may not perseverance be identical, and this has between the processor of different operating voltage and swap data directly.See also Fig. 8, Fig. 8 is the constitutional diagram of a computer system 80 in the sixth embodiment of the present invention, the 3rd processor 82 and the four-processor 84 that are comprised in the computer system 80 have different operating voltage (for instance, the operating voltage of the 3rd processor 82 is 2.5v, and the operating voltage of four-processor 84 is 3.3v), and also comprise first serial line unit 56, second serial line unit 58, first system bus 53, second system bus 55, an and UART ASIC 90 in the computer system 80.Different with the shown UART ASIC of Fig. 2 30 is, (point that control module 96 is different from control module 36 is to be that node e in the control module 36 is replaced by the node e in the control module 96 to UART ASIC 90 except comprising a UART 32, the 2nd UART 34 and a control module 96 ₁And e ₂) outside, other comprises one and is electrically connected on node e ₁Electric potential transducer 98.Switch SW in control module 96 ₁, SW ₂, SW ₃, SW ₄, SW ₅, SW ₆, and SW ₇Respectively with node a and c, a and d ₁, b and d ₂, b and e ₁, under A and D, B and D and c and the f situation about linking together, after electric potential transducer 98 can send the 3rd processor 82 and is converted to predetermined voltage via electric potential transducer 98, be sent to the 2nd UART 34 and control module 96 by a UART32 again, and be converted to the voltage level of four-processor 84 by electric potential transducer 98, vice versa.Thus, only pipe has different operating voltage, and the 3rd processor 82 in the computer system 80 and four-processor 84 still can be in swap datas to each other.

In the shown UART ASIC 90 of Fig. 8, electric potential transducer 98 is to be positioned at outside a UART 32 and the 2nd UART 34, certainly, the electric potential transducer in the serial of the present invention also can be arranged at respectively a UART 32/ and or the 2nd UART 34 in.

Compared to known serial (comprising two mutual incoherent serial converters), serial of the present invention not only this first processor of may command and this second processor at the same time or separately with this first serial line unit and this second serial line unit swap data, also can be in swap data to each other.In addition, the first processor and second processor that operate on different operating voltage still can be changed down by the current potential of an electric potential transducer, with the character picture format data-switching current potential that sends or receive to carry out exchanges data, therefore, serial of the present invention has bigger use elasticity.

The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. computer system, it comprises:

One first processor;

One first serial converter, it comprises a parallel port and a serial port;

One second serial converter, it comprises a parallel port and a serial port; And

One control module, be used for optionally this first processor being electrically connected on this first serial converter parallel port, this first processor is electrically connected on the parallel port of this first serial converter and this second serial converter simultaneously, maybe this first processor is electrically connected on the parallel port of the first serial converter and the serial port of this first serial converter is electrically connected on the serial port of this second serial converter.

2. computer system as claimed in claim 1, it comprises a serial line unit that is electrically connected on the serial port of this first serial converter in addition.

3. computer system as claimed in claim 1, it comprises two serial line units in addition, and wherein this control module is used for optionally this two serial line unit being electrically connected on respectively the serial port of this first serial converter and the serial port of this second serial converter in addition.

4. computer system as claimed in claim 1, it comprises second processor in addition, and wherein this control module is used for optionally this second processor being electrically connected on the parallel port of this second serial converter in addition.

5. computer system as claimed in claim 4, wherein, the operating voltage of this first processor is the operating voltage that is same as this second processor.

6. computer system as claimed in claim 4, wherein, the operating voltage of this first processor is the operating voltage that is different from this second processor.

7. computer system as claimed in claim 1, it comprises an electric potential transducer in addition, be electrically connected between the serial port of the serial port of this first serial converter and this second serial converter, be used for adjusting the current potential of the data between the serial port of the serial port that is transmitted in this first serial converter and this second serial converter.

8. computer system as claimed in claim 1, wherein, this control module is a logical circuit.

9. computer system as claimed in claim 1, wherein, this control module is one to be stored in the program code in the internal memory.

10. computer system as claimed in claim 1, wherein, this first serial converter, this second serial converter, and this control module be to be integrated in the Application Specific Integrated Circuit.

11. computer system as claimed in claim 1, wherein, this first serial converter is a UART Universal Asynchronous Receiver Transmitter.

12. computer system as claimed in claim 1, wherein, this first serial converter is an I2C.

13. computer system as claimed in claim 1, wherein, this first serial converter is a USB.

14. a serial, it comprises:

One first serial converter, it comprises a parallel port and a serial port;

One control module is used for optionally parallel port that parallel port with this first serial converter is electrically connected on this second serial converter maybe the serial port of this first serial converter to be electrically connected on the serial port of this second serial converter.

15. serial as claimed in claim 14, it comprises an electric potential transducer in addition, be electrically connected between the serial port of the serial port of this first serial converter and this second serial converter, be used for adjusting the current potential of the data between the serial port of the serial port that is transmitted in this first serial converter and this second serial converter.

16. serial as claimed in claim 14, wherein, this control module is a logical circuit.

17. serial as claimed in claim 14, wherein, this control module is one to be stored in the program code in the internal memory.

18. serial as claimed in claim 14, wherein, this first serial converter, this second serial converter, and this control module be to be integrated in the Application Specific Integrated Circuit.

19. serial as claimed in claim 14, wherein, this first serial converter is a UART Universal Asynchronous Receiver Transmitter.

20. serial as claimed in claim 14, wherein, this first serial converter is an I2C.

21. serial as claimed in claim 14, wherein, this first serial converter is a USB.