CN1319246A - Insulated-gate electron field mission devices and their fabrication processes - Google Patents
Insulated-gate electron field mission devices and their fabrication processes Download PDFInfo
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- CN1319246A CN1319246A CN00801523A CN00801523A CN1319246A CN 1319246 A CN1319246 A CN 1319246A CN 00801523 A CN00801523 A CN 00801523A CN 00801523 A CN00801523 A CN 00801523A CN 1319246 A CN1319246 A CN 1319246A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/30—Cold cathodes, e.g. field-emissive cathode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J21/00—Vacuum tubes
- H01J21/02—Tubes with a single discharge path
- H01J21/06—Tubes with a single discharge path having electrostatic control means only
- H01J21/10—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode
- H01J21/105—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode with microengineered cathode and control electrodes, e.g. Spindt-type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
- H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
Abstract
A lateral-emitter field emission device has a gate (30) that is separated by an insulating layer (40) from a vacuum- or gas-filled environment containing other elements of the device. For example, the gate may be disposed external to a microchamber (110). The insulating layer is disposed such that there is no vacuum- or gas-filled path to the gate for electrons that are emitted from a lateral emitter. The insulating layer disposed between the emitter and the gate preferably comprises a material having a dielectric constant greater than one. The insulating layer also preferably has a low secondary electron yield over the device's operative range of electron energies. For display applications, the insulating layer is preferably transparent. Emitted electrons are confined to the microchamber containing their emitter. Thus, the gate current component of the emitter current consists of displacement current only, and direct electron current from the emitter to the gate is prevented. An array of the devices comprises an array of microchamber, so that electron current from each emitter can reach only the anode in the same microchamber, even for diode devices lacking a gate electrode. A fabrication process is specially adapted for fabricating the device and arrays of such devices, including formation in situ of a vacuum microchamber.
Description
The present invention relates to microelectronic component and manufacturing process thereof, be specifically related to cause emission microelectronics at the insulated gate field of the chamber outer setting gate electrode that comprises emitter and anode.
In specification of the present invention and described claim, use term " grid " and " gate electrode " to represent interchangeably, and tube grid is not still carried out other function as control electrode or extraction electrode except the emitter of electron field emission device or any electrode the anode.Microelectronic component can have more than a grid, and physically different grids can be independently-powered or be applied in relevant current potential.
Term " laterally " refer generally to its on formed the parallel direction of substrate of electronic device.Therefore, " laterally field emission device " refers to a kind of field emission device that forms on substrate, and the structure of its formation makes at least on the direction parallel with substrate anode and field emission utmost point interval at a certain distance.Similarly, term " lateral-emitter " refers to a kind of field emission utmost point, and it is parallel with the substrate of transversal device in fact, makes the electronics emission of anode parallel with substrate basically thus.The example of this lateral-emitter that is formed by film is known in the art.
Term " substrate " refers to following any: the simple radical substrate that is made of independent material, or the compound substrate that is made of the basic substrate that has increased one or more different material layers thereon, or the top layer of this compound substrate.
Developed and comprise diode, a lot of field emission device structures of pliotron and tetrode are used for electronic circuit.Some field emission device has been specially adapted for display.In this display, each pixel cell uses one or more field emission devices.Field-emitter display is considered to a kind of attractive alternative and alternative of plate of flat liquid crystal display, because the manufacturing cost of field-emitter display and complexity are low, energy consumption is low, the brightness height, and angular field of view makes moderate progress.Need update microelectronic component structure and manufacturing process at present, especially for flat-panel monitor.
Known have a lot of field emission device structures, great majority Spindt type normally wherein, and for example in U.S. Patent No. 3,755, the example of describing in 704.Following United States Patent (USP) has been described variously to have transverse field and causes 4,728,851 of the field emission device of emitter and/or their manufacturing process: Lambe; 4,827,177 of Lee etc.; 5,144,191 of Jones etc.; 5,233,263 and 5,308,439 of Cronin etc.; 5,528,099 and 5,445,550 of Xie etc.; 5,629,580 of Mandelman etc.; With 5,616,061,5,618,216,5,628,663,5,630,741,5 of Potter, 644,188,5,644,190,5,647,998,5,666,019,5,669,802,5,691,599,5,700,176,5,703,380,5,811,929,5,831,384,5,850,123,5,872,421,5,920,148,5,965,192,6,004,830,6,005,335,6,015,324,6,015,326,6,017,257,6,037,708 and 6,071,633.
Up to now, microelectronics field emission device of the prior art (comprising Spindt type device and emitted transverse polar form device) is exposed to gate electrode in vacuum identical with emitter or the inflation environment, the direct electron that gate electrode is exposed to from field emissive cathode flows, and allows from the Secondary Emission of the surface generation of gate electrode.
A kind of lateral-emitter field emission device with grid is isolated grid and the vacuum or the inflation environment of other element that comprises this device by insulating barrier.For example, grid can be arranged on the outside of micro chamber.Insulating barrier is set to, and makes for from the lateral-emitter electrons emitted there be not to arrive the vacuum or the inflation path of this grid.Be arranged on insulating barrier between emitter and the grid and preferably include the material that has greater than one dielectric constant.Insulating barrier is preferably in the electron energy effective range of device also has low secondary electron generation rate.For display application, insulating barrier is preferably transparent.Electrons emitted is limited in comprising the micro chamber of their emitter.Therefore, the grid current component of emitter current only is made up of displacement current, and has prevented the direct electron stream from the emitter to the grid.The array of device is made up of the array of micro chamber, makes electron stream from each emitter can only arrive the anode in the identical micro chamber, even also be like this for the diode component that lacks gate electrode.A kind of manufacturing process is particularly suitable for making the array of this device and this device, comprises that original position (in situ) forms the vacuum micro chamber chamber.Part I-" oppositely " limited electron field emission device and display element
The full content of following file is included in this as a reference: the U.S. Patent application 09/020 that on February 9th, 1998 submitted to, 547 and 09/020,548 (the two is all abandoned), the U.S. Patent application 09/276 that on March 25th, 1999 submitted to, 198 and 09/276,200, the United States Patent (USP) 6 that on December 21st, 1999 authorized, International Patent Application PCT/US99/02609 that on February 6th, 004,830 and 1999 submitted to.
Fig. 1-13 shows a series of side view cutaway drawings, the overall manufacturing of the limited electronic device that expression is carried out according to the present invention;
Figure 14 shows a flow chart, the overall fabrication process that expression is carried out according to the present invention;
Figure 15-27 shows a series of side view cutaway drawings, the manufacturing of the insulated-gate electron field mission devices that expression is carried out according to the present invention.Realize pattern of the present invention
Described herein is a kind of new reverse limited electron field emission device.This structure is not in the emitter of device and the vacuum path between the grid.This new construction has been eliminated any possible DC gate current, thereby makes this device show as pure emitting electrons field-effect transistor.Can be by similar device architecture, solid state device structure (for example silicon or comprise CMOS, NMOS, PMOS, Bipolar, the III of Bi-CMOS etc.-V material) constitutes integrated circuit.This new unit can also be used for display element or be used as display system.It can or can be used in combination with luminescent material on independent assembly in conjunction with integrated luminescent material.It can also have integrated display driver circuit.
Fig. 1-11 shows a series of side view cutaway drawings, represents each stage of the overall craft of device constructed in accordance.Figure 14 is the flow chart of first overall craft of expression device constructed in accordance.
If use conductive substrates 15, so on conductive substrates 15 deposit first insulating barrier to form dielectric substrate 20.As shown in Figure 1, if use dielectric substrate 20, omit above-mentioned steps so.
Deposit and patterning conductive grid material 30 (Fig. 1) on first insulating barrier.Deposit second insulating barrier 40 (Fig. 2) on grid layer 30.Deposit and patterning conductive emitter layer 50 (Fig. 3) on second insulating barrier 40.Deposit the 3rd insulating barrier 60 (Fig. 4) on emitter layer 50.Form groove 70 (Fig. 5), to remove a part the 3rd insulation 60 downwards up to emitter layer 50.Remove the emitter material (Fig. 6) in the groove qualification district, on emitter layer 50, stay next transmitting side at least along 80.Can remove a part of second insulating barrier 40.But, keep a part of second insulating barrier 40, this eliminated any vacuum path and prevent emitter 50 and grid 30 between the DC electric current.
Can provide conventional contact hole by the semiconductor making method of routine, interlayer joint pin or the like (not shown).
Can be formed for the assembly of various systems (for example flat-panel monitor) by the structure of this technology manufacturing.In the case, the individual panels 100 that is coated with luminescent material is placed (Fig. 7) on the trench area, form chamber 110.In a particular embodiment, can between emitter 50 (being that transmitting side is along 80) and panel 100, insert the focus mask (not shown).In another embodiment, can replace panel to be used as anode with electric conducting material.Can also use spacer 90 and/or sealant.
Said structure (Fig. 1-6) can be the part of an integrated device.This integrated device can be active pliotron or display element.Under the situation of active pliotron element, after forming groove 70, deposit and composition expendable material 120 (Fig. 8), expendable material 120 at least complete filling groove limit district 70.
Deposit conductive anode 130 (Fig. 9) on the aggregate surface of the 3rd insulating barrier 60 and sacrifice layer 120.If desired, can be to these conductive anode 130 compositions.
Utilize example, standard semiconductor fabrication techniques to leave and enter hole 140 (Figure 10) by anode conductive layer 130.Remove expendable material 120 by entering hole 140, stay empty chamber 160.
Deposit encapsulant 150,155 (Figure 11) in vacuum system.Vacuum level is restricted to the degree of enough pliotron device operations.If desired, can original position backflow encapsulant 150,155.If desired, can be to encapsulant 150,155 compositions.
Can provide conventional contact hole, interlayer joint pin or the like (not shown) by conventional semiconductor making method.
Under the situation of display element, after forming groove 70, deposit and composition expendable material 120, expendable material 120 complete filling groove at least limit district's 70 (see figure 8)s.
The luminous anode material 135 of deposit on the aggregate surface of the 3rd insulating barrier 60 and sacrifice layer 120.If desired, can be to these luminous anode material layer 135 compositions.If desired, can be on luminous material layer 135 deposit the 4th transparent insulating layer (not shown).Utilize example, standard semiconductor fabrication techniques to leave and enter hole 140 by anode material layer 135.Remove expendable material 120 (see figure 10)s by entering hole 140.
Deposit encapsulant 150,155 (Figure 13) in vacuum system.The vacuum level that is provided should reach the degree of enough display element operations.If desired, can original position backflow encapsulant 150,155.Can be to encapsulant 150,155 compositions, to remove its part on the display element light emitter region.If layer 150,155th, transparent material can not done above-mentioned processing.S1 provides substrate S 1a if desired, insulating barrier S6 on the insulating barrier S4 deposit of deposition insulating layer S2 deposit and patterned gate electrode S3 deposit covering grid electrode and the composition emitter S5 deposit emitter forms opening by insulating barrier, on emitter, do not form transmitting side and provide and deposit anode S9 closed chamber (S9a) and execution in step S11 and do not expose gate electrode S7 along S8, S12, S13, S14 and S15S9a closed chamber S10 (combination of execution in step S8 and S9a simultaneously) S11 deposit and composition expendable material S12 deposited capping layer S13 form by cover layer and enter hole S14 and remove expendable material S15 embolism and enter the hole by entering the hole, and the device S17 that the S16 of sealed chamber is provided for applying bias voltage is provided for applying the device table I of control signal. the processing step of Figure 14
Figure 14 is the flow chart of expression overall fabrication process, uses label S1, S2 ..., S17 represents each processing step.For each step, (top) listed in performed operating in the table I.Part II-insulated-gate electron field mission devices and technology
What describe in the following specification (part II) is a kind of new insulated-gate electron field mission devices.This structure is not in the emitter of device and the vacuum path between the grid.This new construction has been eliminated any possible DC gate current, thereby makes this device show as pure emitting electrons field-effect transistor.Can be by similar device architecture, solid state device structure (for example silicon or comprise CMOS, NMOS, PMOS, Bipolar, the III of Bi-CMOS etc.-V material) constitutes integrated circuit.This new unit is specially adapted to comprise the frequency applications of wireless communication system.
First kind of situation describing in this part (part II) is the common gate structure that is used for the work simplification purpose.Preferred embodiment is second kind of situation in this part (part II).
As shown in figure 15, use conductive substrates 15, therefore deposit first insulating barrier 25 on conductive substrates 15 forms dielectric substrate.Deposit second insulating barrier 40 on first insulating barrier.The mutual difference of first insulating barrier 25 and second insulating barrier 40 is to have different etching characteristics for the corrosive agent that uses in the technology of back.
Deposit and patterning conductive emitter material layer 50 (Figure 16) on second insulating barrier.Deposit the 3rd insulating barrier 60 (also shown in Figure 16) on emitter layer 50.
The 3rd insulating barrier 60 compositions (Figure 17) are respectively applied for the opening 65 and 75 of emitter contact stud and anode member by corrosion with formation.As shown in figure 17, this etching process stops on the emitter layer 50 and first insulating barrier 25.
In opening 65 and 75, fill (Figure 18) electric conducting material forming emitter contact stud 85 and anode 95 respectively, and carry out complanation by the chemico-mechanical polishing (CMP) of using routine.Erode away groove 70 (Figure 19),, on emitter layer 50, stay next transmitting side, and expose a part of anode 95 at least along 80 to expose a part of emitter layer 50 at least.As shown in figure 19, this corrosion stops on first insulating barrier 25.
At the 3rd insulating barrier 60, deposit sacrifice layer 120 (Figure 20) on emitter contact stud 85 and the anode 95.As shown in figure 20 to the sacrifice layer composition.Deposit the 4th insulating barrier 165 (Figure 21) on the 3rd insulating barrier 60 and sacrifice layer 120. Enter hole 170 and 180 by the 4th insulating barrier 165 compositions and corrosion, and remove (Figure 22) expendable material 120, reserve empty opening 70 by entering hole 170 and 180.As shown in figure 22, the position that enters hole 170 and 180 is set to, and makes each enter at least a portion in hole and following element alignment, and one enters hole (170) and aims on emitter contact stud 85, and another enters hole (180) and aims on anode 95.
Deposition materials 190 (for example metal) on the 4th insulating barrier 165 in a vacuum.Material 190 is refluxed to be sealed into hand- hole 170 and 180 by original position.To encapsulant 190 compositions being retained in the material that enters on hole 170 and 180, thereby be sealed into hand-hole.Therefore the chamber body original position is manufactured vacuum chamber 160.The gland cock that is formed by material 190 can further provide with the electric conducting material of emitter and anode and contact (Figure 23).
Under second kind of situation (preferred embodiment), a kind of structure that is used for unshared grid disclosed below, it has significantly reduced the electric capacity of grid to emitter and grid to anode.The reduction of electric capacity makes the switch speed and the overall performance maximization of device.
If use conductive substrates 15, deposit first insulating barrier 25 is with isolating device so.If use dielectric substrate 20, do not need the first extra insulating barrier 25 so.The technology that is used for dielectric substrate 20 is described below.Gate groove 200 compositions are also corroded to obtain dielectric substrate (Figure 24).Deposit first conductive gate layer 210 on dielectric substrate, and be planarized to the level (Figure 25) of filling groove, to form gate electrode 30.
Technology (Figure 15-16) from deposit first insulating barrier to deposit the 3rd insulating barrier during technology hereafter and front are described is identical.
For composition and corrode the step (as Figure 17) of the 3rd insulating barrier, provide the 3rd opening (not shown), as the grid conductive contact that is used to contact gate electrode 30 with the opening that obtains being used for emitter contact stud and anode.The corrosion step of carrying out grid conducting layer 210 is to provide this gate contacts.(this gate contacts does not illustrate outside the section plane of Figure 26 and 27).
If wish to make display device, anode 95 is made of luminescent material at least in part.
As shown in figure 27, can replace anode to make bilateral device by mirror image with emitter spare 50 and grid spare 30.Grid 30 can be shared between two emitters 50, and perhaps independent grid 30 can be controlled each emitter 50.Can provide conventional contact hole by the semiconductor making method of routine, interlayer joint pin or the like.
The present invention is applicable to the manufacturing field emission device, be particularly useful for the field-emitter display that constitutes by the field emission device array, because each device in the array can have the independent micro chamber that comprises emitter and cathodoluminescence anode, this anode is only in response to the electronics from its oneself emitter.If utilize insulating barrier that gate electrode and each micro chamber are isolated, each microelectronic component has improved performance so.This preferred manufacturing process is particularly useful for making in a lot of devices in this array.
The present invention eliminates or has greatly reduced the direct electric current from the emitter to the grid in the electron field emission microelectronic component.The present invention can also reduce undesirable secondary, and need not to introduce the supplemantary electrode that is used to suppress secondary.Otherwise the secondary of gate electrode can influence the control of gate electrode antianode electric current unfriendly.In display device, comprise under the situation of fluorophor at least a portion of the anode of each pixel, eliminated crosstalking between the pixel.
Though in the detail specifications of accompanying drawing and front, show and described specific embodiment of the present invention, should be appreciated that the present invention is not limited to described specific embodiment.As can be seen, the present invention can implement with the multiple conversion and the modification that are different from above-mentioned specification from above-mentioned specification.For example, the order of execution in step can be changed, the function of use identical materials can be replaced.For another example, can also adopt the more gate electrode (not shown) of isolating in a similar manner so that three or four gate electrodes to be provided in the multigate device chamber.Following what is claimed is in order to contain all such modifications.Therefore, scope of the present invention should be definite by the foregoing description, and should be determined by claims and legal equivalents thereof.
Claims (46)
1. insulated-gate electron field mission devices comprises:
A) dielectric substrate;
B) with the conductive gate electrode of described dielectric substrate adjacency;
C) with the coextensive chamber of at least a portion of described gate electrode;
D) anode is provided to receive the electronics that is transmitted in the described chamber; With
E) have the electron emitter on transmitting side edge, be provided to the electronics emission be entered and arrive described anode by described chamber;
Described device is characterised in that to have
F) be arranged on insulating barrier between the described part of described chamber and described gate electrode, prevent direct electron stream thus from described electron emitter to described gate electrode.
2. insulated-gate electron field mission devices comprises:
A) dielectric substrate;
B) with the conductive gate electrode of described dielectric substrate adjacency;
E) with the coextensive chamber of at least a portion of described gate electrode;
D) be arranged on insulating barrier between the described part of described chamber and described gate electrode;
E) anode is provided to receive the electronics that is transmitted in the described chamber; With
F) have the electron emitter on transmitting side edge, be provided to the electronics emission be entered and arrive described anode by described chamber.
3. according to the device of claim 1, wherein said dielectric substrate (a) comprising:
ⅰ) the basic substrate of from conductor and semiconductor, selecting; With
ⅱ) the insulating barrier of the described basic substrate of covering.
4. according to the device of claim 1, further comprise a plurality of gate electrodes.
5. according to the device of claim 1, wherein said dielectric substrate (a) comprises the material of selecting from following tabulation: glass, ceramic material, silica, silicon nitride, aluminium oxide, boron nitride, and diamond.
6. according to the device of claim 1, wherein said dielectric substrate (a) comprises transparent in fact substrate.
7. according to the device of claim 1, further comprise:
G) be used for applying to described emitter and described anode the device of bias voltage, described voltage can produce from described transmitting side effectively along the electron field emission electric current to described anode.
8. according to the device of claim 7, further comprise:
H) be used for applying control voltage to control the device of described electric current to described gate electrode.
9. according to the device of claim 1, further comprise being used for applying the device that extracts voltage to described gate electrode.
10. according to the device of claim 1, wherein said dielectric film comprises for the incident electron energy in effective range having material less than one secondary generation rate.
11. according to the device of claim 1, wherein said dielectric film comprises the material that has greater than about four dielectric constant.
12. according to the device of claim 1, wherein said dielectric film comprises first and second layers, wherein
ⅰ) material of described ground floor is selected as having the dielectric constant bigger with respect to the described second layer;
ⅱ) material of the described second layer is selected as having the secondary electron generation rate lower with respect to described ground floor, and the described second layer is set to form the inner surface of described chamber.
13. according to the device of claim 12, wherein said ground floor has the dielectric constant greater than about four, the described second layer has secondary generation rate less than one for the incident electron energy in the effective range.
14., comprise a plurality of described gate electrodes according to the device of claim 12.
15. according to the device of claim 1, wherein said dielectric film comprises the substrate of selecting from following group: silicon nitride, aluminium oxide, titanium carbide, tungsten carbide, vanadium diboride, titanium diboride, barium titanate, strontium titanates, barium strontium titanate, and tantalum oxide.
16. according to the device of claim 1, wherein said dielectric film comes down to transparent.
17. according to the device of claim 1, described chamber has inner surface, wherein said dielectric film is arranged between the described inner surface and described gate electrode of described chamber.
18. according to the device of claim 1, described chamber has inner surface, wherein said dielectric film forms at least a portion of the described inner surface of described chamber.
19. according to the device of claim 1, wherein said anode comprises the fluorophor that is used to form display device.
20. according to the device of claim 1, wherein said gate electrode comprises transparent in fact electric conducting material.
21. according to the device of claim 1, wherein said gate electrode comprises the transparent conductive material of selecting from following group: indium oxide, tin oxide, and indium tin oxide target.
22. a method that is used to make field emission device may further comprise the steps:
A) provide a dielectric substrate;
B) deposit and composition one electric conducting material are to form gate electrode;
C) deposit first insulating barrier covers described gate electrode;
D) deposit and composition one electric conducting material are to form emitter;
E) deposit second insulating barrier on described emitter;
F) form an opening by described second insulating barrier, expose the part of described emitter, and do not expose described gate electrode;
G) the transmitting side edge of the described expose portion of the described emitter of formation; With
H) provide an anode.
23. insulated-gate electron field mission devices of making by the method for claim 22.
24. according to the method for claim 22, wherein said dielectric substrate provides that step (a) is following carries out:
ⅰ) provide a conductive substrates and
ⅱ) on described conductive substrates deposit the 3rd insulating barrier to form described dielectric substrate.
25. according to the method for claim 22, wherein said transmitting side is along forming following the carrying out of step (g):
At least a portion of described expose portion of removing described emitter is to form the transmitting side edge.
26. the method according to claim 22 further may further comprise the steps: remove the part of described first insulating barrier, keep a certain amount of described first insulating barrier simultaneously to cover the whole of described gate electrode.
27. according to the method for claim 26, whole described a certain amount of described first insulating barrier that wherein covers described gate electrode has preset thickness.
28. the method according to claim 22 further may further comprise the steps: cover described opening comprises described transmitting side edge and described anode with sealing chamber.
29., further comprise the step of the described chamber of finding time according to the method for claim 28.
30. the method according to claim 22 further may further comprise the steps:
Be provided for applying to described emitter and described anode the device of bias voltage, described bias voltage can produce from described transmitting side effectively along the electron field emission electric current to described anode.
31. the method according to claim 30 further may further comprise the steps:
Be provided for applying control voltage to control the device of described electric current to described gate electrode.
32. the method according to claim 30 further may further comprise the steps:
Be provided for applying extraction voltage to extract the device of described electronics to described gate electrode.
33. according to the method for claim 22, wherein said electric conducting material deposit and pattern step (b) is following carries out: the described electric conducting material of composition is to form a plurality of gate electrodes.
34. according to the method for claim 22, wherein said anode provides that step (h) is following carries out: with the described emitter deposit positive plate that keeps at a certain distance away.
35. according to the method for claim 34, wherein said anode provides that step (h) is following carries out: at least one wall of deposit between described positive plate and described second insulating barrier.
36. according to the method for claim 34, wherein said anode provides that step (h) is following carries out: deposit is coated with the positive plate of luminescent material.
37. the method according to claim 22 further may further comprise the steps:
Deposit one grid between described emitter and described anode.
38. according to the method for claim 28, wherein said opening covers step and carries out following substep:
ⅰ) deposit and composition one expendable material in described opening are filled described opening at least;
ⅱ) deposit one cover layer on described expendable material and described second insulating barrier, described tectal material is selected from conductor and luminescent material;
ⅲ) form one and enter opening to described expendable material by described cover layer;
ⅳ) remove described expendable material by the described opening that enters; With
ⅴ) provide effective vacuum environment, simultaneously at the described deposit sealant that enters in the opening with the described opening of embolism, thereby sealing comprises the chamber of described transmitting side edge and described anode.
39. the method according to claim 38 further may further comprise the steps:
ⅵ) the described sealant of composition.
40. according to the method for claim 38, wherein said effective vacuum environment comprises a certain amount of inert gas.
41. according to the method for claim 38, wherein said effective vacuum environment has residual gas pressure, described residual gas pressure is enough low to allow the operation of described device.
42. according to the method for claim 38, the covering layer material of wherein said selection is selected from transparent conductor and transparent luminescent material.
43. a method that is used to make field emission device may further comprise the steps:
A) provide a dielectric substrate;
B) deposit and composition one electric conducting material are to form gate electrode;
C) deposit first insulating barrier covers described gate electrode;
D) deposit and composition one electric conducting material are to form emitter;
E) deposit second insulating barrier on described emitter;
F) form an opening by described second insulating barrier, expose the part of described emitter, and do not expose described gate electrode;
G) remove at least a portion of described expose portion of described emitter with the transmitting side edge of the described expose portion that forms described emitter;
H) provide an anode, cover described opening comprises described transmitting side edge and described anode with sealing chamber simultaneously;
J) be provided for applying to described emitter and described anode the device of bias voltage, described bias voltage can produce from described transmitting side effectively along the electron field emission electric current to described anode; With
K) be provided for applying control voltage to control the device of described electric current to described gate electrode.
44. according to the method for claim 43, wherein said anode provides with opening and covers the following substep of step (h) execution:
ⅰ) deposit and composition one expendable material in described opening are filled described opening at least;
ⅱ) deposit one cover layer on described expendable material and described second insulating barrier, described tectal material is selected from conductor and luminescent material;
ⅲ) form one and enter opening to described expendable material by described cover layer;
ⅳ) remove described expendable material by the described opening that enters; With
ⅴ) provide effective vacuum environment, simultaneously at the described deposit sealant that enters in the opening with the described opening of embolism, thereby sealing comprises the chamber of described transmitting side edge and described anode.
45. according to the method for claim 22, wherein said opening forms step (f) and comprising: with in described emitter and the described anode at least one to small part aims at the described opening of deposit.
46. according to the method for claim 45, wherein said opening forms step (f) and comprising: aim at least two openings of ground deposit respectively with described emitter and described anode to small part.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14557099P | 1999-07-26 | 1999-07-26 | |
| US60/145,570 | 1999-07-26 |
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| CN1319246A true CN1319246A (en) | 2001-10-24 |
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| KR102084288B1 (en) | 2012-11-05 | 2020-03-03 | 유니버시티 오브 플로리다 리서치 파운데이션, 아이엔씨. | Brightness compensation in a display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2635913B1 (en) * | 1988-08-31 | 1990-11-09 | Saint Louis Inst | FIELD EMISSION DIODE |
| JPH0340332A (en) * | 1989-07-07 | 1991-02-21 | Matsushita Electric Ind Co Ltd | Electric field emitting type switching element and manufacture thereof |
| JP2574500B2 (en) * | 1990-03-01 | 1997-01-22 | 松下電器産業株式会社 | Manufacturing method of planar cold cathode |
| DE4010909A1 (en) * | 1990-04-04 | 1991-10-10 | Siemens Ag | Cold-emission protection diode - has air-isolated electrodes with micrometric separation to prevent electrical discharge |
| US5289086A (en) * | 1992-05-04 | 1994-02-22 | Motorola, Inc. | Electron device employing a diamond film electron source |
| US5534743A (en) * | 1993-03-11 | 1996-07-09 | Fed Corporation | Field emission display devices, and field emission electron beam source and isolation structure components therefor |
| US5445550A (en) * | 1993-12-22 | 1995-08-29 | Xie; Chenggang | Lateral field emitter device and method of manufacturing same |
| US5442193A (en) * | 1994-02-22 | 1995-08-15 | Motorola | Microelectronic field emission device with breakdown inhibiting insulated gate electrode |
| US5629580A (en) * | 1994-10-28 | 1997-05-13 | International Business Machines Corporation | Lateral field emission devices for display elements and methods of fabrication |
| EP0827626A4 (en) * | 1995-05-08 | 1998-06-17 | Advanced Vision Tech Inc | Field emission display cell structure and fabrication process |
| US5644188A (en) * | 1995-05-08 | 1997-07-01 | Advanced Vision Technologies, Inc. | Field emission display cell structure |
| US5604399A (en) * | 1995-06-06 | 1997-02-18 | International Business Machines Corporation | Optimal gate control design and fabrication method for lateral field emission devices |
| AU6273396A (en) * | 1995-06-13 | 1997-01-09 | Advanced Vision Technologies, Inc. | Laminar composite lateral field-emission cathode and fabrica tion process |
| WO1997002586A1 (en) * | 1995-07-05 | 1997-01-23 | Advanced Vision Technologies, Inc. | Direct electron injection field-emission display device and fabrication process |
| WO1997009733A1 (en) * | 1995-09-06 | 1997-03-13 | Advanced Vision Technologies, Inc. | High-frequency field-emission device and fabrication process |
| AU2661399A (en) * | 1998-02-09 | 1999-08-23 | Advanced Vision Technologies, Inc. | Confined electron field emission device and fabrication process |
| CN1128461C (en) * | 1998-03-21 | 2003-11-19 | 韩国科学技术院 | Line field emitter display |
| US6437360B1 (en) * | 1998-03-25 | 2002-08-20 | Korea Advanced Institute Of Science And Technology | Vacuum field transistor |
-
2000
- 2000-07-24 KR KR1020017003710A patent/KR20010075311A/en not_active Application Discontinuation
- 2000-07-24 JP JP2001512613A patent/JP2003505843A/en not_active Withdrawn
- 2000-07-24 EP EP00948927A patent/EP1116255A1/en not_active Withdrawn
- 2000-07-24 CA CA002355660A patent/CA2355660A1/en not_active Abandoned
- 2000-07-24 CN CN00801523A patent/CN1319246A/en active Pending
- 2000-07-24 WO PCT/US2000/020144 patent/WO2001008192A1/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| CA2355660A1 (en) | 2001-02-01 |
| JP2003505843A (en) | 2003-02-12 |
| WO2001008192A1 (en) | 2001-02-01 |
| EP1116255A1 (en) | 2001-07-18 |
| KR20010075311A (en) | 2001-08-09 |
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