CN1307688C - 氙预无定形化植入法 - Google Patents

氙预无定形化植入法 Download PDF

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CN1307688C
CN1307688C CNB028152212A CN02815221A CN1307688C CN 1307688 C CN1307688 C CN 1307688C CN B028152212 A CNB028152212 A CN B028152212A CN 02815221 A CN02815221 A CN 02815221A CN 1307688 C CN1307688 C CN 1307688C
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M·S·布诺斯基
C－H·恩
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Advanced Micro Devices Inc
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Abstract

在形成源/漏极延伸区域(21)和源极/漏极区域(41)之前，利用植入Xe(15)将硅绝缘层基板(101)预无定形化，藉此消除或大幅降低浮体效应。另一方面包括在形成具有减少垂直与横向散布的浅层接面的源极/漏极延伸区域和源极/漏极区域之前，将Xe2 +离子植入到表体硅或SOI基板中，以产生无定形化的效果。

Description

氙预无定形化植入法
技术领域
一般而言，本发明关于制造半导体装置，特别是具有超浅层接面深度的高度小型化半导体。
背景技术
半导体制造技术历经不断的挑战，如设计尺寸持续地向下深入至次微米领域，例如制造具有大约及小于0.12微米之设计标准的装置。以有效方法准确形成具有高信赖度之超浅层接面深度(Xj)系成为十分具有挑战性的问题。
预无定形化技术，例如藉由离子植入硅(Si)或锗(Ge)，以在掺杂物植入和退火之前定义源极/漏极区域的轮廓等已被用来降低穿隧效应(channeling effect)与减少瞬间增强扩散(transient enhanced diffusion，TED)，并降低活化温度。然而，此种预无定形化(SPE)技术并非没有不利之处。例如，植入的Si和Ge离子容易漂移越过源极/漏极区域导致所谓之植入散布(implantation straggle)，该散布包括垂直和水平两种，因而非常难以精确定义例如在400埃以下的超浅层源极/漏极延伸区域。
当设计尺寸下降至深次微米的范围时，沟道长度，亦即穿越沟道接面之间的距离，系逐渐成为临界尺寸，尤其当沟道长度降低至大约及小于1000埃时。接面位置的自然差异以及加工处理所引起的差异使得准确设计装置变得困难。从TED所引起掺杂轮廓的改变以及植入散布加重了设计上的问题。
传统硅绝缘层(SOI)型基板具有逐步形成和基本上包括一基板、一位于该基板上方埋入的氧化物层以及在该埋入氧化物层上为构成该晶体管之″主体″的半导体层。在此种SOI装置中，该主体浮动在其中，并未直接电性连接至该装置。当源极和漏极区域与该基板绝缘时，接面电容降低，亦即当源极和漏极其中之一或两者的电讯号改变时，会大幅减少对基板的电容偶合。当采用SOI基板促进电性绝缘时，电路中的某些电性组件可以彼此更紧密地放置，藉此缩小芯片尺寸。SOI结构也可提供更快速开闭的优点。此外，由于基板为埋入的氧化物所绝缘，因此栓锁作用(latchup)通常发生在CMOS装置，不存在于使用SOI基板的情况。在SOI装置中，静电电弧或等离子体电弧也会减少。
然而，制造半导体装置中使用SOI基板会带来缺点。显著的缺点称之为″浮体效应″(floating body effects)。例如，要花费相当长的时间来泄漏释出电荷(ejected charge)。其结果，可能产生瞬时双极效应(transientbipolar effect)，其中会激活类似MOSFET的寄生偶极晶体管。此外，会产生磁滞效应(hysteresis effect)。
因此需要对于制造具有准确之超浅层接面的有效方法。而同样也需要制造以SOI基板为主，没有浮体效应而具有准确之超浅层接面的有效方法。
发明内容
本发明的优点是具有减少浮体效应的SOI结构的半导体装置的制造方法。
本发明的另一优点为制造具有超浅层接面的半导体装置，以及准确形成源极/漏极延伸区域和源极/漏极区域。
本发明的额外优点和其它特征将在以下的说明书中提到，就某种程度上而言，本领域技术人员经由参照下文或者可从本发明的实施中学习，而轻易了解本发明之额外优点和其它特征。本发明的优点可根据权利要求所特别指出得以了解及获得。
根据本发明，上述与其它优点在某种程度上可藉由制造半导体装置的方法来达成，该方法包括：形成包含较低硅基板；在基板上埋入的绝缘层；以及在绝缘层之上结晶硅上层的硅绝缘体(SOI)结构；将氙(Xe)离子植入到上硅层，在该层中形成从上表面向埋入的绝缘层延伸的无定形区域；离子植入掺杂杂质以形成源极/漏极延伸区域植入物和源极/漏极区域植入物；退火以活化浅层源极/漏极延伸区域和源极/漏极区域，并且使该无定形区域结晶。
本发明的实施方案包括：以氧化硅埋入的绝缘层形成SOI结构，以大约1×1014至大约5×1014离子/cm2的植入剂量及大约1KeV至大约200KeV的植入能量将氙离子植入。本发明的实施方案包括在大约500℃至大约650℃，例如大约550℃至大约600℃的温度退火，使源极/漏极延伸区域和源极/漏极区域活化，并且使得由Xe离子植入所形成的无定形区域再结晶。本发明的实施方案包含在形成源极/漏极区域之前形成源极/漏极延伸区域，并且还包含在形成源极/漏极延伸区域之前形成源极/漏极区域的可移除间隔片技术。
本发明另一方面为制造半导体装置的方法，该方法包括：提供一主要由氙二聚物(Xe2 +)所构成的离子束；将Xe2 +植入到结晶半导体基板，在该基板中形成无定形化的区域；将掺杂杂质离子植入到该无定形区域，形成源极/漏极延伸区域植入物，和源极/漏极区域植入物；以及退火以活化该源极/漏极延伸区域和源极/漏极区域并且使该无定形区域再结晶。
实施方案包含分析第一Xe离子束和选择性地从该离子束中提取Xe2 +束。本发明的实施方案包括将Xe2 +离子植入到包含表体硅和SOI基板的基板中，以预无定形化离子植入掺杂杂质之前的区域，然后在大约500℃至大约650℃的温度退火。本发明的实施方案包括将Xe2 +离子植入到表体硅基板中形成具有深度不超过大约250埃的无定形化区域，例如大约100埃至250埃，接着以大约500℃至650℃温度的中度退火形成源极/漏极延伸区域和源极/漏极区域。
本领域技术人员可从以下的详细说明，轻易了解本发明另外的优点，其中简单地藉由本发明最佳实施方案的图解，说明本发明的实施方案。应能了解本发明能实施其它不同的实施方案，其数种详述能实施明显不同方面的修饰，皆不背离本发明。因此，附图及说明将视为本质上示范的说明，并非作为限制之用。
附图说明
图1至图4说明根据本发明实施方案的方法的连续顺序阶段。
图5和图6说明根据本发明其它实施方案的方法的连续顺序阶段。
图7说明适合用于本发明实施方案的离子植入设备。
发明详述
本发明提供经由大幅减少垂直和横向散布以制造具有明确界定的超浅层接面的半导体装置，特别是具有SOI基板的半导体装置的可行方法。本发明也提供利用Xe离子植入，特别是经由离子植入Xe2 +以制造具有明确界定的超浅层接面的半导体装置的有效方法。本发明进一步提供可制造包含大幅降低浮体效应之SOI基板的半导体装置的方法。
采用Xe离子植入在形成源极/漏极延伸区域和源极/漏极区域之前预无定形化，造成有利于在SOI型结构中，降低浮体效应的确切机制仍无法确知。然而，相信结合相对Xe而言为高原子量和大离子体积的元素，例如Ge和Si，及较少的横向和垂直散布，有助于杂质活化且以某种方式使Xe包含于再结晶晶格中，以大致上消除或大幅降低浮体效应，而不会有一般由于离子植入的晶体损坏所造成过量的漏电流。
本发明的实施方案包括将Xe离子植入到SOI基板的上结晶层中，以预无定形化该上硅层，该SOI基板包括基板、埋入的绝缘层(如二氧化硅)与在该绝缘层之上的上结晶层。接着进行随后的离子植入和退火，利用在栅电极上的侧壁间隔片形成源极/漏极延伸区域和源极/漏极区域。在Xe离子植入之后的活化退火可以在比传统活化温度大约800℃至大约1,050℃，相对较低的温度大约500℃至大约650℃的有利条件下进行。因此，本发明的实施方案包含在形成源极/漏极区域之前或之后形成源极/漏极延伸区域。
本发明的实施方案包含在SOI基板的上结晶硅层之上形成栅电极结构，然后例如以大约1×1014至大约5×1014离子/cm2的植入剂量及大约1KeV至大约200KeV的植入能量(例如大约10KeV至大约130KeV)，将Xe离子植入，以无定形化该上硅层向下达到埋入的绝缘层。
在图1-4中概要说明根据本发明实施方案的方法，其中以相似的参考数字表示相似的特征或组件。形成包括有基板10、埋入的绝缘层11(例如二氧化硅)、上结晶硅层12的SOI结构。该上结晶硅层12通常具有大约100埃至1000埃的厚度。在上硅层12之上隔着栅绝缘层13形成栅电极14。例如图1所示，进行Xe离子植入以预无定形化上硅层12的上面部分向下达到投影深度，在栅电极14每一侧上方形成无定形区域12A。本发明的实施方案包含预无定形化上硅层12直到大约400埃的深度，例如50至300埃，而且向下达到埋入的绝缘层11。
其后，如箭头20所示，进行杂质物种的离子植入，例如N型杂质，如砷或磷。一般而言，此等离子植入系以大约1×1014至大约5×1014离子/cm2的植入剂量及大约200KeV至大约10KeV的植入能量进行，以形成浅层源极/漏极延伸区域植入物。接着，例如在大约500℃至650℃(例如大约550℃至大约600℃)的温度进行退火，使源极/漏极延伸区域21活化，并且使无定形区域12A再结晶。该源极/漏极延伸区域21通常会从上硅层表面12延伸到大约50埃至大约300埃的深度。
然后，在栅电极14侧表面之上形成侧壁间隔片30，如图3所示。侧壁间隔片30可以包括例如二氧化硅或氮化硅的绝缘材料。再次进行Xe离子植入，如箭头30所示，以形成毗邻源极/漏极延伸区域21的无定形区域12B。此等Xe植入可以在先前图1所揭示的条件下进行。
其后，如图4所示，通常以大约1×1014至大约5×1014离子/cm2的植入剂量及大约10KeV至大约60KeV的植入能量，进行离子植入，例如箭头40所示，以形成源极/漏极区域植入物。接着例如在大约500℃至大约650℃的温度进行退火，以活化源极/漏极区域41，并且使无定形区域12B再结晶。在SOI结构上制造半导体装置中，Xe离子植入的用途有利于消除或大幅降低浮体效应，藉此改善装置的信赖性。在图1-4所示的实施方案中，在形成源极/漏极区域之前形成源极/漏极延伸区域。然而，考虑到有利于因Xe离子植入而导致的杂质活化所采用的极低退火温度，可以使用可移除间隔片技术，在形成源极/漏极延伸区域之前形成源极/漏极区域。在图5-6中概要说明此种实施方案，其中例如图1-4中所采用的组件和特征，相似的参考数字表示相似的特征和相似的组件。图5系形成包括基板10、埋入的绝缘层11和上结晶硅层12的SOI结构105。在上硅层12之上隔着栅绝缘层13形成栅电极14。然后在栅电极14和栅绝缘层13的侧表面之上形成侧壁间隔片15。随后进行Xe离子植入，使上结晶层12无定形化向下达到侧壁间隔片15相对侧上方之埋入的绝缘层11，接着藉由离子植入形成源极/漏极区域植入物，然后例如在大约500℃至大约650℃的温度退火，形成源极/漏极区域16。
其后，移除侧壁间隔片15，如图6所示，再次进行Xe离子植入，在上硅层12中形成上无定形区域向下达到投影深度，接着藉由杂质离子植入，形成源极/漏极延伸区域植入物。本发明的实施方案包含形成无定形区域直到大约400埃的深度(例如大约50埃至大约300埃)，而且向下达到埋入的绝缘层11。然后例如在大约500℃至大约650℃的温度进行退火，使源极/漏极延伸区域20活化，并且使无定形区域再结晶，形成如图6所示的结构。
本发明之另一方面包括经由离子植入氙二聚物(Xe2 +)预无定形化，藉此使得超浅层接面深度以及经过精确控制的源极/漏极延伸区域和源极/漏极区域得以形成。在低吸引电压下，从Xe源提取Xe2 +，并藉由离子植入装置内的检偏镜磁铁进行分析。根据本发明的实施方案，Xe2 +作为预无定形化的用途不仅包含SOI结构而且还包含传统的基板结构，例如表体硅结构。
在图7中概要说明用来实施包括Xe2 +离子植入的本发明实施方案的离子植入***的顶视平面图。如图所示，该离子植入***70包含来源腔室72、检偏镜磁铁74、加速器76和末端站78。提取电源供应器80电性连接至容纳于来源腔室内72的提取电极81以及离子来源(未显示)。加速电源供应器82电性分别连接至加速器76的相对两端的加速电极83和84。
在操作过程中，提取电极81从来源腔室72中提取入射离子束85。藉由检偏镜磁铁74分析入射离子束85，其中从离子束85中选择所要的离子种类。分析磁铁74释出经过分析的离子束86，并且将该离子束导向位于电极83的隙缝87。检偏镜磁铁74从入射离子束85中，除了一种所要的离子束以外，过滤掉全部的离子束。检偏镜磁铁74内部所产生的磁场会造成当离子束85之中的各个离子通过检偏镜磁铁74时，沿着拱形轨道行进。已知离子的轨道半径依该离子的质量和速度，以及检偏镜磁铁74内部的磁场强度而定。检偏镜磁铁74内部的机械阻碍会阻挡不具有能通过检偏镜磁铁74出口的适当曲率轨道的所有离子。因此，只有所要的离子(Xe2 +)能离开检偏镜磁铁74，而形成经过分析的离子束86。
进入入口隙缝87后，藉由加速器76加速经过分析的离子束86，并导向末端站78。一般认为工业用的离子植入***通常包含附加的聚焦***使该离子束在离开加速器76之后适当地聚焦。一般也认为可能有许多种不同的末端站结构，依照该离子植入***所能形成的特定离子束而定。
虽然藉由提取电极81可进行起始加速，但是可以藉由加速器76进一步地加速达到依所需要的植入深度而决定之特定的能量位准Xe2 +的提取电压通常在大约10KeV至大约80KeV(例如大约20KeV至大约50KeV)的范围。
在进行离子植入的过程中，将例如表体硅基板88的基板放置在末端站78内部，对准经过分析的离子束86。在实际进行离子植入之前，将末端站78抽真空，以便从硅基板88附近移除周围的气体。在Xe2 +植入的过程中，经过分析的离子束86通过电极84中的隙缝89离开。隙缝89可容许末端站78和加速器76之间进行气体传递。
根据本发明的实施方案，利用将提取电压操作在大约10KeV至大约50KeV之低值或更低值，可以最清晰地得到由Xe来源所产生的最大光谱。
图7所示基板88可为任何种类传统的基板，包含表体硅基板。采用Xe2 +使表体硅基板无定形化，形成源极/漏极延伸区域和源极/漏极区域的顺序与图1-4或图5和6所说明的顺序可以平行。一般认为图7所示的基板88亦可为SOI结构，并且可以使用Xe2 +进行与图1-4或图5和6中所说明的实施方案有关的Xe2 +离子植入。在实施Xe2 +离子植入的过程中，可以使用比实施Xe离子植入时，由于植入能量会分配给两个离子之较低的植入能量。因此，使用Xe2 +预无定形化时，可以有效地采用大约1KeV至大约200KeV的能量。
本发明能制造具有实际上不含或大幅降低浮体效应，并且能准确地将源极/漏极延伸区域和源极/漏极区域定位及定义尺寸之SOI结构的半导体装置。本发明也提供在具有例如小于大约400埃，不超过大约250埃的超浅层接面表体硅基板中能形成准确地将源极/漏极延伸区域和源极/漏极区域定位及定义尺寸的有效方法。利用Xe离子植入作为预无定形化能够优异地活化掺杂杂质，藉此提高装置的信赖性以及改善晶片对晶片的均匀度。
本发明具有在各种半导体装置制造上的产业应用性。本发明特别适合用来制造具有次微米特征的半导体装置。
在前述说明中提出许多明确的详细说明，例如特定材料、结构、化学药品、制程等，以提供对于本发明较佳之理解。然而，不需要藉由特别提出详细说明便能实施本发明。在其它情形中，并不详细叙述众所周知的工艺和材料，以避免不必要地模糊本发明。
在本发明揭示中仅表示及叙述本发明较佳实施方案及本发明的多种用途的少数实施例。据了解本发明可以用于其它各种组合和环境，并且可以在本文所示进步性概念的范畴内进行改变或修饰。

Claims (10)

1.一种半导体装置的制造方法，该方法包括：
形成一种硅绝缘层(SOI)结构(101)，其包括：
位于底部的硅基板(10)；
在基板上埋入的绝缘层(11)；以及
位于该绝缘层上之上结晶硅(12)层；
然后，将氙(Xe)离子(15)植入到上硅层(12)，以形成无定形区域(12A)，该无定形区域(12A)从上表面向埋入的绝缘层(11)延伸；
然后，植入离子掺杂杂质(20)，以形成源极/漏极延伸区域的植入物；
然后，退火以活化浅层源极/漏极延伸区域(21)，并且使无定形区域(12A)再结晶；
然后，将氙离子(30)植入上硅层，以形成无定形区域(12B)，该无定形区域(12B)从上表面向埋入的绝缘层(11)延伸；
然后，植入离子掺杂杂质(40)，以形成源极/漏极区域植入物，其与所述的植入离子掺杂杂质(20)以形成源极/漏极延伸区域植入物的步骤是分开进行的；以及，
然后，退火以活化源极/漏极区域(41)，并且使无定形区域(12B)再结晶。
2.根据权利要求1所述的方法，其中
以大约1×1014至大约5×1014离子/cm2的植入剂量及大约3KeV至大约150KeV的植入能量将氙离子(15，30)植入；以及
在大约500℃至大约650℃的温度退火，将源极/漏极延伸区域(21)和源极/漏极区域(41)活化，并且使无定形区域(12A，12B)再结晶。
3.根据权利要求1所述的方法，其中
在上硅层(12)之上隔着栅绝缘层(13)形成栅电极(14)；以及
在形成所述的源极/漏极延伸区域(21)之后以及在植入氙离子(30)以在临近源极/漏极延伸区域(21)的上硅层中形成所述的无定形区域(12B)之前，在栅电极(14)侧面上形成侧壁间隔片(30)()。
4.根据权利要求1所述的方法，其中
在上硅层(12)之上隔着栅绝缘层(13)形成栅电极(14)；在将掺杂杂质(40)植入到上硅层的无定形区域以形成所述的源极/漏极区域植入物之前，在栅电极(14)的侧面上形成侧壁间隔片(15)；
在将氙离子(15)植入所述的上硅层以形成无定形区域(12A)以及将所述的掺杂杂质(20)植入以形成源极/漏极延伸区域植入物之前，去除所述的侧壁间隔片(15)。
5.根据权利要求1所述的方法，其中所述的氙离子包括主要由氙离子二聚物Xe2+所构成的离子束。
6.一种制造半导体装置的方法，该方法包括：
提供主要由氙二聚物(Xe2 +)所构成的离子束；
然后，将Xe2 +植入到结晶半导体基板(10)，以使在该基板中的区域(12A，12B)无定形化；
然后，将离子掺杂杂质(20，40)植入到该无定形区域，以形成源极/漏极延伸区域植入物和源极/漏极区域植入物；以及
然后，退火以活化该源极/漏极延伸区域和源极/漏极区域，并且使该无定形区域再结晶。
7.根据权利要求6所述的方法，其中
提供主要由Xe2 +所构成的离子束；
从离子源提取第一Xe离子束；
分析该Xe离子束；
从该第一离子束选择单一带电的Xe2 +，形成主要由Xe2 +所构成的离子束；以及
在大约500℃至大约650℃的温度退火，使源极/漏极延伸区域和源极/漏极区域活化，并且使无定形区域再结晶。
8.根据权利要求6所述的方法，其中
将Xe2 +植入到结晶基板中以形成无定形区域，该无定形区域从该基板上表面延伸至不超过大约400埃的深度；
将掺杂杂质植入到经无定形化的区域，以形成源极/漏极区域植入物；
在大约500℃至大约650℃的温度退火，使源极/漏极延伸区域活化。
9.根据权利要求6所述的方法，进一步包括在该基板(10)上表面之上隔着栅绝缘层(13)形成栅电极(14)；
将离子掺杂杂质植入到该无定形区域，以形成源极/漏极延伸区域植入物；
退火以活化该源极/漏极延伸区域，并且使该无定形区域再结晶；
在源极/漏极延伸区域上方的栅电极侧表面上形成侧壁间隔片(30)；
植入Xe2 +，以形成毗邻该源极/漏极延伸区域的无定形区域；
将离子掺杂杂质植入到该无定形区域，形成源极/漏极区域植入物；以及
在大约500℃至大约650℃的温度退火，形成源极/漏极区域，并且使该无定形区域再结晶。
10.根据权利要求6所述的方法，进一步包括：
在基板(10)上表面之上隔着栅绝缘层(13)形成栅电极(14)；
在栅电极侧表面形成侧壁间隔片(15)；
将离子掺杂杂质植入到无定形区域，以形成隔开的源极/漏极区域植入物；
退火以活化源极/漏极区域，并且使该无定形区域再结晶；
移除该侧壁间隔片；
将Xe2 +植入到该基板，以无定形化栅电极侧表面和源极/漏极区域之间的区域；
将离子掺杂杂质植入到经无定形化的区域，以形成源极/漏极延伸区域植入物；以及
在大约500℃至大约650℃的温度退火，使源极/漏极延伸区域活化并且使该无定形区域再结晶。
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CN1539160A (zh) 2004-10-20
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EP1511071A2 (en) 2005-03-02
KR100880687B1 (ko) 2009-01-30
TWI228276B (en) 2005-02-21
JP4526819B2 (ja) 2010-08-18
US20030027381A1 (en) 2003-02-06
EP1419521B1 (en) 2007-09-26
US6624037B2 (en) 2003-09-23
DE60222675D1 (de) 2007-11-08
EP1419521A1 (en) 2004-05-19
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JP2004537856A (ja) 2004-12-16
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