CN1306592C - Laying-out designing device, method and program for semiconductor elements - Google Patents
Laying-out designing device, method and program for semiconductor elements Download PDFInfo
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- CN1306592C CN1306592C CNB2004100300182A CN200410030018A CN1306592C CN 1306592 C CN1306592 C CN 1306592C CN B2004100300182 A CNB2004100300182 A CN B2004100300182A CN 200410030018 A CN200410030018 A CN 200410030018A CN 1306592 C CN1306592 C CN 1306592C
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Abstract
Layout design method provided in the present invention could easily and accurately carry out a layout design of a semiconductor integrated circuit which contains elements need to be pair-assigned. The layout design method contain: step S10 to acquire the element type of the elements contained in the semiconductor integrated circuit, and the connection relationship between electrodes of the elements, step S12 to select a element contained in the semiconductor integrated circuit as targeted element in sequence, to find the elements which should be adjacently disposed with the targeted element based on the element type and connection relationship, and to assign the targeted element and the elements which should be adjacently disposed with the targeted element as pair-group, and step S14 to carry out the layout design of semiconductor integrated circuit by adjacently disposing the elements assigned as pair-group.
Description
Technical field
The present invention relates to the element of semiconductor integrated circuit is carried out layout designs device, layout design method and the layout designs program of layout.
Background technology
Requirement when semiconductor integrated circuit is applied to analog circuit can list the skew that reduces bucking voltage or gain.During the component placement that comprises in analog circuit, specific element is carried out suppressing bad to the circuit characteristic that the characteristic deviation of designated components causes by these to specifying by using layout tool.
Here, when being meant the layout designs of analog circuit, become than precision problem element to or group.Bipolar transistor or resistance for example about using in current mirror circuit or the differential amplifier circuit etc., when necessary choice has the element of similar characteristic, carry out element to specifying.At this moment, require voltage V between the base-emitter
BEThe ratio precision of ratio precision, resistance following for number mV for below the number %.
In order to realize these than precision, be necessary to carry out the layout of element, make in the access areas of paired element in semiconductor chip to same direction configuration.By will the element of appointment being configured in the approaching zone to same direction, can avoiding the skew of element characteristic in the same wafer that the skew of manufacturing process causes or size or become inhomogeneous from heat and The noise that periphery is subjected to.
In semiconductor integrated circuit,, on Semiconductor substrate, form elements such as transistor, resistance, electric capacity as Figure 19 and shown in Figure 20.Each element is formed on the epitaxial loayer that is separated by the separating layer 12 on Semiconductor substrate 10 surfaces and promptly is called in the zone on island 14.Separating layer 12 is connected electrically on the Semiconductor substrate 10, is potential minimum (GND) in semiconductor integrated circuit.Be that island 14 interior current potentials maintain also higher than the current potential of separating layer 12.
When the current potential in the island 14 was also lower than the current potential of separating layer 12, non-existent parasitic antenna among the forming circuit figure in semiconductor integrated circuit was because this parasitic antenna might carry out unexpected action.As a result, produce semiconductor integrated circuit and work improperly, can't bring into play the such problem of desired performance.Therefore, the current potential of island 14 and separating layer 12 must always be kept correct relation.
Here, the structure with regard to the frequent element that uses in the semiconductor integrated circuit is illustrated.Figure 19 (a) is the plane graph and the cutaway view of NPN transistor.NPN transistor is forming in the stacked N type epitaxial loayer of N type buried regions 16 on the Semiconductor substrate 10.Epitaxial loayer is by having added the P of high concentration p type impurity
+Separating layer 12 constitutes island 14 around surrounding.In island 14, be formed with the N type emitter region 22 in N type collector region 18, P type base 20 and the base 20.
Figure 19 (b) is transistorized plane graph of horizontal type PNP and cutaway view.Horizontal type PNP transistor is forming in the stacked N type epitaxial loayer of N type buried regions 16 on the Semiconductor substrate 10.Epitaxial loayer is by the P of high concentration
+Separating layer 12 constitutes island 14 around surrounding.Island 14 becomes N type base 20, adds p type impurity in this island 14, forms collector region 18 and emitter region 22.
Figure 19 (c) is transistorized plane graph of longitudinal type PNP and cutaway view.Longitudinal type PNP transistor is forming in the stacked epitaxial loayer of the buried regions 24 of the buried regions 16 of N type and P type on the Semiconductor substrate 10.Epitaxial loayer is by the P of high concentration
+Separating layer 12 constitutes island 14 around surrounding.In longitudinal type PNP transistor, the inboard that also surrounds this island 14 forms the P of high concentration
+Collector region 18.By the base 20 of these collector region 18 area surrounded, in this base 20, form the emitter region 22 of P type as the N type.
Figure 20 is the plane graph and the cutaway view of resistance.Resistance is forming in the stacked epitaxial loayer of the buried regions 16 of N type on the Semiconductor substrate 10.Epitaxial loayer is by the P of high concentration
+Separating layer 12 constitutes island 14 around surrounding.In island 14, become the P type resistive layer 24 of resistive element.On island 14 is in the N type epitaxial loayer electrode to be set, and this electrode is maintained than the highest also high current potential of voltage in the terminal voltage that is configured in the resistance in the island 14.Like this, be called and hang electrode 25, the current potential that hangs electrode 25 is called hangs current potential being arranged on electrode in the island 14.
As mentioned above, each element of formation semiconductor integrated circuit is formed on by P
+In the island 14 that separating layer 12 is surrounded.At this moment, by carrying out arrangements of components to appointment in same island 14, can avoid the influence of the element characteristic skew in the wafer that manufacture process causes.In addition, when not being the element that carries out appointment, carry out the islandization of a plurality of arrangements of components same island 14 in that satisfies specified criteria, by necessarily the current potential maintenance on the island of dividing by separating layer 12 14, can carry out electricity with other islands 14 and isolate, can stablize and carry out circuit operation.Sometimes also can obtain the advantage that reduces semiconductor chip size.
[patent documentation 1]
Te Kaiping 5-218202 communique
, in layout designs in the past, carry out element to specifying, or in the same island of a plurality of arrangements of components the time, the problem below existing.
1. because the element that uses is varied in the semiconductor integrated circuit,, takes place the wrong of appointment easily or forget that to specify the circuit characteristic that causes bad so be necessary that the combination of elements of carrying out appointment is huge.
2. in the layout operation, carry out element group to appointment always be necessary to be configured to or group, when when appointment has been realized desirable arrangements of components, when the downsizing of semiconductor chip was insufficient, layout designer was necessary manual the releasing specifying, and disposes element again.
3. when removing specifying, during the configuration element, after layout designs, layout operator is necessary to carry out whether appropriate configuration should be carried out the element of appointment is taken as industry really.Therefore, the layout operation becomes numerous and diverse, and the activity duration is elongated.In addition, according to the operator's who confirms operation ability, the offset of performance of semiconductor integrated circuit.
4. carry out the element of appointment is confined to the element of same kind, the configuration direction of element is identical, in order to suppress the characteristic deviation that technology causes, is necessary to consider approaching as far as possible configuration, and when carrying out these by hand, the burden that the layout operator is brought is big.
Summary of the invention
The present invention is in view of the problem of described layout designs, and in order to solve at least one of described problem, its purpose is: provide make element to specifying and layout becomes and is easy to layout designs device, layout design method and layout designs program.
The present invention that can solve described problem is a kind of layout designs device, by disposing a plurality of elements, carry out the layout of semiconductor integrated circuit, it is characterized in that: comprising: obtain the component type of a plurality of elements that comprise in the object of layout, the circuit information of interelectrode annexation that element has is obtained parts; The element that comprises in the object of layout is selected successively as paying close attention to element, according to described component type and described annexation, obtain and pay close attention to the element of element with this near configuration, this concerns element and should near the element of configuration be appointed as to organize to specified parts; Being appointed as described element configuration closer to each other, carry out the layout parts of layout to group.
The present invention that can solve described problem is a kind of layout designs device, by disposing a plurality of elements, carry out the layout of semiconductor integrated circuit, it is characterized in that: comprising: obtain the component type of a plurality of elements that comprise in the object of layout, the circuit information of interelectrode annexation that element has is obtained parts; The element that comprises in the object of layout is selected successively as paying close attention to element, according to described component type and described annexation, obtain the element that be configured in the island identical, this concern element and the element in should being configured in identical island are appointed as the island specified parts of island group with this concern element; The arrangements of components of being appointed as described island group in same island, is carried out the layout parts of layout.
Here, to obtain parts are parts of further obtaining the annexation of hanging current potential of element to described circuit information; Described layout parts are when the hanging current potential and equate of the whole elements that comprise in the group of described island, the parts that hang electrode that the parts number that configuration comprises in than this island group in the island of the element that comprises in this island group of configuration also lacks.
The present invention that can solve described problem is a kind of layout design method, by disposing a plurality of elements, carry out the layout of semiconductor integrated circuit, it is characterized in that: comprising: obtain the component type of a plurality of elements that comprise in the object of layout, the circuit information of interelectrode annexation that element has is obtained step; The element that comprises in the object of layout is selected successively as paying close attention to element, according to described component type and described annexation, obtain and pay close attention to the element of element with this near configuration, this concerns element and should near the element of configuration be appointed as to organize to given step; Being appointed as described element configuration closer to each other, carry out the layout step of layout to group.
The present invention that can solve described problem is a kind of layout design method, by disposing a plurality of elements, carry out the layout of semiconductor integrated circuit, it is characterized in that: comprising: obtain the component type of a plurality of elements that comprise in the object of layout, the circuit information of interelectrode annexation that element has is obtained step; The element that comprises in the object of layout is selected successively as paying close attention to element, according to described component type and described annexation, obtain the element that be configured in the island identical, this concern element and the element in should being configured in identical island are appointed as the island given step of island group with this concern element; The arrangements of components of being appointed as described island group in same island, is carried out the layout step of layout.
The present invention that can solve described problem is a kind of layout designs program, by disposing a plurality of elements, carry out the layout of semiconductor integrated circuit, it is characterized in that: computer is carried out comprise the processing of following steps, being comprised: obtain the component type of a plurality of elements that comprise in the object of layout, the circuit information of interelectrode annexation that element has is obtained step; The element that comprises in the object of layout is selected successively as paying close attention to element, according to described component type and described annexation, obtain and pay close attention to the element of element with this near configuration, this concerns element and should near the element of configuration be appointed as to organize to given step; Being appointed as described element configuration closer to each other, carry out the layout step of layout to group.
The present invention that can solve described problem is a kind of layout designs program, by disposing a plurality of elements, carry out the layout of semiconductor integrated circuit, it is characterized in that: computer is carried out comprise the processing of following steps, being comprised: obtain the component type of a plurality of elements that comprise in the object of layout, the circuit information of interelectrode annexation that element has is obtained step; The element that comprises in the object of layout is selected successively as paying close attention to element, according to described component type and described annexation, obtain the element that be configured in the island identical, this concern element and the element in should being configured in identical island are appointed as the island given step of island group with this concern element; The arrangements of components of being appointed as described island group in same island, is carried out the layout step of layout.
Here, to obtain step be further to obtain the step of the annexation of hanging current potential of element to described circuit information; Described layout step is when the hanging current potential and equate of the whole elements that comprise in the group of described island, the step of hanging electrode that the parts number that configuration comprises in than this island group in the island of the element that comprises in this island group of configuration also lacks.
According to the present invention, can obtain following effect.
By carry out automatically to or the appointment of islandization, can prevent specify error or forget appointment, the bad generation of circuit characteristic that skew that can the suppression element characteristic etc. causes.
When carry out to or during the island, to the rule of each component type decision configuration, thus can add the configuration direction unanimity that makes element automatically, as far as possible near the layout of considerations such as configuration element.
3. as principle, be that the element to appointment is carried out in the unit configuration automatically, when to block layout's optimization, have problems, only when removing, need layout operator's manual working appointment with the group.Therefore, operation becomes easily, can reduce job error.
4. confirm circuit database on one side or organize the content of registering in the database, can verify the result of layout designs on one side, so do not exist with ... layout operator's technology, can verify operation easily.
Description of drawings
Fig. 1 is the design of expression semiconductor integrated device and the flow chart of manufacturing.
Fig. 2 is the structured flowchart of the layout designs device of the expression embodiment of the invention.
Fig. 3 is the flow chart of the layout design method of the expression embodiment of the invention.
The register content of Fig. 4 indication circuit database.
Fig. 5 be expression carry out to the flow chart of the subprogram of the appointment of islandization.
The register content of Fig. 6 indication circuit database.
Fig. 7 represents to organize the register content of database.
The register content of Fig. 8 indication circuit database.
Fig. 9 represents to organize the register content of database.
Figure 10 represents the element of NPN transistor and the generation example of set of pieces.
Figure 11 represents the generation example of transistorized element of horizontal type PNP and set of pieces.
Figure 12 represents the generation example of transistorized element of longitudinal type PNP and set of pieces.
Figure 13 represents the element of resistance and the generation example of set of pieces.
Figure 14 is the flow chart that the subprogram of block layout is carried out in expression.
The islandization of Figure 15 illustrated block layout.
The islandization of Figure 16 illustrated block layout.
The islandization of Figure 17 illustrated block layout.
The islandization of Figure 18 illustrated block layout.
Figure 19 is the plane graph and the cutaway view of the various transistorized structure examples of expression.
Figure 20 is the plane graph and the cutaway view of the structure example of expression resistance.
The explanation of symbol.
The 10-Semiconductor substrate; The 12-separating layer; The 14-island; The 16-buried regions; The 18-collector region; The 20-base; The 22-emitter region; The 24-resistive layer; The 30-control part; The 32-input part; The 34-efferent; The 36-storage part; The 38-bus; The 40-interface portion; The 46-Disengagement zone; The 48-island; 50-hangs electrode; The 52-polygon; The 54-zone; The 56-zone; The protuberance in 58-zone; The 60-Disengagement zone; 62-hangs electrode.
Embodiment
The manufacturing of＜semiconductor chip 〉
With reference to design, the manufacturing flow chart of Fig. 1, illustrate the semiconductor integrated circuit group is gone into semiconductor chip manufacturing step before.In the system design of step S100, at first carry out the system design of semiconductor integrated circuit.Here, the basic demand specification of systems such as the necessary characteristic of decision-making circuit, chip size, design standard.Then, in the circuit design of step S102, specification is as requested used the circuit design of selection of components, interelement wiring etc.In the layout designs of step S104, carry out the element on the semiconductor wafer or the layout of wiring according to circuit diagram.In layout designs, pattern of the wiring between the configuration of element, Connection Element etc. is begun to write as layout, so that satisfy the basic specification of chip size, design standard etc.According to this layout, generate the mask pattern that uses in the manufacturing process.In step S106, confirm the result of layout designs, if the layout of compensating element is just fed back in the place of revising to layout designs.If necessary, with regard to feedback modifiers, up to the circuit design (component-level) of step S102.If no problem among the result of layout designs, just transfer to the manufacturing process of step S108.
In layout designs,, a plurality of elements are carried out, being necessary carry out the islandization in order to form a plurality of elements in same island to specifying in order to satisfy the characteristic of semiconductor integrated circuit.Before describing, illustrate and in layout designs, carry out the condition of appointment and the condition of energy islandization about these processing., carry out the condition of appointment and the condition of energy islandization are not limited thereto, can be according to the specification that requires of semiconductor integrated circuit, suitably change.
＜carry out condition〉to appointment
In semiconductor integrated circuit,, carry out the condition stub of appointment as follows to a plurality of elements in order to realize requiring specification.
1-1. when mutually each other NPN transistor, mutually horizontal each other type PNP transistor, mutually each other during longitudinal type PNP transistor
(1) mutual base stage, mutual emitter, when mutual collector electrode is connected on the same terminal.For example, list big output transistor.
When (2) mutual base stage, mutual emitter is connected on the same terminal.For example, list current mirror circuit.
(3) when mutual base stage is connected on the same terminal.For example list current mirror circuit.
When (4) mutual emitter is connected on the same terminal.For example list differential amplification input circuit.
When (5) mutual collector electrode is connected on the same terminal.
1-2. mutually each other during resistance
(1) is connected and carries out between the resistance on each transistorized same electrode of appointment.
(2) have between the resistance of syndeton of same series, parallel or combination.
(3) other special case.
The condition of＜energy islandization 〉
Below, in order to reduce semiconductor chip as far as possible, as follows the condition stub that a plurality of elements can be formed in the same island.
2-1. mutually each other during NPN transistor: equate with collector potential in order to make the island current potential, and when connecting between the collector electrode.
2-2. during mutually horizontal each other type PNP transistor: equate with base potential in order to make the island current potential, and when connecting between the base stage.
2-3. mutually each other during longitudinal type PNP transistor: in a plurality of elements, be added to hanging between the transistor that current potential equates on the island between collector region and the separating layer.
2-4. mutually each other during resistance: be added to hanging between the resistance that current potential equates on the island.
2-5. when longitudinal type PNP transistor and resistance: satisfy the condition of described 2-3 and 2-4, and the island of longitudinal type PNP transistor and resistance hang transistor and the resistance that current potential equates.
2-6. in addition, satisfy the condition of 2-1～2-5, and the island current potential has between the element of same structure.
＜layout designs 〉
Layout designs device of the present invention is made of control part 30, input part 32, efferent 34, storage part 36 and bus 38 as shown in Figure 2 basically.Control part 30, input part 32, efferent 34, storage part 36 are connected to energy transmission information by bus 38.The layout designs device can be realized by the hardware configuration of all-purpose computer.
In addition, become possibility, wish to comprise interface portion 40 in order to make the information exchange with outer computer.By interface portion 40, be connected to energy transmission information with external network, receive the necessary data of layout designs from the external device (ED) that is connected on the network, or a result who obtains in layout designs is outputed to external device (ED).
The user interface images of efferent 34 when showing from the various information of input part 32 inputs, or use during the affirmation picture of intermediate object program in display layout's design and final layout.As efferent 34, for example can use display, printer etc.
Result that storage part 36 forever or temporarily stores and keep the various information of OS, layout designs program, input, obtained by processing etc.The data or the program that are stored in the storage part 36 can suitably be consulted from control part 30 by bus 38.As storage part 36, can use semiconductor memory, hard disk, floppy disk, photomagneto disk, tape etc.
Below, with reference to the flow chart of Fig. 3, describe each step of layout designs in detail.Below each step of Biao Shi layout designs is programmed for the program that can be carried out by computer, this procedure stores with remain in the storage part 36, handles by being carried out by control part 30.
In the following description, carry out to the condition of appointment and condition that can the islandization in advance as database storage in storage part 36 so that can consult from control part 30.
In step S10, obtain information about circuit diagram by the circuit design decision.In information, comprise the component information of representing component specification and the link information of representing the element annexation about circuit diagram.In the information about the circuit diagram obtained, component information comprises the layout patterns shape of component type, component size, each element etc., link information comprise element electrode node, hang the node of electrode etc.Component information and link information are as shown in Figure 4, and be related with the element number of distributing to each element, stores in the storage part 36 as circuit database.
In step S12, carry out becoming to the processing of specifying and the element of the object of islandization divides into groups each other.In step S12, carrying out after element to appointment divides into groups each other, the element of islandization is divided into groups each other.Step S12 subroutinization, carry out along the flow chart of Fig. 5.
At first, consult the database of circuit,, select, obtain this component type (S12-1) as paying close attention to element according to the element number order.Here, which of NPN transistor, horizontal type PNP transistor, longitudinal type PNP transistor, resistance, electric capacity or other particular components types the component type of decision concern element be equivalent to.
Below, consult circuit database, each electrode of retrieval and concern element has other elements of the electrode that is connected on the same node.As a result, when the annexation of the element of retrieval and the electrode of paying close attention to element satisfies condition to appointment, these elements groupings (S12-2).At this moment, to each component type, decision is for the priority to appointment, and according to priority, the element to appointment is carried out in decision.
For example, when the NPN transistor of selecting element number Q1 from the example of circuit database shown in Figure 4 when paying close attention to element, decision is the node 1,6,10 of splicing ear 1 (collector electrode), terminal 2 (base stage), terminal 3 (emitter) respectively, and the retrieval electrode is connected other elements on the node 1,6,10.As a result, select the NPN transistor of element number Q2 and Q3.Then, the annexation of the element of element and selection is paid close attention in investigation.At this moment, be equivalent to described to specified requirements 1-1, be NPN transistor each other, base stage each other, emitter each other, collector electrode is connected the condition on the same terminal separately from each other, so the NPN transistor of the concern element of element number Q1 and element number Q2 and Q3 is organized into groups.
Equally, element is selected successively as paying close attention to element, repeated to satisfy grouping (S12-3) the element of specified requirements from circuit database.
Here, give expression this intrinsic to appointment to the element of appointment to group name to carrying out, as shown in Figure 6, for each element registration of circuit database to group name.In addition, wish the attribute conduct to group is registered type.As shown in Figure 7, new life's database in groups in storage part 36, with related to group name, registration and this element number (S12-4) to the element that comprises in the corresponding group of group name.At this moment, group name is wished for can be to the name of each component type classification.
Then, from circuit database element is selected (S12-5) as paying close attention to element.Judge that whether the electrode of the element that comprises in each group identical with this concern element satisfies the condition of islandization, for the element that satisfies condition, specifies islandization (S12-6).At this moment, consult the group database, with the concern element associated, when registering group name, about having the whole elements that comprise in this group to group name, whether investigation satisfies the island condition.For the whole elements that comprise in the group, when satisfying the island condition,, specify the islandization for these elements.
In order the element of registering in the circuit database is selected as paying close attention to element, whether had other elements (S12-7) that satisfy the island condition for paying close attention to the element investigation.
Here, give the intrinsic island group name of its group of expression to the element of specifying the islandization, as shown in Figure 8, to each element registration island group name of circuit database.In addition, as shown in Figure 9, when the element that has carried out the island appointment belongs to arbitrarily group, with related to group name, the having or not of registration islandization, island group name and hang the node (S12-8) of electrode in the group database.
More than, the processing of the subprogram of step S12 finishes, and then enters step S14.
In step S14, according to registration to the circuit database of the appointed information of islandization with organize database, correction circuit figure.The circuit diagram of revising also can be called the circuit map generalization of having considered layout.
The circuit diagram of revising uses in element generation and set of pieces generation.Element generates size, the shape be meant inscapes such as each size of component, shape, doped region or electrode, is configured.Set of pieces generates and to be meant according to the having or not of appointment, and is adjacent to same direction configuration a plurality of elements, or according to the having or not of island appointment, and a plurality of arrangements of components in same island, or according to the having or not of island node, are disposed in the island of islandization and hang electrode.
Generating and the set of pieces generation about element, is example with the NPN transistor, describes.When for element number Q1, Q2, Q3, when not carrying out, shown in Figure 10 (a), to size, shape and the configuration of each element decision doped region, electrode to appointment and island appointment, each arrangements of components is separating each other, respectively in the island 48 that is surrounded by the Disengagement zone 46 of separation independently of one another.When not specifying the islandization, only carry out when specifying, shown in Figure 19 (b), in the adjacent area of each element on semiconductor chip,, but be configured in respectively independently in the island 48 to same direction configuration.When specifying to the time, shown in Figure 10 (c), in the adjacent area of each arrangements of components on semiconductor chip, and be configured in the same island 48 by 46 encirclements of common Disengagement zone with the island both sides.
Dispose element too in horizontal type PNP transistor, expression is not when to the appointment of islandization the time in Figure 11 (a), and representing among Figure 11 (b) has appointment, when not having the island appointment, in Figure 11 (c), represents to have to the appointment of islandization the time.
In longitudinal type PNP transistor, the configuration element, Figure 12 (a) expression is not to the appointment of islandization the time, and Figure 12 (b) expression has to appointment, when not having the island appointment.At this moment, the island separate configurations of each element is hung electrode 50.As to the appointment of islandization the time, whether electrode 50 is shared according to hanging, and changes to handle.Hang electrode when shared when making, shown in Figure 12 (c), (d), for be configured in whole arrangements of components in the same island 48 shared hang electrode 50.When hanging electrode 50 when not shared, shown in Figure 12 (d), with each element associated that is configured in the same island 48, electrode 50 is hung in configuration.
Dispose element in resistance too, Figure 13 (a) expression is not to the appointment of islandization the time, and Figure 13 (b) expression has to appointment, when not having the island appointment.In addition,, hang electrode when shared, resemble and dispose element Figure 13 (c), (d), hang electrode when shared, resemble and dispose element Figure 13 (d) when not making when making as to the time with the island appointment.
Then, in step S16,, carry out the block layout that carries out all layouts of semiconductor integrated circuit and handle according to the result that element generates and set of pieces generates.Can be along flow chart execution block layout shown in Figure 14.
In the step S16-1 of subprogram, by the automatic configuration tool of selling on the market, according to the element or the set of pieces of circuit diagram configuration generation., replace using automatic configuration tool, also can use same CAD system, layout designer is manual to be configured.
In step S16-2, in order to satisfy the specification that requires of semiconductor chip size, shape etc., can judgement dispose element or set of pieces.When the configuration of element or set of pieces meets the demands specification, step S16-3 is transferred in processing.When not meeting the demands specification, at step S16-4, the register content of manual correction circuit database of layout designer and group database, the element of getting back to the step S14 of main program generates and the set of pieces generation, repeats described processing, up to the specification that meets the demands.
In the moment of the configuration end of job of element that generates and set of pieces, finish fully for islandization except the component type of longitudinal type PNP transistor and resistance., longitudinal type PNP transistor and resistance can be configured in the same island with hanging element or the set of pieces that current potential equates, so carry out in step S16-3 the processing in the same island of the element that satisfies condition or configuration set.
Situation when at first, the semi-automatic processing being described.Layout designer is specified a plurality of current potentials that hang to equate, and is carried out the element and the set of pieces of islandization with reference to circuit diagram etc.For example, as shown in figure 15, in the display frame of display etc., be presented at the element that block layout obtains in handling or the configuration of set of pieces, use pointing devices such as mouse, specify definite encirclement to hang current potential and equate, and 2 points (A point and B point among the figure) of the polygon 52 (rectangle) of the element of energy islandization and set of pieces.If specify polygon 52, just be chosen in and comprise its a part of element and set of pieces in this polygon 52 at least, with reference to circuit database and group database, obtaining only encirclement from the element selected and set of pieces, to hang electrode be the shared element and the zone 54 (Figure 16) of set of pieces.Here, when having carried out the element of appointment just thought to be included in the polygon 52 to the whole elements that comprise in organizing, select the element that comprises in this group.Then, the processing of dwindling of figure is carried out in zone 54.At this moment, layout designer 54 boundary line, zone only in zone 54 side direction move in advance the reduced width (for example ,-2 μ m) of setting such as specification as requested.Handle according to this,, can delete protuberance 58 not for example as the zone 56 of Figure 17.At last, as shown in figure 18, surround the zone 56 that dwindles processing Disengagement zone 60 is set, in the Disengagement zone, hang electrode 62, carry out the islandization of element and set of pieces according to necessity configuration.If islandization necessary in the semiconductor chip is all over, just processing is got back to the step S18 of main program.
Comprise the element that comprises in the semiconductor chip and whole zone of set of pieces by appointment, carry out above processing automatically.
In step S18, the link information according to circuit database and group database is configured element in semiconductor chip and the wiring between set of pieces.In wiring, can use auto-placement tool that has existed etc.
In step S20, verify operation.The checking operation is carried out automatically or with the visual of layout operator according to DRC (Design Rule Checking) or LVS (layout and electrical schematic diagram consistency check).At this moment, Yi Bian confirm the content of circuit database or group database, Yi Bian verify operation.Here,, just make to handle and get back to step S12, carry out layout designs once again if having problems in the layout result.
Claims (6)
1. layout designs device by disposing the layout that a plurality of elements carry out semiconductor integrated circuit, is characterized in that: comprising:
Obtain the circuit information of annexation between the component type of a plurality of elements that comprise in the layout object and electrode that element has and obtain parts;
To specified parts, the element that comprises in the layout object is selected successively as paying close attention to element, obtain and pay close attention to the element of element with this according to described component type and described annexation, this concerns element with should be appointed as organizing near the element of configuration near configuration;
Being appointed as the described element layout parts that are configured to carry out layout closer to each other to group.
2. layout designs device by disposing the layout that a plurality of elements carry out semiconductor integrated circuit, is characterized in that: comprising:
Obtain the circuit information of annexation between the component type of a plurality of elements that comprise in the layout object and electrode that element has and obtain parts;
The island specified parts, the element that comprises in the layout object is selected successively as paying close attention to element, obtain and pay close attention to the element of arrangements of components in same island with this according to described component type and described annexation, this concern element and the element that should be configured in this same island are appointed as the island group;
The element of being appointed as described island group is configured in the same island each other to carry out the layout parts of layout.
3. layout designs device according to claim 2 is characterized in that:
It is further to obtain the parts that element hangs the annexation of current potential that described circuit information is obtained parts;
Described layout parts are when the hanging current potential and equate of the whole elements that comprise in the group of described island, the parts that hang electrode that configuration is also lacked than the parts number that comprises in this island group in the island of the element that comprises in disposing this island group.
4. layout design method by disposing the layout that a plurality of elements carry out semiconductor integrated circuit, is characterized in that: comprising:
Obtain the circuit information of annexation between the component type of a plurality of elements that comprise in the layout object and electrode that element has and obtain step;
To given step, the element that comprises in the layout object is selected successively as paying close attention to element, obtain and pay close attention to the element of element with this according to described component type and described annexation, this concerns element with should be appointed as organizing near the element of configuration near configuration;
Being appointed as the described element layout step that is configured to carry out layout closer to each other to group.
5. layout design method by disposing the layout that a plurality of elements carry out semiconductor integrated circuit, is characterized in that: comprising:
Obtain the circuit information of annexation between the component type of a plurality of elements that comprise in the layout object and electrode that element has and obtain step;
The island given step, the element that comprises in the layout object is selected successively as paying close attention to element, obtain and pay close attention to the element of arrangements of components in same island with this according to described component type and described annexation, this concern element and the element that should be configured in this same island are appointed as the island group;
The element of being appointed as described island group is configured in the same island each other to carry out the layout step of layout.
6. layout design method according to claim 5 is characterized in that:
It is further to obtain the step that element hangs the annexation of current potential that described circuit information is obtained step;
Described layout step is when the hanging current potential and equate of the whole elements that comprise in the group of described island, the step of hanging electrode that configuration is also lacked than the parts number that comprises in this island group in the island of the element that comprises in disposing this island group.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP071358/2003 | 2003-03-17 | ||
| JP2003071358A JP2004280493A (en) | 2003-03-17 | 2003-03-17 | Layout design device, layout design method and layout design program for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1534765A CN1534765A (en) | 2004-10-06 |
| CN1306592C true CN1306592C (en) | 2007-03-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100300182A Expired - Fee Related CN1306592C (en) | 2003-03-17 | 2004-03-17 | Laying-out designing device, method and program for semiconductor elements |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2004280493A (en) |
| CN (1) | CN1306592C (en) |
| TW (1) | TWI240354B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102682161B (en) * | 2012-04-18 | 2015-04-01 | 南阳理工学院 | Method for arranging component of interface chip |
| CN102682648B (en) * | 2012-04-18 | 2014-01-01 | 南阳理工学院 | Method for distributing components of experiment box used for principles of computer composition |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218202A (en) * | 1992-02-07 | 1993-08-27 | Matsushita Electric Ind Co Ltd | Forming apparatus for mask data of semiconductor element |
| US5761075A (en) * | 1993-12-28 | 1998-06-02 | Kabushiki Kaisha Toshiba | Apparatus for designing photomasks |
| CN1204148A (en) * | 1997-06-26 | 1999-01-06 | 西门子公司 | Integrated circuit devices including shallow trench isolation |
| CN1207582A (en) * | 1997-08-01 | 1999-02-10 | 三菱电机株式会社 | Layout pattern of memory cell circuit |
| JP2000067094A (en) * | 1998-08-21 | 2000-03-03 | Nec Corp | Method and device for designing circuit layout |
-
2003
- 2003-03-17 JP JP2003071358A patent/JP2004280493A/en active Pending
-
2004
- 2004-02-27 TW TW93105050A patent/TWI240354B/en active
- 2004-03-17 CN CNB2004100300182A patent/CN1306592C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218202A (en) * | 1992-02-07 | 1993-08-27 | Matsushita Electric Ind Co Ltd | Forming apparatus for mask data of semiconductor element |
| US5761075A (en) * | 1993-12-28 | 1998-06-02 | Kabushiki Kaisha Toshiba | Apparatus for designing photomasks |
| CN1204148A (en) * | 1997-06-26 | 1999-01-06 | 西门子公司 | Integrated circuit devices including shallow trench isolation |
| CN1207582A (en) * | 1997-08-01 | 1999-02-10 | 三菱电机株式会社 | Layout pattern of memory cell circuit |
| JP2000067094A (en) * | 1998-08-21 | 2000-03-03 | Nec Corp | Method and device for designing circuit layout |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1534765A (en) | 2004-10-06 |
| TWI240354B (en) | 2005-09-21 |
| TW200423286A (en) | 2004-11-01 |
| JP2004280493A (en) | 2004-10-07 |
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