CN1295870C

CN1295870C - A clock frequency multiplier circuit

Info

Publication number: CN1295870C
Application number: CNB2004100049993A
Authority: CN
Inventors: 张磊; 黄友珍
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2004-02-13
Filing date: 2004-02-13
Publication date: 2007-01-17
Anticipated expiration: 2024-02-13
Also published as: CN1558553A

Abstract

The present invention discloses a clock frequency multiplication circuit, particularly a clock frequency multiplication circuit in circuit design and programmable logic devices. The clock frequency multiplication circuit comprises a base module of the frequency multiplication circuit, and a time delay triggering part, wherein the base module of the frequency multiplication circuit is the first stage of the frequency multiplication circuit. The time delay triggering part is connected in series with the base module of the frequency multiplication circuit, and is composed of a time delay triggering module or is formed by the series connection of a plurality of time delay triggering modules. The base module of the frequency multiplication circuit provides the input and output of frequency multiplication signals and an interface with a rear-stage time delay triggering module; the time delay triggering module makes the falling edge position of a clock after frequency is multiplied rearward shift to achieve the effects of synchronizing and broadening clock width. The present invention can obtain stable and constant phase frequency multiplication clock under the conditions of low cost and high compatibility, and can overcome the defect that the prior art does not simultaneously give attention to the conditions.

Description

A kind of clock multiplier circuit

Technical field

The present invention relates to a kind of clock multiplier circuit, especially relate to the clock multiplier circuit in the design of circuit design and programmable logic device.

Background technology

Clock multiplier circuit is a kind of common circuit in circuit design and programmable logic device design.

In existing circuit design and programmable logic device design, the implementation method of clock multiplier circuit has following several:

1. with the another one high-frequency clock clock sampling that needs frequency multiplication is counted the clock after the output frequency multiplication.The shortcoming of this method is, because high-frequency clock and input clock are nonsynchronous, makes clock and the input clock phase relation exported after the frequency multiplication uncertain.This frequency-doubling method can not use in many instances.Owing to need another high-frequency clock, increased the wiring complexity of circuit board simultaneously.

2. realize simple frequency multiplication with single d type flip flop and single XOR gate.The shortcoming of this method is that the clock width of exporting after the frequency multiplication is very narrow, can't widen.If adopt outside simple logic device frequency multiplication in this way in circuit design, the burr that produces on the clock width of output and the signal is similar, and behind the circuit board cabling, clock quality can be very poor, can't use.If frequency multiplication in this way in programmable logic device design, because the logical device internal speed is fast, its inner frequency doubling clock width that produces is narrower, if output to the device outside, can be sponged by the input capacitance of peripheral components, perhaps externally only see a little burr in the input of device, can't use.This frequency-doubling method can not use in many instances.

3. use the modulus hybrid circuit that constitutes by analogue devices such as digital logic device and capacitance-resistance, transistors to realize frequency multiplication.The shortcoming of this method is that the circuit that analogue device is formed can only be used for certain section specific frequency, as 10MHz-30MHz to limited bandwidth system; Owing to there is analogue device, design can't realize in programmable logic device, increase system complexity simultaneously.

4. realize frequency multiplication with PHASE-LOCKED LOOP PLL TECHNIQUE, comprise analog phase-locked look and digital delay locked loop.This method can be exported frequency doubling clock stable, that the input and output phase relation is constant, but the shortcoming of this method is that phase-locked loop has certain bandwidth, and the frequency range of input clock is had requirement, a device can't compatible differ bigger frequency, and Change In Design is restricted; Particularly to the programmable logic device of band phase-locked loop, can't be simultaneously to height differ bigger two kinds of frequencies and carry out frequency multiplication (as simultaneously to below the 10MHz and two kinds of frequency frequencys multiplication more than the 30MHz); And the use PHASE-LOCKED LOOP PLL TECHNIQUE, circuit resource takies greatly, the design cost height.

Summary of the invention

The technical problem that the present invention solves is the shortcoming that overcomes in the prior art in the clock multiplier design separately, solves that the clock multiplier that exists in the prior art is can't simultaneous adaptation stable, phase place is constant, highly compatible, problem cheaply.

In order to reach above purpose, the present invention adopts following technical scheme:

Clock multiplier circuit of the present invention, comprise frequency multiplier circuit basic module and time-delay triggering part, the frequency multiplier circuit basic module is the first order of frequency multiplier circuit, the time-delay triggering part comprises the time-delay trigger module, link to each other in turn with the frequency multiplier circuit basic module, the frequency multiplier circuit basic module provide frequency-doubled signal input, output and and the interface of back level time-delay trigger module, the time-delay trigger module moves after making the trailing edge position of clock after the frequency multiplication, realizes synchronously and widens the clock width.The time-delay triggering part is made of a time-delay trigger module or is made of a plurality of time-delay trigger module series connection.

Wherein said frequency multiplier circuit basic module inside comprises main frequency multiplier circuit, constitute main frequency multiplier circuit by first XOR gate and a T trigger, the output of first XOR gate is connected to the input end of clock of a T trigger, its signal flow is to being divided into two-way: the first via: after treating that frequency doubling clock passes through the output of first XOR gate, again by a T trigger, initial trailing edge after the output frequency multiplication, treat that next stage postpones trigger module and handles, the second the tunnel: move trailing edge after first XOR gate is mixed after treating frequency doubling clock and postponing that trigger module returns, without a T trigger, directly export the clock behind the frequency multiplication broadening.

Described time-delay trigger module inside comprises delay circuit, constitute delay circuit by second XOR gate, the 2nd T trigger and the 3rd T trigger, the output of second XOR gate is connected to the input end of clock of the second and the 3rd T trigger, the T output of the 2nd T trigger is connected to an input of XOR gate simultaneously, its signal flow is to being: after the initial trailing edge of frequency multiplier circuit basic module output passes through whole delay circuit, and the clock signal of moving trailing edge after the output.

The present invention adopts full-digital circuit to realize, does not need outside high-frequency clock, has simplified the circuit board wiring requirement; Do not use PHASE-LOCKED LOOP PLL TECHNIQUE, it is few to take resource, realizes that cost is low; Can realize that with logical device independently be more suitable in realizing in programmable logic device that with hardware description languages such as Verilog, VHDL the frequency doubling clock of output and input clock phase place are constant, octave band is roomy, can from below the 1KHz to more than the 50MHz.The present invention can obtain the frequency doubling clock stable, that phase place is constant under the condition of low-cost, highly compatible, overcome the shortcoming that prior art can't be taken into account these several conditions simultaneously.

Description of drawings

Fig. 1 is general principles figure of the present invention

Fig. 2 is a frequency multiplier circuit basic module schematic diagram of the present invention

Fig. 3 is a delay trigger module schematic diagram of the present invention

Fig. 4 is the schematic diagram of one embodiment of the present of invention

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further details.

As shown in Figure 1, clock multiplier circuit of the present invention, comprise frequency multiplier circuit basic module and time-delay triggering part, the frequency multiplier circuit basic module is the first order of frequency multiplier circuit, the time-delay triggering part links to each other in turn with the frequency multiplier circuit basic module, can be constituted or is made of a plurality of time-delay trigger module series connection by a time-delay trigger module.

The frequency multiplier circuit basic module provide frequency-doubled signal input, output and and the interface of back level time-delay trigger module, the time-delay triggering part moves after making the trailing edge position of clock after the frequency multiplication, reaches synchronously and the effect of widening the clock width.

The signal flow of whole device is to being such: after the clock signal 101 for the treatment of frequency multiplication enters the frequency multiplier circuit basic module, by main frequency multiplier circuit, initial trailing edge 105 after the output frequency multiplication, enter the delay triggering part, through behind the delay circuit, the trailing edge 106 that moves behind the outgoing position turns back to the frequency multiplier circuit basic module, mix the clock 102 behind the generation frequency multiplication broadening with treating frequency-doubled signal 101.

The frequency multiplier circuit basic module constitutes main frequency multiplier circuit by first XOR gate 201 and a T trigger 202 as shown in Figure 2, and the output of first XOR gate 201 is connected to the input end of clock of a T trigger 202, and its signal flow is to being divided into two-way:

The first via: after treating that frequency doubling clock signal 101 is by 201 outputs of first XOR gate, again by a T trigger 202, initial trailing edge 105 after the output frequency multiplication treats that next stage postpones trigger module and handles.

The second the tunnel: move trailing edge signal 106 after first XOR gate 201 is mixed after treating frequency doubling clock signal 101 and postponing that trigger module returns,, directly export the clock 102 behind the frequency multiplication broadening without a T trigger 202.

Postpone trigger module as shown in Figure 3 and constitute delay circuit by second XOR gate 301 and two T triggers 302,303, the output of second XOR gate 301 is connected to the input end of clock of two T triggers, and the T output of the 2nd T trigger 302 is connected to input 1 end of XOR gate simultaneously.

Its signal flow is to being: the initial trailing edge 105 of frequency multiplier circuit basic module output, behind whole delay circuit, move the clock signal 106 of trailing edge after the output.

Time-delay trigger module among the present invention can be a plurality of the series connection back link to each other in turn with the frequency multiplier circuit basic module, as shown in Figure 4 be exactly two embodiment that the time-delay trigger module is connected.

Fig. 4 is 2 grades of embodiment block diagrams that postpone trigger module of series connection, is made of the first order frequency multiplier circuit basic module 103 that links to each other in turn and 2 grades of delay trigger modules 401,402.Treat frequency doubling clock signal 101, through behind the whole device, the clock 102 after the output frequency multiplication.2 grades of time-delay trigger modules can obtain wideer frequency doubling clock owing to connected.

T trigger among the present invention also can substitute with d type flip flop, and its principle is basic identical, does not repeat them here.

Should be understood that; for those of ordinary skills; can be equal to change or replacement by technical conceive according to the present invention, and all this change of extra creative work or protection ranges that alternative all should belong to claims of the present invention of need not.

Claims

1. clock multiplier circuit, it is characterized in that comprising frequency multiplier circuit basic module and time-delay triggering part, the frequency multiplier circuit basic module is the first order of frequency multiplier circuit, the time-delay triggering part comprises the time-delay trigger module, link to each other in turn with the frequency multiplier circuit basic module, the frequency multiplier circuit basic module provide frequency-doubled signal input, output and and the interface of back level time-delay trigger module, the time-delay trigger module moves after making the trailing edge position of clock after the frequency multiplication, realizes synchronously and widens the clock width;

Described frequency multiplier circuit basic module inside comprises main frequency multiplier circuit, constitute main frequency multiplier circuit by first XOR gate and a T trigger, the output of first XOR gate is connected to the input end of clock of a T trigger, its signal flow is to being divided into two-way: the first via: after treating that frequency doubling clock passes through the output of first XOR gate, again by a T trigger, initial trailing edge after the output frequency multiplication, treat that next stage postpones trigger module and handles, the second the tunnel: move trailing edge after first XOR gate is mixed after treating frequency doubling clock and postponing that trigger module returns, without a T trigger, directly export the clock behind the frequency multiplication broadening;

2. clock multiplier circuit as claimed in claim 1 is characterized in that described time-delay triggering part is made of a time-delay trigger module or is made of a plurality of time-delay trigger module series connection.

3. clock multiplier circuit as claimed in claim 1 or 2 is characterized in that described T trigger can substitute with d type flip flop.